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From: Aditya Gupta <adityag@linux.ibm.com>
To: Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
Madhavan Srinivasan <maddy@linux.ibm.com>,
Nicholas Piggin <npiggin@gmail.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>,
=?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= <fbarrat@linux.ibm.com>
Cc: <qemu-devel@nongnu.org>, <qemu-ppc@nongnu.org>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PATCH v7 4/7] ppc/pnv: Add PHB5 PCIe Host bridge to Power11
Date: Fri, 28 Mar 2025 01:37:35 +0530
Message-ID: <20250327200738.1524401-5-adityag@linux.ibm.com>
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Power11 also uses PHB5, same as Power10.
Add Power11 PHBs with similar code as the corresponding Power10 implementat=
ion.
Cc: Fr=C3=A9d=C3=A9ric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 982decc11386..8b92ad11ae8e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -973,6 +973,8 @@ static void pnv_chip_power11_pic_print_info(PnvChip *ch=
ip, GString *buf)
=20
pnv_psi_pic_print_info(&chip11->psi, buf);
pnv_xive2_pic_print_info(&chip11->xive, buf);
+ object_child_foreach_recursive(OBJECT(chip),
+ pnv_chip_power9_pic_print_info_child, buf);
}
=20
/* Always give the first 1GB to chip 0 else we won't boot */
@@ -2373,6 +2375,7 @@ static void pnv_chip_power10_realize(DeviceState *dev=
, Error **errp)
=20
static void pnv_chip_power11_instance_init(Object *obj)
{
+ PnvChip *chip =3D PNV_CHIP(obj);
Pnv11Chip *chip11 =3D PNV11_CHIP(obj);
PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(obj);
int i;
@@ -2395,6 +2398,13 @@ static void pnv_chip_power11_instance_init(Object *o=
bj)
object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
TYPE_PNV_N1_CHIPLET);
=20
+ chip->num_pecs =3D pcc->num_pecs;
+
+ for (i =3D 0; i < chip->num_pecs; i++) {
+ object_initialize_child(obj, "pec[*]", &chip11->pecs[i],
+ TYPE_PNV_PHB5_PEC);
+ }
+
for (i =3D 0; i < pcc->i2c_num_engines; i++) {
object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I=
2C);
}
@@ -2427,6 +2437,38 @@ static void pnv_chip_power11_quad_realize(Pnv11Chip =
*chip11, Error **errp)
}
}
=20
+static void pnv_chip_power11_phb_realize(PnvChip *chip, Error **errp)
+{
+ Pnv11Chip *chip11 =3D PNV11_CHIP(chip);
+ int i;
+
+ for (i =3D 0; i < chip->num_pecs; i++) {
+ PnvPhb4PecState *pec =3D &chip11->pecs[i];
+ PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec);
+ uint32_t pec_cplt_base;
+ uint32_t pec_nest_base;
+ uint32_t pec_pci_base;
+
+ object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
+ object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
+ &error_fatal);
+ object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
+ &error_fatal);
+ if (!qdev_realize(DEVICE(pec), NULL, errp)) {
+ return;
+ }
+
+ pec_cplt_base =3D pecc->xscom_cplt_base(pec);
+ pec_nest_base =3D pecc->xscom_nest_base(pec);
+ pec_pci_base =3D pecc->xscom_pci_base(pec);
+
+ pnv_xscom_add_subregion(chip, pec_cplt_base,
+ &pec->nest_pervasive.xscom_ctrl_regs_mr);
+ pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
+ pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
+ }
+}
+
static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev);
@@ -2556,7 +2598,12 @@ static void pnv_chip_power11_realize(DeviceState *de=
v, Error **errp)
pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_ES_BASE,
&chip11->n1_chiplet.xscom_pb_es_mr);
=20
- /* WIP: PHB added in future patch */
+ /* PHBs */
+ pnv_chip_power11_phb_realize(chip, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
=20
/*
* I2C
@@ -2690,6 +2737,7 @@ static void pnv_chip_power11_class_init(ObjectClass *=
klass, void *data)
k->xscom_core_base =3D pnv_chip_power11_xscom_core_base;
k->xscom_pcba =3D pnv_chip_power11_xscom_pcba;
dc->desc =3D "PowerNV Chip Power11";
+ k->num_pecs =3D PNV10_CHIP_MAX_PEC;
k->i2c_num_engines =3D PNV10_CHIP_MAX_I2C;
k->i2c_ports_per_engine =3D i2c_ports_per_engine;
=20
@@ -3280,6 +3328,13 @@ static void pnv_machine_power11_class_init(ObjectCla=
ss *oc, void *data)
XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc);
static const char compat[] =3D "qemu,powernv11\0ibm,powernv";
=20
+ static GlobalProperty phb_compat[] =3D {
+ { TYPE_PNV_PHB, "version", "5" },
+ { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
+ };
+
+ compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat=
));
+
pmc->compat =3D compat;
pmc->compat_size =3D sizeof(compat);
pmc->max_smt_threads =3D 4;
--=20
2.49.0