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From: Aditya Gupta <adityag@linux.ibm.com>
To: Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
Madhavan Srinivasan <maddy@linux.ibm.com>,
Nicholas Piggin <npiggin@gmail.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>,
=?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= <fbarrat@linux.ibm.com>
Cc: <qemu-devel@nongnu.org>, <qemu-ppc@nongnu.org>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
Subject: [PATCH v7 2/7] ppc/pnv: Introduce Power11 PowerNV machine
Date: Fri, 28 Mar 2025 01:37:33 +0530
Message-ID: <20250327200738.1524401-3-adityag@linux.ibm.com>
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The Powernv11 machine doesn't have XIVE & PHBs as of now
XIVE2 interface and PHB5 added in later patches to Powernv11 machine
Also add mention of Power11 to powernv documentation
Note: A difference from P10's and P11's machine_class_init is, in P11
different number of PHBs cannot be used on the command line, ie. the
following line does NOT exist in pnv_machine_power11_class_init, which
existed in case of Power10:
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
Cc: Fr=C3=A9d=C3=A9ric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@redhat.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
docs/system/ppc/powernv.rst | 9 +++++----
hw/ppc/pnv.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
index f3ec2cc69c0d..5154794cc8cd 100644
--- a/docs/system/ppc/powernv.rst
+++ b/docs/system/ppc/powernv.rst
@@ -1,5 +1,5 @@
-PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
-=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powern=
v11``)
+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D
=20
PowerNV (as Non-Virtualized) is the "bare metal" platform using the
OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
@@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today.
Supported devices
-----------------
=20
- * Multi processor support for POWER8, POWER8NVL and POWER9.
+ * Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Powe=
r11.
* XSCOM, serial communication sideband bus to configure chiplets.
* Simple LPC Controller.
* Processor Service Interface (PSI) Controller.
- * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power1=
0).
+ * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power1=
0 &
+ Power11).
* POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
* Simple OCC is an on-chip micro-controller used for power management tas=
ks.
* iBT device to handle BMC communication, with the internal BMC simulator
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 3612a2de2549..9ae71a988b02 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -3150,6 +3150,35 @@ static void pnv_machine_p10_rainier_class_init(Objec=
tClass *oc, void *data)
pmc->i2c_init =3D pnv_rainier_i2c_init;
}
=20
+static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc =3D MACHINE_CLASS(oc);
+ PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc);
+ static const char compat[] =3D "qemu,powernv11\0ibm,powernv";
+
+ pmc->compat =3D compat;
+ pmc->compat_size =3D sizeof(compat);
+ pmc->max_smt_threads =3D 4;
+ pmc->has_lpar_per_thread =3D true;
+ pmc->quirk_tb_big_core =3D true;
+ pmc->dt_power_mgt =3D pnv_dt_power_mgt;
+
+ mc->desc =3D "IBM PowerNV (Non-Virtualized) Power11";
+ mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power11_v2.0");
+
+ object_class_property_add_bool(oc, "big-core",
+ pnv_machine_get_big_core,
+ pnv_machine_set_big_core);
+ object_class_property_set_description(oc, "big-core",
+ "Use big-core (aka fused-core) mode");
+
+ object_class_property_add_bool(oc, "lpar-per-core",
+ pnv_machine_get_lpar_per_core,
+ pnv_machine_set_lpar_per_core);
+ object_class_property_set_description(oc, "lpar-per-core",
+ "Use 1 LPAR per core mode");
+}
+
static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
CPUPPCState *env =3D cpu_env(cs);
@@ -3263,6 +3292,11 @@ static void pnv_machine_class_init(ObjectClass *oc, =
void *data)
}
=20
static const TypeInfo types[] =3D {
+ {
+ .name =3D MACHINE_TYPE_NAME("powernv11"),
+ .parent =3D TYPE_PNV_MACHINE,
+ .class_init =3D pnv_machine_power11_class_init,
+ },
{
.name =3D MACHINE_TYPE_NAME("powernv10-rainier"),
.parent =3D MACHINE_TYPE_NAME("powernv10"),
--=20
2.49.0