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([2409:40f4:26:6ed:a652:7103:3a70:1af9]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7390611c7cfsm14431624b3a.110.2025.03.27.08.36.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Mar 2025 08:36:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743089810; x=1743694610; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=jY2pZXqmdN91zoyHJQ9Q6dIwOWQgQsjp2Sjz6EpDJy0=; b=kXD085HcOFKZtX7OfA9CJsMHFkJ+R0YBndTqcIg2B3PNyndb2y+4s25oSlsB7g1Vk5 mqOcnZoIJPUX/7wR0D1jqvL9Cter0DYhuCl5DIHzK5Us9pAXeA6A1eS7bP4liQ+j0H4K TwqrJOHDSLwWw2Egev9iDP1lSrz5nDallAfOMynWDvZUPnoYSW+TbX8JyByAzkXPYQcd XBwmXBnjkuI59LUFeUNiN4WWABW9cT73eHxlCHTGO/QcQrujdZ/d100QCkRc9KoxTrrJ EBA0lk0gxFGRyQupa/+D/x0o/g55YJ42X+PrnHkmpsMGNQETcl+lTze8zYNipAc6BN+N /2DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743089810; x=1743694610; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jY2pZXqmdN91zoyHJQ9Q6dIwOWQgQsjp2Sjz6EpDJy0=; b=pAK93UK9EU3xrDk2kvoXP9LgpWaKDEEq3dCrZ3p7LdEJyl2w7dNWKI/NdLjOxAFFxf Rr/SAFhSldW0ILn1X0F6ceaxObkdItAKDitZpJihMwJpC2Fh3kpFCq3MrRH01tnlSErW P5jlwlswQt6cAOekCMhfWJKi6PJ4U1ZtSVwSnd7OYKkgqnIaBWYHL3vdbwB+SarFzX38 jun6RGARd1HOZroxvMrTipQQdtthDbvZH7tmNSL+kuQRd5gEtYgm6EgW7a5Q+thFPCOu 7WVkhW48GcfpTfTgPeVLoooZtpnFd4BKwSGOZ/+b0u1OMvfOasVDG1T/S92SefrC9Uwq 9ZEA== X-Gm-Message-State: AOJu0YzBihTDmVqDJQ44ozn9ufXVKpFPt/Zzuwxjm4xZNKbQL6YJ1zLF WPHHkcV+3qgsjruTVlWWzQPfWtSx1M2FmGGJEwFCihB4PFi4g+MYvtZ0pSKcG8Q= X-Gm-Gg: ASbGncsb3m1Hhb3w3KRDYmcwr2z2TW6Qwd896E2zT30AihZnYe9Uw/D8wzGyMx4A1rP PWussgsmnzv8bvOhup1tpHbFtI8C4Lz8tGikx6vQoPJAL8nOGBvxXPbQlnS/sbVweOEhV37G0A6 gXtUD7LCOqr8KLdGLRNVdOC1KCZzzuyT01TrwAE3/CbBLn9JNof56yw7S1teh8lIw1uHjXXTQNq HRSO8ymWT0Y7jLy+DYBftkEThlWWrURw5TSkGAbtpQqwu3Yh2Uh/Aghx6aIpE4237cQyi4izT/o fnh/N8fy+dQ30l7p67H1aW2Ed+nz9mUG6pdebzkCegz2Fkrf X-Google-Smtp-Source: AGHT+IED+OonyK/RYmGbXPRqetHcui6wMkxvsUMt7nY7AM0C097dGeC6giILVW3xhjlfnIwG+oI8kw== X-Received: by 2002:a05:6a20:160f:b0:1fd:f8dc:83f6 with SMTP id adf61e73a8af0-1fea2fa6363mr8146433637.40.1743089810380; Thu, 27 Mar 2025 08:36:50 -0700 (PDT) From: rakeshj To: qemu-devel@nongnu.org Cc: marcandre.lureau@redhat.com, philmd@linaro.org, thuth@redhat.com, rakeshj Subject: [PATCH] hw/pci-host/gt64120.c: Fix PCI host bridge endianness handling Date: Thu, 27 Mar 2025 21:06:27 +0530 Message-ID: <20250327153627.307040-1-rakeshjb010@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=rakeshjb010@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 27 Mar 2025 16:13:31 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1743106479594019000 Content-Type: text/plain; charset="utf-8" The GT-64120 PCI controller requires special handling where: 1. Host bridge (device 0) must use native endianness 2. Other devices follow MByteSwap bit in GT_PCI0_CMD Previous implementation accidentally swapped all accesses, breaking host bridge detection (lspci -d 11ab:4620). This fix: - Adds device filtering via (phb->config_reg & 0x00FFF800) - Preserves native endianness for host bridge - Maintains swapping for other devices in big-endian mode Fixes: 145e2198 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE Me= moryRegionOps") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2826 Signed-off-by: rakeshj --- hw/pci-host/gt64120.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index d5c13a89b6..098f8e5988 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -320,11 +320,46 @@ static void gt64120_isd_mapping(GT64120State *s) memory_region_transaction_commit(); } =20 +static uint64_t gt64120_pci_data_read(void *opaque, hwaddr addr, unsigned = size) +{ + GT64120State *s =3D opaque; + PCIHostState *phb =3D PCI_HOST_BRIDGE(s); + uint32_t val =3D pci_data_read(phb->bus, phb->config_reg, size); + =20 + /* Only swap for non-bridge devices in big-endian mode */ + if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { + val =3D bswap32(val); + } + return val; +} + +static void gt64120_pci_data_write(void *opaque, hwaddr addr,=20 + uint64_t val, unsigned size) +{ + GT64120State *s =3D opaque; + PCIHostState *phb =3D PCI_HOST_BRIDGE(s); + if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) { + val =3D bswap32(val); + } + if (phb->config_reg & (1u << 31)) + pci_data_write(phb->bus, phb->config_reg | (addr & 3), val, size); +} + +static const MemoryRegionOps gt64120_pci_data_ops =3D { + .read =3D gt64120_pci_data_read, + .write =3D gt64120_pci_data_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + static void gt64120_update_pci_cfgdata_mapping(GT64120State *s) { /* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc= 00 */ static const MemoryRegionOps *pci_host_data_ops[] =3D { - &pci_host_data_be_ops, &pci_host_data_le_ops + >64120_pci_data_ops, &pci_host_data_le_ops }; PCIHostState *phb =3D PCI_HOST_BRIDGE(s); =20 --=20 2.43.0