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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1743010755; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lP38z8k7Rfn+cEpB3dun7+TjWK/eALtqg1VxIldAvpI=; b=Xl+CogUPWiCVhJa3fNjenZHLJcOoqQiS2Ag51OJp3PDb+jvGhFK++a9Sxbe91rasdnWKZq aIYJ8G0vl9/CISBaatg+Wp7tY38SvRBUFXNzmm9F8yqhr83WnJ0NsPdmSUB29yb+hl+vu1 VtIC7rCn0fLGCgAA7oBWN/o2JbAULuo= X-MC-Unique: r32EJLOyMEC3GnMQkySpMg-1 X-Mimecast-MFC-AGG-ID: r32EJLOyMEC3GnMQkySpMg_1743010749 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH for-10.1 v4 05/13] arm/cpu: Store aa64mmfr0-3 into the idregs array Date: Wed, 26 Mar 2025 18:37:15 +0100 Message-ID: <20250326173723.389988-6-cohuck@redhat.com> In-Reply-To: <20250326173723.389988-1-cohuck@redhat.com> References: <20250326173723.389988-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-features.h | 74 +++++++++++++++++++-------------------- target/arm/cpu.h | 4 --- target/arm/cpu64.c | 8 ++--- target/arm/helper.c | 8 ++--- target/arm/hvf/hvf.c | 21 ++++++----- target/arm/kvm.c | 12 +++---- target/arm/ptw.c | 6 ++-- target/arm/tcg/cpu64.c | 64 ++++++++++++++++----------------- 8 files changed, 95 insertions(+), 102 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 5cc4721e6406..36c35f6a434a 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -710,192 +710,192 @@ static inline bool isar_feature_aa64_nmi(const ARMI= SARegisters *id) =20 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 1; + return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 1; } =20 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *= id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran4_lpa2(id)); } =20 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >=3D 2; } =20 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters = *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran16_lpa2(id)); } =20 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 0; } =20 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 1; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >=3D 1; } =20 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN64) >=3D 0; } =20 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran4(id)); } =20 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran16(id)); } =20 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN64_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran64(id)); } =20 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, FGT) !=3D 0; } =20 static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 0; } =20 static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 1; } =20 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, VH) !=3D 0; } =20 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, LO) !=3D 0; } =20 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) !=3D 0; } =20 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >=3D 2; } =20 static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 3; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >=3D 3; } =20 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HCX) !=3D 0; } =20 static inline bool isar_feature_aa64_afp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, AFP) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, AFP) !=3D 0; } =20 static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, TIDCP1) !=3D 0; } =20 static inline bool isar_feature_aa64_cmow(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, CMOW) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, CMOW) !=3D 0; } =20 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) !=3D 0; } =20 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) >=3D 2; } =20 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, XNX) !=3D 0; } =20 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, UAO) !=3D 0; } =20 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, ST) !=3D 0; } =20 static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, AT) !=3D 0; } =20 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, FWB) !=3D 0; } =20 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, IDS) !=3D 0; } =20 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >=3D 1; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >=3D 1; } =20 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >=3D 2; } =20 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, CCIDX) !=3D 0; } =20 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, VARANGE) !=3D 0; } =20 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, E0PD) !=3D 0; } =20 static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) !=3D 0; } =20 static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 83ac125b97c5..30f27fb64aed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1097,10 +1097,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64mmfr0; - uint64_t id_aa64mmfr1; - uint64_t id_aa64mmfr2; - uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 111b2514218e..6d51a53b0abb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -623,12 +623,12 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) return; } =20 - t =3D cpu->isar.id_aa64mmfr0; + t =3D GET_IDREG(&cpu->isar, ID_AA64MMFR0); t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 = */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 = */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2= */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2= */ - cpu->isar.id_aa64mmfr0 =3D t; + SET_IDREG(&cpu->isar, ID_AA64MMFR0, t); } =20 static void aarch64_a57_initfn(Object *obj) @@ -673,7 +673,7 @@ static void aarch64_a57_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001124; + SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; @@ -735,7 +735,7 @@ static void aarch64_a53_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ + SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x00110f13; cpu->isar.dbgdevid1 =3D 0x1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 716d0570f6d6..15ca88b165e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8041,22 +8041,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR0)}, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR1) }, { .name =3D "ID_AA64MMFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr2 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR2) }, { .name =3D "ID_AA64MMFR3_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr3 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR3) }, { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index a4861d96fff3..68fdb3969a63 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -845,14 +845,17 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) return val; } =20 -static void clamp_id_aa64mmfr0_parange_to_ipa_size(uint64_t *id_aa64mmfr0) +static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) { uint32_t ipa_size =3D chosen_ipa_bit_size ? chosen_ipa_bit_size : hvf_arm_get_max_ipa_bit_size(); + uint64_t id_aa64mmfr0; =20 /* Clamp down the PARange to the IPA size the kernel supports. */ uint8_t index =3D round_down_to_parange_index(ipa_size); - *id_aa64mmfr0 =3D (*id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | ind= ex; + id_aa64mmfr0 =3D GET_IDREG(isar, ID_AA64MMFR0); + id_aa64mmfr0 =3D (id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index; + SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); } =20 static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) @@ -869,9 +872,9 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ - { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, - { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, - { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, + { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_= IDX] }, + { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_= IDX] }, + { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_= IDX] }, /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ }; hv_vcpu_t fd; @@ -898,7 +901,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) r |=3D hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); r |=3D hv_vcpu_destroy(fd); =20 - clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar.id_aa64mmfr0); + clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 /* * Disable SME, which is not properly handled by QEMU hvf yet. @@ -1065,12 +1068,12 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 /* We're limited to underlying hardware caps, override internal versio= ns */ ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, - &arm_cpu->isar.id_aa64mmfr0); + &arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 - clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar.id_aa64mmfr0); + clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar); ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, - arm_cpu->isar.id_aa64mmfr0); + arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 return 0; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 44a5e219b051..5f3c42b94690 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -362,14 +362,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, - ARM64_SYS_REG(3, 0, 0, 7, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, - ARM64_SYS_REG(3, 0, 0, 7, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, - ARM64_SYS_REG(3, 0, 0, 7, 2)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3, - ARM64_SYS_REG(3, 0, 0, 7, 3)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR2_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR3_EL1_IDX); =20 /* * Note that if AArch32 support is not present in the host, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 43309003486b..79c7dabdc687 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -120,7 +120,7 @@ unsigned int arm_pamax(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { unsigned int parange =3D - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE); =20 /* * id_aa64mmfr0 is a read-only register so values outside of the @@ -330,7 +330,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, * physical address size is invalid. */ pps =3D FIELD_EX64(gpccr, GPCCR, PPS); - if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { + if (pps > FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE)) { goto fault_walk; } pps =3D pamax_map[pps]; @@ -1701,7 +1701,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * ID_AA64MMFR0 is a read-only register so values outside of the * supported mappings can be considered an implementation error. */ - ps =3D FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + ps =3D FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE); ps =3D MIN(ps, param.ps); assert(ps < ARRAY_SIZE(pamax_map)); outputsize =3D pamax_map[ps]; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 478ef839bafa..439c29e69546 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -69,8 +69,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64ISAR1, 0); - cpu->isar.id_aa64mmfr0 =3D 0x00101122; - cpu->isar.id_aa64mmfr1 =3D 0; + SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); + SET_IDREG(isar, ID_AA64MMFR1, 0); cpu->clidr =3D 0x0a200023; cpu->dcz_blocksize =3D 4; =20 @@ -222,9 +222,9 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull); SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; @@ -312,7 +312,7 @@ static void aarch64_a72_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001124; + SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; @@ -355,9 +355,9 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; @@ -430,9 +430,9 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; cpu->id_aa64afr0 =3D 0x0000000000000000; cpu->id_aa64afr1 =3D 0x0000000000000000; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; - cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000011212100); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011); SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001); SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); @@ -603,9 +603,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; @@ -682,9 +682,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0x00000000; SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull), + SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull), SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; @@ -931,9 +931,9 @@ static void aarch64_a710_initfn(Object *obj) cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x1221011110101011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101122ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x1221011110101011ull); cpu->clidr =3D 0x0000001482000023ull; cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x000000049444c004ull; @@ -1033,9 +1033,9 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x1221011112101011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x1221011112101011ull); cpu->clidr =3D 0x0000001482000023ull; cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x00000004b444c004ull; @@ -1206,7 +1206,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ SET_IDREG(isar, ID_AA64PFR1, t); =20 - t =3D cpu->isar.id_aa64mmfr0; + t =3D GET_IDREG(isar, ID_AA64MMFR0); t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ @@ -1214,9 +1214,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ - cpu->isar.id_aa64mmfr0 =3D t; + SET_IDREG(isar, ID_AA64MMFR0, t); =20 - t =3D cpu->isar.id_aa64mmfr1; + t =3D GET_IDREG(isar, ID_AA64MMFR1); t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ @@ -1229,9 +1229,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* FEAT_AFP */ t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* FEAT_CMOW */ - cpu->isar.id_aa64mmfr1 =3D t; + SET_IDREG(isar, ID_AA64MMFR1, t); =20 - t =3D cpu->isar.id_aa64mmfr2; + t =3D GET_IDREG(isar, ID_AA64MMFR2); t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ @@ -1245,11 +1245,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ - cpu->isar.id_aa64mmfr2 =3D t; + SET_IDREG(isar, ID_AA64MMFR2, t); =20 - t =3D cpu->isar.id_aa64mmfr3; - t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ - cpu->isar.id_aa64mmfr3 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPE= C */ =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); --=20 2.48.1