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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- hw/intc/armv7m_nvic.c | 5 +- target/arm/cpu-features.h | 10 ++-- target/arm/cpu.c | 8 +-- target/arm/cpu.h | 3 - target/arm/cpu64.c | 8 +-- target/arm/helper.c | 8 +-- target/arm/kvm.c | 3 +- target/arm/tcg/cpu-v7m.c | 120 +++++++++++++++++++------------------- target/arm/tcg/cpu32.c | 52 ++++++++--------- target/arm/tcg/cpu64.c | 44 +++++++------- 10 files changed, 128 insertions(+), 133 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 55e726be7a2c..407933eaf42e 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -988,6 +988,7 @@ static void nvic_nmi_trigger(void *opaque, int n, int l= evel) static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) { ARMCPU *cpu =3D s->cpu; + ARMISARegisters *isar =3D &cpu->isar; uint32_t val; =20 switch (offset) { @@ -1263,12 +1264,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_pfr0; + return GET_IDREG(isar, ID_PFR0); case 0xd44: /* PFR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_pfr1; + return GET_IDREG(isar, ID_PFR1); case 0xd48: /* DFR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 003cf735e8ef..156130085067 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -136,12 +136,12 @@ static inline bool isar_feature_aa32_i8mm(const ARMIS= ARegisters *id) =20 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR0, RAS) !=3D 0; } =20 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR1, MPROGMOD) !=3D 0; } =20 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) @@ -150,7 +150,7 @@ static inline bool isar_feature_aa32_m_sec_state(const = ARMISARegisters *id) * Return true if M-profile state handling insns * (VSCCLRM, CLRM, FPCTX access insns) are implemented */ - return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >=3D 3; + return FIELD_EX32_IDREG(id, ID_PFR1, SECURITY) >=3D 3; } =20 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) @@ -349,12 +349,12 @@ static inline bool isar_feature_aa32_evt(const ARMISA= Registers *id) =20 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR0, DIT) !=3D 0; } =20 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR2, SSBS) !=3D 0; } =20 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 45d922110c17..51027e279f5f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2323,7 +2323,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * Disable the security extension feature bits in the processor * feature registers as well. */ - cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); =20 @@ -2363,8 +2363,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * registers if we don't have EL2. */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0); - cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, - ID_PFR1, VIRTUALIZATION, 0); + FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0); } =20 if (cpu_isar_feature(aa64_mte, cpu)) { @@ -2427,8 +2426,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); - cpu->isar.id_pfr0 =3D - FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); + FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0); /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0); } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c98bdc1687c0..3d68938c2893 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1079,9 +1079,6 @@ struct ArchCPU { uint32_t id_mmfr3; uint32_t id_mmfr4; uint32_t id_mmfr5; - uint32_t id_pfr0; - uint32_t id_pfr1; - uint32_t id_pfr2; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1489ebb1015e..a35acf63aef7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -652,8 +652,8 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -714,8 +714,8 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; diff --git a/target/arm/helper.c b/target/arm/helper.c index 1ba8551f6db8..86f21ad2a18c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6929,7 +6929,7 @@ static void define_pmu_regs(ARMCPU *cpu) static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr1 =3D cpu->isar.id_pfr1; + uint64_t pfr1 =3D GET_IDREG(&cpu->isar, ID_PFR1); =20 if (env->gicv3state) { pfr1 |=3D 1 << 28; @@ -7775,7 +7775,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_pfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_PFR0)}, /* * ID_PFR1 is not a plain ARM_CP_CONST because we don't know * the value of the GIC field until after we define these regs. @@ -7786,7 +7786,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa32_tid3, #ifdef CONFIG_USER_ONLY .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_pfr1, + .resetvalue =3D GET_IDREG(isar, ID_PFR1), #else .type =3D ARM_CP_NO_RAW, .accessfn =3D access_aa32_tid3, @@ -8128,7 +8128,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_pfr2 }, + .resetvalue =3D GET_IDREG(isar, ID_PFR2)}, { .name =3D "ID_DFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ceb7e7bec7a2..91610d45aef8 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -399,8 +399,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 1)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, - ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, ARM64_SYS_REG(3, 0, 0, 3, 5)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 9d5938abdb4b..aa86fdd528f4 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -45,7 +45,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t *idregs =3D cpu->isar.idregs; + ARMISARegisters *isar =3D &cpu->isar; set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_M); =20 @@ -59,53 +59,53 @@ static void cortex_m0_initfn(Object *obj) * by looking at ID register fields. We use the same values as * for the M3. */ - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - SET_IDREG(idregs, ID_ISAR0, 0x01141110); - SET_IDREG(idregs, ID_ISAR1, 0x02111000); - SET_IDREG(idregs, ID_ISAR2, 0x21112231); - SET_IDREG(idregs, ID_ISAR3, 0x01111110); - SET_IDREG(idregs, ID_ISAR4, 0x01310102); - SET_IDREG(idregs, ID_ISAR5, 0x00000000); - SET_IDREG(idregs, ID_ISAR6, 0x00000000); + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t *idregs =3D cpu->isar.idregs; + ARMISARegisters *isar =3D &cpu->isar; set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); cpu->midr =3D 0x410fc231; cpu->pmsav7_dregion =3D 8; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - SET_IDREG(idregs, ID_ISAR0, 0x01141110); - SET_IDREG(idregs, ID_ISAR1, 0x02111000); - SET_IDREG(idregs, ID_ISAR2, 0x21112231); - SET_IDREG(idregs, ID_ISAR3, 0x01111110); - SET_IDREG(idregs, ID_ISAR4, 0x01310102); - SET_IDREG(idregs, ID_ISAR5, 0x00000000); - SET_IDREG(idregs, ID_ISAR6, 0x00000000); + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m4_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t *idregs =3D cpu->isar.idregs; + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -116,27 +116,27 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000000; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - SET_IDREG(idregs, ID_ISAR0, 0x01141110); - SET_IDREG(idregs, ID_ISAR1, 0x02111000); - SET_IDREG(idregs, ID_ISAR2, 0x21112231); - SET_IDREG(idregs, ID_ISAR3, 0x01111110); - SET_IDREG(idregs, ID_ISAR4, 0x01310102); - SET_IDREG(idregs, ID_ISAR5, 0x00000000); - SET_IDREG(idregs, ID_ISAR6, 0x00000000); + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t *idregs =3D cpu->isar.idregs; + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -147,27 +147,27 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00100030; cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - SET_IDREG(idregs, ID_ISAR0, 0x01101110); - SET_IDREG(idregs, ID_ISAR1, 0x02112000); - SET_IDREG(idregs, ID_ISAR2, 0x20232231); - SET_IDREG(idregs, ID_ISAR3, 0x01111131); - SET_IDREG(idregs, ID_ISAR4, 0x01310132); - SET_IDREG(idregs, ID_ISAR5, 0x00000000); - SET_IDREG(idregs, ID_ISAR6, 0x00000000); + SET_IDREG(isar, ID_ISAR0, 0x01101110); + SET_IDREG(isar, ID_ISAR1, 0x02112000); + SET_IDREG(isar, ID_ISAR2, 0x20232231); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m33_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t *idregs =3D cpu->isar.idregs; + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_M); @@ -180,21 +180,21 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000210; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000210); cpu->isar.id_dfr0 =3D 0x00200000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00101F40; cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - SET_IDREG(idregs, ID_ISAR0, 0x01101110); - SET_IDREG(idregs, ID_ISAR1, 0x02212000); - SET_IDREG(idregs, ID_ISAR2, 0x20232232); - SET_IDREG(idregs, ID_ISAR3, 0x01111131); - SET_IDREG(idregs, ID_ISAR4, 0x01310132); - SET_IDREG(idregs, ID_ISAR5, 0x00000000); - SET_IDREG(idregs, ID_ISAR6, 0x00000000); + SET_IDREG(isar, ID_ISAR0, 0x01101110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; cpu->ctr =3D 0x8000c000; } @@ -202,7 +202,7 @@ static void cortex_m33_initfn(Object *obj) static void cortex_m55_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t *idregs =3D cpu->isar.idregs; + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_V8_1M); @@ -218,21 +218,21 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12100211; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x20000030; - cpu->isar.id_pfr1 =3D 0x00000230; + SET_IDREG(isar, ID_PFR0, 0x20000030); + SET_IDREG(isar, ID_PFR1, 0x00000230); cpu->isar.id_dfr0 =3D 0x10200000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00111040; cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000011; - SET_IDREG(idregs, ID_ISAR0, 0x01103110); - SET_IDREG(idregs, ID_ISAR1, 0x02212000); - SET_IDREG(idregs, ID_ISAR2, 0x20232232); - SET_IDREG(idregs, ID_ISAR3, 0x01111131); - SET_IDREG(idregs, ID_ISAR4, 0x01310132); - SET_IDREG(idregs, ID_ISAR5, 0x00000000); - SET_IDREG(idregs, ID_ISAR6, 0x00000000); + SET_IDREG(isar, ID_ISAR0, 0x01103110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; /* caches not implemented */ cpu->ctr =3D 0x8303c003; } diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d022ba3c9b32..dcc3064ebb86 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -71,16 +71,16 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ cpu->isar.id_mmfr5 =3D t; =20 - t =3D cpu->isar.id_pfr0; + t =3D GET_IDREG(isar, ID_PFR0); t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ - cpu->isar.id_pfr0 =3D t; + SET_IDREG(isar, ID_PFR0, t); =20 - t =3D cpu->isar.id_pfr2; + t =3D GET_IDREG(isar, ID_PFR2); t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ - cpu->isar.id_pfr2 =3D t; + SET_IDREG(isar, ID_PFR2, t); =20 t =3D cpu->isar.id_dfr0; t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ @@ -228,8 +228,8 @@ static void arm1136_r2_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -260,8 +260,8 @@ static void arm1136_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -293,8 +293,8 @@ static void arm1176_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x33; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -323,8 +323,8 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x11111111; cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0; cpu->id_afr0 =3D 0x2; cpu->isar.id_mmfr0 =3D 0x01100103; @@ -363,8 +363,8 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00011111; cpu->ctr =3D 0x82048004; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(isar, ID_PFR0, 0x1031); + SET_IDREG(isar, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x400; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x31100003; @@ -439,8 +439,8 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x01111111; cpu->ctr =3D 0x80038003; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(isar, ID_PFR0, 0x1031); + SET_IDREG(isar, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x000; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x00100103; @@ -505,8 +505,8 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x84448003; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00001131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -557,8 +557,8 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00001131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -601,8 +601,8 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->midr =3D 0x411fc153; /* r1p3 */ - cpu->isar.id_pfr0 =3D 0x0131; - cpu->isar.id_pfr1 =3D 0x001; + SET_IDREG(isar, ID_PFR0, 0x0131); + SET_IDREG(isar, ID_PFR1, 0x001); cpu->isar.id_dfr0 =3D 0x010400; cpu->id_afr0 =3D 0x0; cpu->isar.id_mmfr0 =3D 0x0210030; @@ -748,8 +748,8 @@ static void cortex_r52_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8144c004; cpu->reset_sctlr =3D 0x30c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x10111001; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x10111001); cpu->isar.id_dfr0 =3D 0x03010006; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00211040; @@ -980,8 +980,8 @@ static void arm_max_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index ad47279cdd46..cfaf01fbf9bc 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -49,8 +49,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->midr =3D 0x411fd040; cpu->revidr =3D 0; cpu->ctr =3D 0x84448004; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -241,9 +241,9 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00011011); + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x412FD050; /* r2p0 */ cpu->revidr =3D 0; =20 @@ -295,8 +295,8 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -374,9 +374,9 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0b1; /* r4p1 */ cpu->revidr =3D 0; =20 @@ -622,9 +622,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0c1; /* r4p1 */ cpu->revidr =3D 0; =20 @@ -701,9 +701,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x01021110; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x21110131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x411FD402; /* r1p2 */ cpu->revidr =3D 0; =20 @@ -902,8 +902,8 @@ static void aarch64_a710_initfn(Object *obj) /* Ordered by Section B.4: AArch64 registers */ cpu->midr =3D 0x412FD471; /* r2p1 */ cpu->revidr =3D 0; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + SET_IDREG(isar, ID_PFR0, 0x21110131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ cpu->isar.id_dfr0 =3D 0x16011099; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -921,7 +921,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR2, 0x00000011); SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ @@ -1005,8 +1005,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) /* Ordered by Section B.5: AArch64 ID registers */ cpu->midr =3D 0x410FD493; /* r0p3 */ cpu->revidr =3D 0; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + SET_IDREG(isar, ID_PFR0, 0x21110131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ cpu->isar.id_dfr0 =3D 0x16011099; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -1024,7 +1024,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR2, 0x00000011); SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ --=20 2.48.1