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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7390611d3d6sm11111321b3a.94.2025.03.25.15.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Mar 2025 15:44:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742942646; x=1743547446; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BEoa5+P2s+dvjQMF6oUGcAe5STudghf85RD71OkQiHw=; b=mdYuAJBb6nUkpq0aI58jwcnu0xk5zG2VDx7w6Qpn7KwfgEXPQ5t3M7KIdevOoo6QIa yCL9GyYldenr1SSrmBgvwnsdxSCAn6Ri4KhJbdPIDVQGUQu4+CkhyI9IK2GlKBtFHXez 1i32lZc1pwHUI9klrf40IPV6T+hBRHBp0MtQ/vEdQI7bAmmVh/21Nt20BtAfZPfY9Yhv b1s0XSvxwy92WDJx0XLSsMiSg4sRCUXaXzPaJh4XiOKJxrhyLNrh4YG9Y2/DzVUsf0bC +wc5P/AvJusE8sI2yJp7e85HHtd1hLWfjuhX5zpDqzYY8MMKNV0tqQyEY7A7KsyI9FhE lxqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742942646; x=1743547446; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BEoa5+P2s+dvjQMF6oUGcAe5STudghf85RD71OkQiHw=; b=kpHhoxpsl3D8/Rb5duqYJuNisA8NOzFW1XBa3gSvn6C5WKbRMrZt4b5itKP7ke5N8W 1rS8bElQBlCbnjARUx0Zl+8BpdAZUspdjLVd6upQ0v1ZzEHSydbiuXolDYX0N5hEKf73 FGbGPYzE7+pvNJSGjSVUsUJMcWJMLdzBATnpvt/HApRFqqpSzgLIiUFPk3S4TioFEODO EJp5YFceH3YNnqDt47hGUY3rcweYi4pNmH1RHi1Kex1wSL/c8tC7EdGYjdQaxhdrnNpC M/SgIpDgO1jvx8fImvQM/hfCE/xHjkk0MkUh1uewraTWYyFeLLZySACv3DEgVB8G1+hD d2Xw== X-Gm-Message-State: AOJu0YzQ+ZvifebEVzaH2EeCfmH3GjNKU1XdYPqU+jfYDU3x1FA41DkS wwWtjw7nPdgfklHsUnLyEehReQpnz9Eo+bh4R6VxtUTa/9e+Wm0evjTQ355YfAisRQ3k9XcoHwR N X-Gm-Gg: ASbGnctGc9EgO4HXLy8abp+w/PJO4f43YHfYHBTCp27dWWA0bzygHXIfUciIvGf3Kvo GOC/l7UyoGUB7Iucfos9JuJThxX566PfjcPNKhryUujmaPMAvKx3vQiarKYCKWBSL6lb10+Ue5N qgNx9BjHoITvQvr8tgOWYS8LZezvvFc/IeVqASPIlkuyvMwaGPErVDsWJFtiMIAw3pDpLLzOT64 yO+st8P1R/BVg0E5Jz3o77Twu2gBxf1DfztdGTQhoCs+F4mzUc1PoRx7Zqp4c87hSFX/pThwBpa PT08YQ4JUZJupomovgdW5RO5csivvv0lj6nAo5WHBeijEmCcsDoqxuAoQr7CrjmI6nVVa93IG0c T X-Google-Smtp-Source: AGHT+IFnjpLQqFskCkmRthOCUw2WWZMAB8rTHZgfcwPMPqwOhf4H/UfSI+lZ3iEOB2qttPWlZdM+/g== X-Received: by 2002:a05:6a21:9188:b0:1f5:64fd:68eb with SMTP id adf61e73a8af0-1fe42f07ba9mr32640081637.7.1742942646156; Tue, 25 Mar 2025 15:44:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org, qemu-stable@nongnu.org Subject: [PATCH v2 02/11] target/avr: Improve decode of LDS, STS Date: Tue, 25 Mar 2025 15:43:54 -0700 Message-ID: <20250325224403.4011975-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325224403.4011975-1-richard.henderson@linaro.org> References: <20250325224403.4011975-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742942695796019000 Content-Type: text/plain; charset="utf-8" The comment about not being able to define a field with zero bits is out of date since 94597b6146f3 ("decodetree: Allow !function with no input bits"). This fixes the missing load of imm in the disassembler. Cc: qemu-stable@nongnu.org Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling via option '= -d in_asm'") Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/translate.c | 2 -- target/avr/insn.decode | 7 ++----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 4ab71d8138..e7f8ced9b3 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1578,7 +1578,6 @@ static bool trans_LDS(DisasContext *ctx, arg_LDS *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D tcg_temp_new_i32(); TCGv H =3D cpu_rampD; - a->imm =3D next_word(ctx); =20 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */ tcg_gen_shli_tl(addr, addr, 16); @@ -1783,7 +1782,6 @@ static bool trans_STS(DisasContext *ctx, arg_STS *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D tcg_temp_new_i32(); TCGv H =3D cpu_rampD; - a->imm =3D next_word(ctx); =20 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */ tcg_gen_shli_tl(addr, addr, 16); diff --git a/target/avr/insn.decode b/target/avr/insn.decode index 482c23ad0c..cc302249db 100644 --- a/target/avr/insn.decode +++ b/target/avr/insn.decode @@ -118,11 +118,8 @@ BRBC 1111 01 ....... ... @op_bit_imm @io_rd_imm .... . .. ..... .... &rd_imm rd=3D%rd imm=3D%io= _imm @ldst_d .. . . .. . rd:5 . ... &rd_imm imm=3D%ldst_d_imm =20 -# The 16-bit immediate is completely in the next word. -# Fields cannot be defined with no bits, so we cannot play -# the same trick and append to a zero-bit value. -# Defer reading the immediate until trans_{LDS,STS}. -@ldst_s .... ... rd:5 .... imm=3D0 +%ldst_imm !function=3Dnext_word +@ldst_s .... ... rd:5 .... imm=3D%ldst_imm =20 MOV 0010 11 . ..... .... @op_rd_rr MOVW 0000 0001 .... .... &rd_rr rd=3D%rd_d rr=3D%r= r_d --=20 2.43.0