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Cc: qemu-stable@nongnu.org Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/avr/disas.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/target/avr/disas.c b/target/avr/disas.c index b7689e8d7c..d341030174 100644 --- a/target/avr/disas.c +++ b/target/avr/disas.c @@ -68,28 +68,35 @@ static bool decode_insn(DisasContext *ctx, uint16_t ins= n); =20 int avr_print_insn(bfd_vma addr, disassemble_info *info) { - DisasContext ctx; + DisasContext ctx =3D { info }; DisasContext *pctx =3D &ctx; bfd_byte buffer[4]; uint16_t insn; int status; =20 - ctx.info =3D info; - - status =3D info->read_memory_func(addr, buffer, 4, info); + status =3D info->read_memory_func(addr, buffer, 2, info); if (status !=3D 0) { info->memory_error_func(status, addr, info); return -1; } insn =3D bfd_getl16(buffer); - ctx.next_word =3D bfd_getl16(buffer + 2); - ctx.next_word_used =3D false; + + status =3D info->read_memory_func(addr + 2, buffer + 2, 2, info); + if (status =3D=3D 0) { + ctx.next_word =3D bfd_getl16(buffer + 2); + } =20 if (!decode_insn(&ctx, insn)) { output(".db", "0x%02x, 0x%02x", buffer[0], buffer[1]); } =20 - return ctx.next_word_used ? 4 : 2; + if (!ctx.next_word_used) { + return 2; + } else if (status =3D=3D 0) { + return 4; + } + info->memory_error_func(status, addr + 2, info); + return -1; } =20 =20 --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742942693; cv=none; d=zohomail.com; s=zohoarc; b=DmQcNZ0xxb4TqSzR6vG9KNmDnlnzoIfGC3dwPEwkVAMh4YEf0GErMt4ePsG4Bc4SZKvi09sQth2b073mama0TnCVGvG1XDP7ngFu3+8A3CLwTcjGNp+8Bv6vDK4iKU6tF7t7cNstiki2iK7GjoUQrW1WsfUXS8tq3fD1+8LH72c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742942693; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BEoa5+P2s+dvjQMF6oUGcAe5STudghf85RD71OkQiHw=; b=jhlX5tuyIAr2zyyrI13tv0RBF58EVpmQB7mq7S2wWkT6rW1aN8oMv4o0yR8YFS1WgOrtzYQ2c7bJthd+mFQX+rKnqH0CnC6yDjlUVDrE3AIM7r7+Ws5wpcOEOGMg3FECTMl5/sai3sogDQ9LRTFQy2AfXX3zmmOIO57fZx6Z3Vo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742942693830247.03894563572362; Tue, 25 Mar 2025 15:44:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1txD0X-0002cJ-T2; Tue, 25 Mar 2025 18:44:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1txD0F-0001Mg-GZ for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:11 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1txD0B-00072Q-Nq for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:11 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-22423adf751so116948005ad.2 for ; Tue, 25 Mar 2025 15:44:07 -0700 (PDT) Received: from stoup.. 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This fixes the missing load of imm in the disassembler. Cc: qemu-stable@nongnu.org Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling via option '= -d in_asm'") Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/translate.c | 2 -- target/avr/insn.decode | 7 ++----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 4ab71d8138..e7f8ced9b3 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1578,7 +1578,6 @@ static bool trans_LDS(DisasContext *ctx, arg_LDS *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D tcg_temp_new_i32(); TCGv H =3D cpu_rampD; - a->imm =3D next_word(ctx); =20 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */ tcg_gen_shli_tl(addr, addr, 16); @@ -1783,7 +1782,6 @@ static bool trans_STS(DisasContext *ctx, arg_STS *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D tcg_temp_new_i32(); TCGv H =3D cpu_rampD; - a->imm =3D next_word(ctx); =20 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */ tcg_gen_shli_tl(addr, addr, 16); diff --git a/target/avr/insn.decode b/target/avr/insn.decode index 482c23ad0c..cc302249db 100644 --- a/target/avr/insn.decode +++ b/target/avr/insn.decode @@ -118,11 +118,8 @@ BRBC 1111 01 ....... ... @op_bit_imm @io_rd_imm .... . .. ..... .... &rd_imm rd=3D%rd imm=3D%io= _imm @ldst_d .. . . .. . rd:5 . ... &rd_imm imm=3D%ldst_d_imm =20 -# The 16-bit immediate is completely in the next word. -# Fields cannot be defined with no bits, so we cannot play -# the same trick and append to a zero-bit value. -# Defer reading the immediate until trans_{LDS,STS}. -@ldst_s .... ... rd:5 .... imm=3D0 +%ldst_imm !function=3Dnext_word +@ldst_s .... ... rd:5 .... imm=3D%ldst_imm =20 MOV 0010 11 . ..... .... @op_rd_rr MOVW 0000 0001 .... .... &rd_rr rd=3D%rd_d rr=3D%r= r_d --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742942716; cv=none; d=zohomail.com; s=zohoarc; b=hOeiodmFAVUpvycqkuFDIRFd/LQYm+d9trlpv0hY4LylPLTbDfW7P+oCZjhxvMsSw7iWfGPeoYzXl/4XTOXU9pHNYRj8JXZVNnUK/ZZf75paF3bj1KcV2ZS3UK1Jclozr9V4Ci8JsB8kx4XJJT4m27wqNBmI0yQZblshU37kC5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742942716; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YP1/YoZtmNlvDfK/7GvLWQk4iAQ+/s3R4pyDEvaptyk=; b=NuJQgLdZIqhOih9WBoifF2o0nvI9CS+L6UKtWtKAafUbT2rFJuqOZlKCnUtBnRv9FeLBvFbqRHED0aiCAr6Z7M33+Qyhw0IW9+SOkcfcvxQjKW1dcQGCSj8nKx6BzvlM4VUmapwluPhfbbPShbuIjUPCZDN48m0uiQNu+4C10vg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742942716656990.4028268180375; Tue, 25 Mar 2025 15:45:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1txD0V-0002VH-Ln; Tue, 25 Mar 2025 18:44:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1txD0G-0001Tt-F4 for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:12 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1txD0C-00072d-MP for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:11 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-22580c9ee0aso127172505ad.2 for ; Tue, 25 Mar 2025 15:44:08 -0700 (PDT) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7390611d3d6sm11111321b3a.94.2025.03.25.15.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Mar 2025 15:44:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742942647; x=1743547447; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YP1/YoZtmNlvDfK/7GvLWQk4iAQ+/s3R4pyDEvaptyk=; b=z3MuKUL8R610AmnUVQnnfoUul6I09LrP6+xPBJCffXlM7XzynQmvINOV9Iqat2uIV+ PYsvu1EBDihLN+1vR3jnTheT9oHgyh4wTp3rKeKaholFcbJrkQ/lhBqP43yk2tfYHR3e pyEMonI9sTB8yMbbcgH6Y2ZyCazmUVv1k0YQGURkrwbP0RTTJbcOFB1924uxbdwaBKj8 DS15E0CeG1B3NjLSdluYrwSme/9jjeLkKb+iVasYWUZayxMczFq5v67RtIiHVC7NfESW EgO5FvmgRksoq1dEeokPavO6xnzaHf3nLN77t0PPRdJfl45bG7F4jhYLG69jP/+yQ6mu FNrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742942647; x=1743547447; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YP1/YoZtmNlvDfK/7GvLWQk4iAQ+/s3R4pyDEvaptyk=; b=UZhasAFYQkzlsLFwD1jstijtbBJIrozdyFEAShx2Cej1JlAqWdBrxrv6AJ4QOzCHy9 tQtNuLiHrWSMwmT4+4xzALUSUbAOeAalJTxf0C9+NktiBW2kq7+AvoNmrcov0TFMhK6S U0u0RFDKnjcP1T24ni5l86v3inR3/9m0bFSZEfgZfpfeuLhJAKa2qDCI8dthu6IJpoxU cGlQL4XM8JQpQ7x9mvKkXR7Q2V7M4oXMLsqPgVxDWWhqpeOguJ43rhSYVBYdgSsTqq4E Dg3tLmcSCNIzOUrePFSG1J/AdzzC0Pqv+UdLIHjMGmscO/HZ9s9jqu7oNR52M5Ci9W9F Nj6Q== X-Gm-Message-State: AOJu0Yx+9c3vC7EqYzXgcFQkqnvfS+BVjXBqNbmiEm6Q22h3oBTlu4Wj PV1m5UNf2s5DhtYTXAXQpFzMl7+VWjnYT0ztuB/2q0F03gi46SLsCl5IlmTr05FPThI0Z/D9z1r 0 X-Gm-Gg: ASbGnctmB0hB58lHPH3O8ddlHzRRVf6FDnH81iErgvLwWTlnMkPlyjA2XSa7OgfWGE/ IkHMtS3qIOCG6KTIkQnNb7jl2dLOyh/VOuh3Ql5IJcv2oxvvMfmEVAxKX0LEZnlC4jADplZ3ImP RnvuAQ90dK4a9Uy7CRJv6uL/pJvMQBDwLLvO/MfFZJLYWeD1sBI62TR2PwBfJS8dROTVzPU+ZJW luvs94VRMsw3xJB08RxvZEt0O6LdiylIDjOKeBo4ttwPdwrJQpn05jtEZZKth6iRdAw2ty2rW/m bUCic+88pYm6hvaGtRXTpeA7plv/fNzQrRkbfI753icZIdFheIKq5aPcYHRrmhdUU/aUCLBDIzz LRkLdT3u9S9A= X-Google-Smtp-Source: AGHT+IEXfQ8MaK3uGSzdmc4hzEM4xER01btUhd+yn5FrwCtOOjvoRd/HgC0pKaFssgBZQ8J2qv2eDA== X-Received: by 2002:a05:6a00:4fd6:b0:736:fff2:9ac with SMTP id d2e1a72fcca58-73905a2780bmr29178545b3a.23.1742942646941; Tue, 25 Mar 2025 15:44:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH v2 03/11] hw/core/cpu: Use size_t for memory_rw_debug len argument Date: Tue, 25 Mar 2025 15:43:55 -0700 Message-ID: <20250325224403.4011975-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325224403.4011975-1-richard.henderson@linaro.org> References: <20250325224403.4011975-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742942716976019000 Match the prototype of cpu_memory_rw_debug(). Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/sparc/mmu_helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5d11d26556..abd8764e83 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -154,7 +154,7 @@ struct CPUClass { =20 int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, - uint8_t *buf, int len, bool is_write); + uint8_t *buf, size_t len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); int64_t (*get_arch_id)(CPUState *cpu); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 462bcb6c0e..68f8c21e7c 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -604,7 +604,7 @@ void dump_mmu(CPUSPARCState *env); =20 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, - uint8_t *buf, int len, bool is_write); + uint8_t *buf, size_t len, bool is_write); #endif =20 /* translate.c */ diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 7548d01777..3821cd91ec 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -389,7 +389,7 @@ void dump_mmu(CPUSPARCState *env) * that the sparc ABI is followed. */ int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address, - uint8_t *buf, int len, bool is_write) + uint8_t *buf, size_t len, bool is_write) { CPUSPARCState *env =3D cpu_env(cs); target_ulong addr =3D address; --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742942985; cv=none; d=zohomail.com; s=zohoarc; b=WLHUEahOJ9Peayz8+2pZ+dwkIekKZrTAqlMBKFMJvsGN7qNSoSZ3YWvyaM6vcWhEc8Qay3V6XZehF0PCquBf7Oa+/3/lcpt+MzJIm3+ScG/ZM7fZw4cSZHrBWYySf7K+fX0b/WuiSyYvDojrn1Rlfu1QjaQkPEptSNW/BA3R9tI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742942985; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=whE4tOIG14eY8JQ2gptqlrplDWnqt4RDL3Ybv6G0d7s=; b=RtKjtsUfrWZ0wKqEUAUfJEQ2Vhc4OEV0MnnKcI4cJRJpTuFunyDZvJin7olSGKwwF3h1dysBdMbNw64xT/ZgnyZbpHwv2r2/ZMeJMI6JwbzT9yMoW1nPXQwP3yjMZclCc5iWFyY4I0/WbQv3T9xmK8r2HD9f3iLZ6HMyNDguy8Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742942985886761.1729363681089; Tue, 25 Mar 2025 15:49:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1txD0Y-0002fD-Tf; Tue, 25 Mar 2025 18:44:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1txD0G-0001TV-ER for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:12 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1txD0D-00072p-0e for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:12 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-223a7065ff8so65114635ad.0 for ; Tue, 25 Mar 2025 15:44:08 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu.h | 2 -- target/avr/helper.c | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 06f5ae4d1b..84a8f5cc8c 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -60,8 +60,6 @@ #define OFFSET_CODE 0x00000000 /* CPU registers, IO registers, and SRAM */ #define OFFSET_DATA 0x00800000 -/* CPU registers specifically, these are mapped at the start of data */ -#define OFFSET_CPU_REGISTERS OFFSET_DATA /* * IO registers, including status register, stack pointer, and memory * mapped peripherals, mapped just after CPU registers diff --git a/target/avr/helper.c b/target/avr/helper.c index 3412312ad5..e5bf16c6b7 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -340,8 +340,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uin= t32_t addr) env->fullacc =3D false; =20 /* Following logic assumes this: */ - assert(OFFSET_CPU_REGISTERS =3D=3D OFFSET_DATA); - assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_CPU_REGISTERS + + assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_DATA + NUMBER_OF_CPU_REGISTERS); =20 if (addr < NUMBER_OF_CPU_REGISTERS) { --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742942981; cv=none; d=zohomail.com; s=zohoarc; b=fwhmYYz3nq3/Q82QWZq3ei3tpBBGWTANDMLnFfYx3I7ifMy79DWzgkDSDIz9M6aFC84QBExAlYL7Ga7BiYiUnpDeE6yjk7cafN0bmXEMsvvfPlRIajQIfLAr9WC94k7sGTvWbT7NKwZR9RJ4jp6+x9gIyb780WoglWjmLhTmuMA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742942981; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zAHr9PqknqCL0FB0Tc4WFmI5gr2YFriYH/85HJUA/+I=; b=KHCfk68NIk4K1kU/J6D9ZHrGNpmiJc/hH7JMXPhcJjXp57HjzrDQccvG5VTc94nzbi+uZrM6MA8h6knWuoOUp5wyoXKzzb9yZhnjEPGd3fpUHUVR6kc5ffEqICd4kwwjAo0DOeOx1AlzAYJ2PTN1b24oFZ+XRr8yjBzDhRHaS88= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742942981303798.5868581048138; Tue, 25 Mar 2025 15:49:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1txD0g-00039X-7j; Tue, 25 Mar 2025 18:44:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1txD0L-0001ni-62 for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:17 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1txD0D-000738-Mp for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:16 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2243803b776so3634615ad.0 for ; Tue, 25 Mar 2025 15:44:09 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 84a8f5cc8c..b49e7a7056 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -44,8 +44,6 @@ =20 /* Number of CPU registers */ #define NUMBER_OF_CPU_REGISTERS 32 -/* Number of IO registers accessible by ld/st/in/out */ -#define NUMBER_OF_IO_REGISTERS 64 =20 /* * Offsets of AVR memory regions in host memory space. --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742943010; cv=none; d=zohomail.com; s=zohoarc; b=YBm99I9FJojbQbHoKfiiZkD8zvCOGWpjQy8qCHCcnopqK/Rn+5bWaBZOSan1uyU8WKLYB5a8kFGV5wR47j6Mcn+GlXXyxTTF9LRy0eVpqQqMDdGzx/i9hXkXA5E77NXqKQZ28TAwzE8PH59pZlcdJ492btgTpIW6tTgLsib5LcY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742943010; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NysG+klqlTH+Cqa+DgVibFr5yz9FYb8KE+rqeZdAsXI=; b=NnOcOSmdii10lNfJwBIZlK9aPNEckKrbKDrHNJVI1PAvFsr1SO6cKf/vf5F5smvOXFaasyYAuRy/LipOvvFwJoM//iOB96c8lE48sycp4+ggAoJILmHRobLxTm/Ecxsbd+Xtmmjyanjxl4sI6szCe/DbW/OLyBnw5ZbQ7sTIzKU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742943010186376.2338367658597; Tue, 25 Mar 2025 15:50:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1txD0a-0002ml-4Q; Tue, 25 Mar 2025 18:44:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1txD0H-0001WR-1c for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:13 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1txD0E-00073P-DL for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:12 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-224171d6826so54962655ad.3 for ; Tue, 25 Mar 2025 15:44:09 -0700 (PDT) Received: from stoup.. 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Tue, 25 Mar 2025 15:44:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH v2 06/11] target/avr: Add defines for i/o port registers Date: Tue, 25 Mar 2025 15:43:58 -0700 Message-ID: <20250325224403.4011975-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325224403.4011975-1-richard.henderson@linaro.org> References: <20250325224403.4011975-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742943013294019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 10 ++++++++++ target/avr/helper.c | 36 ++++++++++++++++++------------------ 2 files changed, 28 insertions(+), 18 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index b49e7a7056..ebcdda20ac 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -45,6 +45,16 @@ /* Number of CPU registers */ #define NUMBER_OF_CPU_REGISTERS 32 =20 +/* CPU registers mapped into i/o ports 0x38-0x3f. */ +#define REG_38_RAMPD 0 +#define REG_38_RAMPX 1 +#define REG_38_RAMPY 2 +#define REG_38_RAMPZ 3 +#define REG_38_EIDN 4 +#define REG_38_SPL 5 +#define REG_38_SPH 6 +#define REG_38_SREG 7 + /* * Offsets of AVR memory regions in host memory space. * diff --git a/target/avr/helper.c b/target/avr/helper.c index e5bf16c6b7..f8ada8b106 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -216,29 +216,29 @@ target_ulong helper_inb(CPUAVRState *env, uint32_t po= rt) { target_ulong data =3D 0; =20 - switch (port) { - case 0x38: /* RAMPD */ + switch (port - 0x38) { + case REG_38_RAMPD: data =3D 0xff & (env->rampD >> 16); break; - case 0x39: /* RAMPX */ + case REG_38_RAMPX: data =3D 0xff & (env->rampX >> 16); break; - case 0x3a: /* RAMPY */ + case REG_38_RAMPY: data =3D 0xff & (env->rampY >> 16); break; - case 0x3b: /* RAMPZ */ + case REG_38_RAMPZ: data =3D 0xff & (env->rampZ >> 16); break; - case 0x3c: /* EIND */ + case REG_38_EIDN: data =3D 0xff & (env->eind >> 16); break; - case 0x3d: /* SPL */ + case REG_38_SPL: data =3D env->sp & 0x00ff; break; - case 0x3e: /* SPH */ + case REG_38_SPH: data =3D env->sp >> 8; break; - case 0x3f: /* SREG */ + case REG_38_SREG: data =3D cpu_get_sreg(env); break; default: @@ -265,39 +265,39 @@ void helper_outb(CPUAVRState *env, uint32_t port, uin= t32_t data) { data &=3D 0x000000ff; =20 - switch (port) { - case 0x38: /* RAMPD */ + switch (port - 0x38) { + case REG_38_RAMPD: if (avr_feature(env, AVR_FEATURE_RAMPD)) { env->rampD =3D (data & 0xff) << 16; } break; - case 0x39: /* RAMPX */ + case REG_38_RAMPX: if (avr_feature(env, AVR_FEATURE_RAMPX)) { env->rampX =3D (data & 0xff) << 16; } break; - case 0x3a: /* RAMPY */ + case REG_38_RAMPY: if (avr_feature(env, AVR_FEATURE_RAMPY)) { env->rampY =3D (data & 0xff) << 16; } break; - case 0x3b: /* RAMPZ */ + case REG_38_RAMPZ: if (avr_feature(env, AVR_FEATURE_RAMPZ)) { env->rampZ =3D (data & 0xff) << 16; } break; - case 0x3c: /* EIDN */ + case REG_38_EIDN: env->eind =3D (data & 0xff) << 16; break; - case 0x3d: /* SPL */ + case REG_38_SPL: env->sp =3D (env->sp & 0xff00) | (data); break; - case 0x3e: /* SPH */ + case REG_38_SPH: if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { env->sp =3D (env->sp & 0x00ff) | (data << 8); } break; - case 0x3f: /* SREG */ + case REG_38_SREG: cpu_set_sreg(env, data); break; default: --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7390611d3d6sm11111321b3a.94.2025.03.25.15.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Mar 2025 15:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742942650; x=1743547450; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LrFDnHMmWJfXB60eSeV67OXTaZn6ARvWbGPfUJmm+OE=; b=EuHkGh9pl4yJ/+3iDeU3OKpY3vk1b1NV/UW0o+nyfIx2n0cNAnETROd6u9wWyViPD3 0ugysLkSTuu05PQzO3BE7Kz+dBPtZ7s/zlslsRkG8Uq4niQ/uWP3phPbAa/egdC748pv 5pI+qXbd2Q/jnbjCm1BhKUzMO0uh8mUwOsNSmd2CM1kzLt5i3PAywtVIlh/rDef+eoOT Y1q3m6/UZ+ErTTCI48jba6g8/kfg/uL2EOraqKqhHRbUl4OazwBOL6LRx0HF+vCiOznY UxHORp1VgiC88kGMTsFlm4ICRaiCQ5RVwkPRxUKK4ekF4nalXYrPXqXY3Y4PgMLiJLtd hPbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742942650; x=1743547450; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LrFDnHMmWJfXB60eSeV67OXTaZn6ARvWbGPfUJmm+OE=; b=v8wRdtnnAEc5ruuBxyMq7NSHZhCqaYTgH1P1QCG70nwxpG6d+tb53vvaOQ7ei1Okg4 NZVlbeowUVyot+qSyrwgvoVBS6JZPvfNtKlcqcn+113esheYWvgkBFGWlYpOm6jvRBqx nSkO5lFq0DNeaSXY/n6zqaR18ugkR1x65socprOXbogmeomRyoOZscDyaOJy3yFV3m9z CKfJjQeW69+CG5/gHtIIoYeAuHF66QoY9rqPq4s7fjgP0bjY6IhjhjiQOM8VzJldOykS 9tnBuhsJbXhCxKR1xHtM0zmma+99guNPZCrjShD4DiWPU89dkpqQyF3pd8lDceH2n5pp q/Pw== X-Gm-Message-State: AOJu0YzS1u4zhhTpRTNackXhMXUiqV+kF+Jv+Ayk/h2+QDSZO75wPBny M4gJ6J24EaooJnDVvWFHWSChaMG4gX81s24N8BISUEON7Sa8n0NRNtM7PnsZvc4QHxqC5lAHY76 N X-Gm-Gg: ASbGnctM2AzaPQyBzbISrnuNjq5sPX047kVfgevI+UfxtHDbg+Yuij0EWHSS2kUqrg3 Ngq+QhJI6ClUjEWTyYB3vO9CuVi2hPnts3CJ6mu9vAeqMoQoCK943t/yacK4EeH+xNWVz3ykjXX qSlgPEwVdMnw0BNnytkvc9LoTxTqjPAppO3Hi6g75dXrKHgJBByq+5r/R+jfBPF2LYDjM9Z4KBT seF1ACevQPJk3l7Go8BmJSw2QgYheZH6+2t2kOKBIa/MIvT/q/JF9iya2kuvqfCwDkyDJKB3dLb /ZL+WgFWGioE2qe99ky3nch2+u54Bn8f3/HZP6VNxR9nB4TtLsvS6UdU8/C5VEkXpXcGmS8cTVN oaJxbYx3rla0= X-Google-Smtp-Source: AGHT+IHZoKay7xkNt+A5BnsBHDgWoYPUxFEDpiytfhCiXsyx/niH+JO1BWSY83rfA/RODfojNsXmGA== X-Received: by 2002:a05:6a00:ac4:b0:736:4c93:1bdf with SMTP id d2e1a72fcca58-73905a275famr27518953b3a.18.1742942649884; Tue, 25 Mar 2025 15:44:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH v2 07/11] target/avr: Move cpu register accesses into system memory Date: Tue, 25 Mar 2025 15:43:59 -0700 Message-ID: <20250325224403.4011975-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325224403.4011975-1-richard.henderson@linaro.org> References: <20250325224403.4011975-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742942695920019000 Content-Type: text/plain; charset="utf-8" Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into the cpu registers with normal address space accesses. We no longer need to trap accesses to the first page within avr_cpu_tlb_fill but can wait until a write occurs. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 7 ++ target/avr/helper.h | 3 - target/avr/cpu.c | 16 +++ target/avr/helper.c | 223 +++++++++++++++++------------------------ target/avr/translate.c | 42 ++++---- 5 files changed, 138 insertions(+), 153 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index ebcdda20ac..9862705c6a 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memory.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" @@ -150,6 +151,9 @@ struct ArchCPU { =20 CPUAVRState env; =20 + MemoryRegion cpu_reg1; + MemoryRegion cpu_reg2; + /* Initial value of stack pointer */ uint32_t init_sp; }; @@ -250,6 +254,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +extern const MemoryRegionOps avr_cpu_reg1; +extern const MemoryRegionOps avr_cpu_reg2; + #include "exec/cpu-all.h" =20 #endif /* QEMU_AVR_CPU_H */ diff --git a/target/avr/helper.h b/target/avr/helper.h index 4d02e648fa..e8d13e925f 100644 --- a/target/avr/helper.h +++ b/target/avr/helper.h @@ -23,7 +23,4 @@ DEF_HELPER_1(debug, noreturn, env) DEF_HELPER_1(break, noreturn, env) DEF_HELPER_1(sleep, noreturn, env) DEF_HELPER_1(unsupported, noreturn, env) -DEF_HELPER_3(outb, void, env, i32, i32) -DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(fullwr, void, env, i32, i32) -DEF_HELPER_2(fullrd, tl, env, i32) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 834c7082aa..0b14b36c17 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/exec-all.h" #include "exec/translation-block.h" +#include "exec/address-spaces.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -110,6 +111,8 @@ static void avr_cpu_disas_set_info(CPUState *cpu, disas= semble_info *info) static void avr_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + CPUAVRState *env =3D cpu_env(cs); + AVRCPU *cpu =3D env_archcpu(env); AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 @@ -122,6 +125,19 @@ static void avr_cpu_realizefn(DeviceState *dev, Error = **errp) cpu_reset(cs); =20 mcc->parent_realize(dev, errp); + + /* + * Two blocks in the low data space loop back into cpu registers. + */ + memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, + "avr-cpu-reg1", 32); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA, &cpu->cpu_reg1); + + memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, + "avr-cpu-reg2", 8); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + 0x58, &cpu->cpu_reg2); } =20 static void avr_cpu_set_int(void *opaque, int irq, int level) diff --git a/target/avr/helper.c b/target/avr/helper.c index f8ada8b106..d0e86f5614 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -108,7 +108,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - int prot, page_size =3D TARGET_PAGE_SIZE; + int prot; uint32_t paddr; =20 address &=3D TARGET_PAGE_MASK; @@ -133,23 +133,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, /* Access to memory. */ paddr =3D OFFSET_DATA + address; prot =3D PAGE_READ | PAGE_WRITE; - if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* - * Access to CPU registers, exit and rebuilt this TB to use - * full access in case it touches specially handled registers - * like SREG or SP. For probing, set page_size =3D 1, in order - * to force tlb_fill to be called for the next access. - */ - if (probe) { - page_size =3D 1; - } else { - cpu_env(cs)->fullacc =3D 1; - cpu_loop_exit_restore(cs, retaddr); - } - } } =20 - tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } =20 @@ -203,134 +189,78 @@ void helper_wdr(CPUAVRState *env) } =20 /* - * This function implements IN instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is read and returned - * b. otherwise io address is translated to mem address and physical memo= ry - * is read. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation - * + * The first 32 bytes of the data space are mapped to the cpu regs. + * We cannot write these from normal store operations because TCG + * does not expect global temps to be modified -- a global may be + * live in a host cpu register across the store. We can however + * read these, as TCG does make sure the global temps are saved + * in case the load operation traps. */ -target_ulong helper_inb(CPUAVRState *env, uint32_t port) + +static uint64_t avr_cpu_reg1_read(void *opaque, hwaddr addr, unsigned size) { - target_ulong data =3D 0; + CPUAVRState *env =3D opaque; =20 - switch (port - 0x38) { - case REG_38_RAMPD: - data =3D 0xff & (env->rampD >> 16); - break; - case REG_38_RAMPX: - data =3D 0xff & (env->rampX >> 16); - break; - case REG_38_RAMPY: - data =3D 0xff & (env->rampY >> 16); - break; - case REG_38_RAMPZ: - data =3D 0xff & (env->rampZ >> 16); - break; - case REG_38_EIDN: - data =3D 0xff & (env->eind >> 16); - break; - case REG_38_SPL: - data =3D env->sp & 0x00ff; - break; - case REG_38_SPH: - data =3D env->sp >> 8; - break; - case REG_38_SREG: - data =3D cpu_get_sreg(env); - break; - default: - /* not a special register, pass to normal memory access */ - data =3D address_space_ldub(&address_space_memory, - OFFSET_IO_REGISTERS + port, - MEMTXATTRS_UNSPECIFIED, NULL); - } - - return data; + assert(addr < 32); + return env->r[addr]; } =20 /* - * This function implements OUT instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is written into the re= gister - * b. otherwise io address is translated to mem address and physical mem= ory - * is written. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementati= on - * + * The range 0x38-0x3f of the i/o space is mapped to cpu regs. + * As above, we cannot write these from normal store operations. */ -void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) -{ - data &=3D 0x000000ff; =20 - switch (port - 0x38) { +static uint64_t avr_cpu_reg2_read(void *opaque, hwaddr addr, unsigned size) +{ + CPUAVRState *env =3D opaque; + + switch (addr) { case REG_38_RAMPD: - if (avr_feature(env, AVR_FEATURE_RAMPD)) { - env->rampD =3D (data & 0xff) << 16; - } - break; + return 0xff & (env->rampD >> 16); case REG_38_RAMPX: - if (avr_feature(env, AVR_FEATURE_RAMPX)) { - env->rampX =3D (data & 0xff) << 16; - } - break; + return 0xff & (env->rampX >> 16); case REG_38_RAMPY: - if (avr_feature(env, AVR_FEATURE_RAMPY)) { - env->rampY =3D (data & 0xff) << 16; - } - break; + return 0xff & (env->rampY >> 16); case REG_38_RAMPZ: - if (avr_feature(env, AVR_FEATURE_RAMPZ)) { - env->rampZ =3D (data & 0xff) << 16; - } - break; + return 0xff & (env->rampZ >> 16); case REG_38_EIDN: - env->eind =3D (data & 0xff) << 16; - break; + return 0xff & (env->eind >> 16); case REG_38_SPL: - env->sp =3D (env->sp & 0xff00) | (data); - break; + return env->sp & 0x00ff; case REG_38_SPH: - if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { - env->sp =3D (env->sp & 0x00ff) | (data << 8); - } - break; + return 0xff & (env->sp >> 8); case REG_38_SREG: - cpu_set_sreg(env, data); - break; - default: - /* not a special register, pass to normal memory access */ - address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + por= t, - data, MEMTXATTRS_UNSPECIFIED, NULL); + return cpu_get_sreg(env); } + g_assert_not_reached(); } =20 -/* - * this function implements LD instruction when there is a possibility to= read - * from a CPU register - */ -target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) +static void avr_cpu_trap_write(void *opaque, hwaddr addr, + uint64_t data64, unsigned size) { - uint8_t data; + CPUAVRState *env =3D opaque; + CPUState *cs =3D env_cpu(env); =20 - env->fullacc =3D false; - - if (addr < NUMBER_OF_CPU_REGISTERS) { - /* CPU registers */ - data =3D env->r[addr]; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - data =3D helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS); - } else { - /* memory */ - data =3D address_space_ldub(&address_space_memory, OFFSET_DATA + a= ddr, - MEMTXATTRS_UNSPECIFIED, NULL); - } - return data; + env->fullacc =3D true; + cpu_loop_exit_restore(cs, cs->mem_io_pc); } =20 +const MemoryRegionOps avr_cpu_reg1 =3D { + .read =3D avr_cpu_reg1_read, + .write =3D avr_cpu_trap_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + +const MemoryRegionOps avr_cpu_reg2 =3D { + .read =3D avr_cpu_reg2_read, + .write =3D avr_cpu_trap_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + /* * this function implements ST instruction when there is a possibility to= write * into a CPU register @@ -339,19 +269,50 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, u= int32_t addr) { env->fullacc =3D false; =20 - /* Following logic assumes this: */ - assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_DATA + - NUMBER_OF_CPU_REGISTERS); - - if (addr < NUMBER_OF_CPU_REGISTERS) { + switch (addr) { + case 0 ... 31: /* CPU registers */ env->r[addr] =3D data; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data); - } else { - /* memory */ + break; + + case REG_38_RAMPD + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPD)) { + env->rampD =3D data << 16; + } + break; + case REG_38_RAMPX + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPX)) { + env->rampX =3D data << 16; + } + break; + case REG_38_RAMPY + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPY)) { + env->rampY =3D data << 16; + } + break; + case REG_38_RAMPZ + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPZ)) { + env->rampZ =3D data << 16; + } + break; + case REG_38_EIDN + 0x38 + NUMBER_OF_CPU_REGISTERS: + env->eind =3D data << 16; + break; + case REG_38_SPL + 0x38 + NUMBER_OF_CPU_REGISTERS: + env->sp =3D (env->sp & 0xff00) | data; + break; + case REG_38_SPH + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { + env->sp =3D (env->sp & 0x00ff) | (data << 8); + } + break; + case REG_38_SREG + 0x38 + NUMBER_OF_CPU_REGISTERS: + cpu_set_sreg(env, data); + break; + + default: address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, MEMTXATTRS_UNSPECIFIED, NULL); + break; } } diff --git a/target/avr/translate.c b/target/avr/translate.c index e7f8ced9b3..0490936cd5 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -194,6 +194,9 @@ static bool avr_have_feature(DisasContext *ctx, int fea= ture) static bool decode_insn(DisasContext *ctx, uint16_t insn); #include "decode-insn.c.inc" =20 +static void gen_inb(DisasContext *ctx, TCGv data, int port); +static void gen_outb(DisasContext *ctx, TCGv data, int port); + /* * Arithmetic Instructions */ @@ -1293,9 +1296,8 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_EQ; ctx->skip_var0 =3D data; @@ -1311,9 +1313,8 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_NE; ctx->skip_var0 =3D data; @@ -1502,11 +1503,18 @@ static void gen_data_store(DisasContext *ctx, TCGv = data, TCGv addr) =20 static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { - if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { - gen_helper_fullrd(data, tcg_env, addr); - } else { - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); - } + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); +} + +static void gen_inb(DisasContext *ctx, TCGv data, int port) +{ + gen_data_load(ctx, data, tcg_constant_i32(port + NUMBER_OF_CPU_REGISTE= RS)); +} + +static void gen_outb(DisasContext *ctx, TCGv data, int port) +{ + gen_helper_fullwr(tcg_env, data, + tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS)); } =20 /* @@ -2126,9 +2134,8 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) static bool trans_IN(DisasContext *ctx, arg_IN *a) { TCGv Rd =3D cpu_r[a->rd]; - TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_inb(Rd, tcg_env, port); + gen_inb(ctx, Rd, a->imm); return true; } =20 @@ -2139,9 +2146,8 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) static bool trans_OUT(DisasContext *ctx, arg_OUT *a) { TCGv Rd =3D cpu_r[a->rd]; - TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_outb(tcg_env, port, Rd); + gen_outb(ctx, Rd, a->imm); return true; } =20 @@ -2407,11 +2413,10 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP = *a) static bool trans_SBI(DisasContext *ctx, arg_SBI *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_ori_tl(data, data, 1 << a->bit); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } =20 @@ -2422,11 +2427,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) static bool trans_CBI(DisasContext *ctx, arg_CBI *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } =20 --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742942869; cv=none; d=zohomail.com; s=zohoarc; b=AP2+DaXIUaJ2MRaGV+/SjgJLebQuOReyYp9cjXGSM+pZar7no/WrID6hzTEzkOdA132HoyHBa3EsZRHDkMpoytaI2E+itwvlKkdlGIchFkjL05yzfvSAIUI1r7mx975J6TAuPv0VFCnDNKqD8bDdQoI1WCQXd8QS5JlcooOZzOY= ARC-Message-Signature: i=1; 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Make use of the softmmu cache of the i/o page. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index d0e86f5614..7d6954ec26 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,10 +23,10 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/getpc.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" -#include "exec/address-spaces.h" #include "exec/helper-proto.h" =20 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -67,6 +67,11 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_= request) return false; } =20 +static void do_stb(CPUAVRState *env, uint32_t addr, uint8_t data, uintptr_= t ra) +{ + cpu_stb_mmuidx_ra(env, addr, data, MMU_DATA_IDX, ra); +} + void avr_cpu_do_interrupt(CPUState *cs) { CPUAVRState *env =3D cpu_env(cs); @@ -311,8 +316,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uin= t32_t addr) break; =20 default: - address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, - MEMTXATTRS_UNSPECIFIED, NULL); + do_stb(env, addr, data, GETPC()); break; } } --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742942778; cv=none; d=zohomail.com; s=zohoarc; b=gs/bx62hbaRP6AOw0mvgN0+CYwDLVr6PIerUPRp8mPkQJ7dKICcT6jTxkSYArifGQroEiHIFu3kOPUbvvCJjVa5ffCDiAQ2s5BxHjsPzdQQPHc8gYnrH5A/3mkU1J1Bf2G9gcc0f2a3L7LBt5KlIg0lf2QNkOwjGIb0DENRXuC8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742942778; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DUF+4Y4/PqO50T2IhlnvWA6B/DIxYokH9Y5du5vjVAo=; b=RG+XYCR4MNVRsaWO4A86176LFLA4ElWpNqNq2HoGUERK6t5jF2gIlbdqmrrrt/nR2cG/RMPHrWqXFyDhs1pV11qKvVT5DQJbi/WrnTSsMjOf5tjsoWypYox5zY+IehAfsjcq0h0e4Zq//REZYTYRY3PJEKpmtyeaYSYUEIFUuM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742942777998989.5002139508891; Tue, 25 Mar 2025 15:46:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1txD0e-00030m-Jj; Tue, 25 Mar 2025 18:44:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1txD0L-0001hd-34 for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:17 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1txD0G-00074n-TO for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:15 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-22435603572so114894755ad.1 for ; Tue, 25 Mar 2025 15:44:12 -0700 (PDT) Received: from stoup.. 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Tue, 25 Mar 2025 15:44:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH v2 09/11] target/avr: Use do_stb in avr_cpu_do_interrupt Date: Tue, 25 Mar 2025 15:44:01 -0700 Message-ID: <20250325224403.4011975-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325224403.4011975-1-richard.henderson@linaro.org> References: <20250325224403.4011975-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742942779162019000 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index 7d6954ec26..f23fa3e8ba 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -88,14 +88,14 @@ void avr_cpu_do_interrupt(CPUState *cs) } =20 if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); - cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); + do_stb(env, env->sp--, ret >> 16, 0); } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); } else { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); + do_stb(env, env->sp--, ret, 0); } =20 env->pc_w =3D base + vector * size; --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742943005; cv=none; d=zohomail.com; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7390611d3d6sm11111321b3a.94.2025.03.25.15.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Mar 2025 15:44:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742942652; x=1743547452; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=my/amCjVPulkTASqhfbzg7kjMYbxalxX57V5rEPDp7E=; b=cqWuDF+2YwWSWcnajvmr+G2JCtfnDSgAlP7t0wkOBtKkuJeW/PDHgGU4lzxk2DFzIq pFoeoHeH21UrovO/v6Ip9Uceg+rN6OIqzFbsL9y3x07+JzRK4Bkq83fXcR16hV743MKh aXrmwBo2B4eavTvFxXkAOJIuCQ3menhWlWHjsr2UhAnGSeC0955obO99S/AQum9qPc8E vtSTwBEl+NelcdcbrcFV1I03QWGtJNs5qiLR5Qbl0748z6mtbFDhzTRPJThqo8uR+0dz vcYe2rdWBnsHmnA23AmiGboZ0YdD+V40AsXx4pfgYXw5WU9Xzkwsu3MJpexs929IQqKp YHgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742942652; x=1743547452; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=my/amCjVPulkTASqhfbzg7kjMYbxalxX57V5rEPDp7E=; b=RZGnqLJDmwkOM0SrHcPDAh+hf8gcbycdy1047wisSd7x6d1XmEckNBwi+1ufDLXi3s 4/6IPDl7B0HJMTPxM4LsCsXQPhGMnNfxw84jV6nm0SEGr9beycUiK7aplLmnHu/XUWw2 zeVTvVTYGVDUZP2oJ7bWmzxtD1JVD7gYaeSPOqXNIznNOIjKX777sQuUsdUaa7FupZPd C7eQkP1hbFWyk07uvLeM2Ssi9yOf/JTthNCdbgNVHtg+PlE/tnDasf9hWaxoNORVfU+G yPgC4CfLXRFmv5lIYM3QCoO32Gr4spctEW4h+ijXBZImVWekzeV6Z3Ot255/5F/6exHs P02w== X-Gm-Message-State: AOJu0YyJY8ifupy6ZNfG9SYZhh5B5MaLFa0AsPRlaIZBqKDs8fV6pO4N n4JktylLCJAFDjt3Bj3jyqDDjTJ/JLg2SUEdYs4AqNfdUbDyHROu/9sWq8koKzoUUGUy4MMqQG9 7 X-Gm-Gg: ASbGncvuNJNdt3dUh4SSDL/PDSf2T0USdcBB/aoJ32/5KSc/BziYK4KGX1dfkRhvPkl X+6list+Zas53OReo/MqIr4/9+b42k4iYJCRY9nTiOQ8uY1BkXaYFmnrpA+TT57PBYmMp3dUxrP pI3uoiRiFezv+HbBg4zY2ESiL+R4NhrzFgAYIVlln3H78vWRcsn105MoWC34rrrFJOQUkPXiADb MapReLOJ7o6eNciZUrTm1gCFCGdLlLP87rIZ/GyhfQ1EauvE0R4KTnQkAjo0nlz0Ubd073HHZfX Z2OKPFbpuXdK5u8BZVa1zZVQXiz0NKa8/dAsYz76DtdhHRzmAfeOjMWPHm/sUKNp/tPVOwF72Oo 7M3BaeqpKOpA= X-Google-Smtp-Source: AGHT+IEszGH0V/rAOIia344CQu0LmDGG4ehRgPGlgICY3wuExP5TSQdw9x22gU+E54/rb4XuSFp8TQ== X-Received: by 2002:a05:6a20:7347:b0:1ee:e2ac:5159 with SMTP id adf61e73a8af0-1fe42f53152mr31245781637.19.1742942651963; Tue, 25 Mar 2025 15:44:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH v2 10/11] hw/avr: Prepare for TARGET_PAGE_SIZE > 256 Date: Tue, 25 Mar 2025 15:44:02 -0700 Message-ID: <20250325224403.4011975-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325224403.4011975-1-richard.henderson@linaro.org> References: <20250325224403.4011975-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742943006161019000 Content-Type: text/plain; charset="utf-8" If i/o does not cover the entire first page, allocate a portion of ram as an i/o device, so that the entire first page is i/o. While memory_region_init_ram_device_ptr is happy to allocate the RAMBlock, it does not register the ram for migration. Do this by hand. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- hw/avr/atmega.h | 1 + hw/avr/atmega.c | 39 ++++++++++++++++++++++++++++++++------- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h index a99ee15c7e..9ac4678231 100644 --- a/hw/avr/atmega.h +++ b/hw/avr/atmega.h @@ -41,6 +41,7 @@ struct AtmegaMcuState { MemoryRegion flash; MemoryRegion eeprom; MemoryRegion sram; + MemoryRegion sram_io; DeviceState *io; AVRMaskState pwr[POWER_MAX]; AVRUsartState usart[USART_MAX]; diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index f6844bf118..11fab184de 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -19,6 +19,7 @@ #include "hw/sysbus.h" #include "qom/object.h" #include "hw/misc/unimp.h" +#include "migration/vmstate.h" #include "atmega.h" =20 enum AtmegaPeripheral { @@ -224,8 +225,6 @@ static void atmega_realize(DeviceState *dev, Error **er= rp) char *devname; size_t i; =20 - assert(mc->io_size <=3D 0x200); - if (!s->xtal_freq_hz) { error_setg(errp, "\"xtal-frequency-hz\" property must be provided.= "); return; @@ -240,11 +239,37 @@ static void atmega_realize(DeviceState *dev, Error **= errp) qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev =3D DEVICE(&s->cpu); =20 - /* SRAM */ - memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size, - &error_abort); - memory_region_add_subregion(get_system_memory(), - OFFSET_DATA + mc->io_size, &s->sram); + /* + * SRAM + * + * Softmmu is not able mix i/o and ram on the same page. + * Therefore in all cases, the first page exclusively contains i/o. + * + * If the MCU's i/o region matches the page size, then we can simply + * allocate all ram starting at the second page. Otherwise, we must + * allocate some ram as i/o to complete the first page. + */ + assert(mc->io_size =3D=3D 0x100 || mc->io_size =3D=3D 0x200); + if (mc->io_size >=3D TARGET_PAGE_SIZE) { + memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_siz= e, + &error_abort); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + mc->io_size, &s->sram); + } else { + int sram_io_size =3D TARGET_PAGE_SIZE - mc->io_size; + void *sram_io_mem =3D g_malloc0(sram_io_size); + + memory_region_init_ram_device_ptr(&s->sram_io, OBJECT(dev), "sram-= as-io", + sram_io_size, sram_io_mem); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + mc->io_size, &s->sram_io= ); + vmstate_register_ram(&s->sram_io, dev); + + memory_region_init_ram(&s->sram, OBJECT(dev), "sram", + mc->sram_size - sram_io_size, &error_abort); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + TARGET_PAGE_SIZE, &s->sr= am); + } =20 /* Flash */ memory_region_init_rom(&s->flash, OBJECT(dev), --=20 2.43.0 From nobody Wed Apr 2 13:34:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742942961; cv=none; d=zohomail.com; s=zohoarc; b=M3m8k4q9CPWclmCx6MXXUny4zSL/E5OhzNZLn4r9FmbL4R2ZZXk0VpMJA4VibVU+txjliGi5/9+QZmkaqQEMji/c2NjZv4QJm3aeDAJgXBi0vNlAPAoIuLZvtwUpEpgLu60x1b/H1rz2B5NWFdkmDKYCBWCmP4sR4dtKZHYe4Gk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742942961; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1fPwSz5GvcZ1Wj62YV7bWBMY5Lb2GJ48t6nbamWgO3Q=; b=P1c+ZsnrM2mkLmnCLfK891r8loiLUk85UCDdU9/zVeNYx+5QgC2cqKcvKIWUk61ZxP+5fLAfUvAXWoUAEEuptPasr8CWdobxZ8dlkMsII+UkiWUbqvngZPRA12HUGehtoysC1DznumiuuUhgemg7taTMZyI+zGuNbPJJJkWVVbU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174294296172032.046734269345734; Tue, 25 Mar 2025 15:49:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1txD0b-0002sm-BU; Tue, 25 Mar 2025 18:44:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1txD0K-0001km-KE for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:16 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1txD0I-00075K-BA for qemu-devel@nongnu.org; Tue, 25 Mar 2025 18:44:16 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-224341bbc1dso120713455ad.3 for ; Tue, 25 Mar 2025 15:44:13 -0700 (PDT) Received: from stoup.. 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Choose 10 as larger than the i/o on every MCU, just so that this path is tested. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu-param.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 81f3f49ee1..f5248ce9e7 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,13 +21,7 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H =20 -/* - * TARGET_PAGE_BITS cannot be more than 8 bits because - * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and they - * should be implemented as a device and not memory - * 2. SRAM starts at the address 0x0100 - */ -#define TARGET_PAGE_BITS 8 +#define TARGET_PAGE_BITS 10 #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 --=20 2.43.0