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Mon, 24 Mar 2025 03:08:46 -0400 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 00:08:44 -0700 Received: from emr.sh.intel.com ([10.112.229.56]) by fmviesa007.fm.intel.com with ESMTP; 24 Mar 2025 00:08:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742800125; x=1774336125; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GkePnjIVwJy2gtvDqRPqWnH+ClNauDcNXM7UqV0aetc=; b=LBgsq+rTHnlTD0vviTTkmqMKy0lqGqwKUsaEEjuQt9AnMaJ/2UtVJz+/ xtv22SctisTF6IgSDGnyDsh0lKbptsoCUYCR4ElT2YBuav5lexSyOWd+2 ft7mSyRuASGfONXR12UJta/q0VNxL6qzSX6S4E73IVhTH3LaDsL8Nh/gl CtPbFjveY2zEFLpxe+go4wBOHGw3AQKdYEGxMBJhAvd9JhFUVIZGnKrOa 30t7/2FvKg9c+K2rrJgqYFTCrJhsWVJDAU7XxWsLvRMcSw6glifuN+0j7 Hf3BCiqRZCcGHz9KCfO9sheNzt01/LmzfLYrsC+m3TaIc6ONX/UYs0Ckm A==; X-CSE-ConnectionGUID: 85qNR3FOSKOyYT8CiaXl4g== X-CSE-MsgGUID: dhHv/Z4hRvGyoTRfBE1iHA== X-IronPort-AV: E=McAfee;i="6700,10204,11382"; a="31588458" X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="31588458" X-CSE-ConnectionGUID: C9tRJ6dtTjuTepXb6kbW3Q== X-CSE-MsgGUID: uqJ5HATGRKK6tTeN6Y6cww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="123944365" From: Dapeng Mi To: Paolo Bonzini , Sean Christopherson Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Zide Chen , Xiaoyao Li , Dongli Zhang , Mingwei Zhang , Das Sandipan , Shukla Manali , Dapeng Mi , Gerd Hoffmann Subject: [PATCH 1/3] kvm: Introduce kvm_arch_pre_create_vcpu() Date: Mon, 24 Mar 2025 12:37:10 +0000 Message-Id: <20250324123712.34096-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> References: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.16; envelope-from=dapeng1.mi@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DATE_IN_FUTURE_03_06=3.027, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1742800185078116600 Content-Type: text/plain; charset="utf-8" From: Xiaoyao Li Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent work prior to create any vcpu. This is for i386 TDX because it needs call TDX_INIT_VM before creating any vcpu. The specific implemnet of i386 will be added in the future patch. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- accel/kvm/kvm-all.c | 5 +++++ include/system/kvm.h | 1 + target/arm/kvm.c | 5 +++++ target/i386/kvm/kvm.c | 5 +++++ target/loongarch/kvm/kvm.c | 5 +++++ target/mips/kvm.c | 5 +++++ target/ppc/kvm.c | 5 +++++ target/riscv/kvm/kvm-cpu.c | 5 +++++ target/s390x/kvm/kvm.c | 5 +++++ 9 files changed, 41 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index f89568bfa3..df9840e53a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -540,6 +540,11 @@ int kvm_init_vcpu(CPUState *cpu, Error **errp) =20 trace_kvm_init_vcpu(cpu->cpu_index, kvm_arch_vcpu_id(cpu)); =20 + ret =3D kvm_arch_pre_create_vcpu(cpu, errp); + if (ret < 0) { + goto err; + } + ret =3D kvm_create_vcpu(cpu); if (ret < 0) { error_setg_errno(errp, -ret, diff --git a/include/system/kvm.h b/include/system/kvm.h index ab17c09a55..d7dfa25493 100644 --- a/include/system/kvm.h +++ b/include/system/kvm.h @@ -374,6 +374,7 @@ int kvm_arch_get_default_type(MachineState *ms); =20 int kvm_arch_init(MachineState *ms, KVMState *s); =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp); int kvm_arch_init_vcpu(CPUState *cpu); int kvm_arch_destroy_vcpu(CPUState *cpu); =20 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index da30bdbb23..93f1a7245b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1874,6 +1874,11 @@ static int kvm_arm_sve_set_vls(ARMCPU *cpu) =20 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6c749d4ee8..f41e190fb8 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2051,6 +2051,11 @@ full: abort(); } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index 7f63e7c8fe..ed0ddf1cbf 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -1075,6 +1075,11 @@ static int kvm_cpu_check_pv_features(CPUState *cs, E= rror **errp) return 0; } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { uint64_t val; diff --git a/target/mips/kvm.c b/target/mips/kvm.c index d67b7c1a8e..ec53acb51a 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -61,6 +61,11 @@ int kvm_arch_irqchip_create(KVMState *s) return 0; } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { CPUMIPSState *env =3D cpu_env(cs); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 992356cb75..20fabccecd 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -479,6 +479,11 @@ static void kvmppc_hw_debug_points_init(CPUPPCState *c= env) } } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 4ffeeaa1c9..451c00f17c 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1389,6 +1389,11 @@ static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, C= PUState *cs) return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret =3D 0; diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 4d56e653dd..1f592733f4 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -404,6 +404,11 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu) return cpu->cpu_index; } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { unsigned int max_cpus =3D MACHINE(qdev_get_machine())->smp.max_cpus; --=20 2.40.1 From nobody Tue Apr 1 08:43:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1742800199; cv=none; d=zohomail.com; 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i=@intel.com; q=dns/txt; s=Intel; t=1742800128; x=1774336128; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RSPvGIZxsfM4bA/IY36Wq0EbC6TmhSvPF08yfS2Nt4k=; b=oCgY3wbDoNG85tEQf19EozkDsvlF1sQ6+BaWNlkHcAPaT1HXcUc5wONq 7F2OMwUZLZSDa/tajoCmBC7sKVp8UBLRAE2G3S/D55J7Ke81xTWEMT5+/ CahnvSQgsU5V49CB+8XOqUNoWrwvVkz8OoncYkoGbPfMaf5y0dR4yJB7P wQOuaCaZ4XsA+ksjskyeI9b160YrIBOm17kJHgA9suoiEt8//+T8NMOk3 kAce0V75ORXhJ/YKh63u2lP+XiX6kr15fSZTbuRi3rCZpSOdnQ/isSLJA p5MxeuHSvW3wh+Ig519YYO5lzIgcl13InLfkejPSxe2GHQTD88F8jUmj+ A==; X-CSE-ConnectionGUID: Kh6vU1fCRL60onHUco7K/g== X-CSE-MsgGUID: wS/RfJwBQI6Nqs9UM0+AWg== X-IronPort-AV: E=McAfee;i="6700,10204,11382"; a="31588466" X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="31588466" X-CSE-ConnectionGUID: h7j1ukYCQSqoT6dryF50Bw== X-CSE-MsgGUID: 6xu+B54JQaiEpUbobTY1pw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="123944393" From: Dapeng Mi To: Paolo Bonzini , Sean Christopherson Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Zide Chen , Xiaoyao Li , Dongli Zhang , Mingwei Zhang , Das Sandipan , Shukla Manali , Dapeng Mi , Dapeng Mi Subject: [PATCH 2/3] target/i386: Call KVM_CAP_PMU_CAPABILITY iotcl to enable/disable PMU Date: Mon, 24 Mar 2025 12:37:11 +0000 Message-Id: <20250324123712.34096-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> References: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.198.163.16; envelope-from=dapeng1.mi@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DATE_IN_FUTURE_03_06=3.027, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1742800200767116600 Content-Type: text/plain; charset="utf-8" After introducing mediated vPMU, mediated vPMU must be enabled by explicitly calling KVM_CAP_PMU_CAPABILITY to enable. Thus call KVM_CAP_PMU_CAPABILITY to enable/disable PMU base on user configuration. Suggested-by: Zhao Liu Signed-off-by: Dapeng Mi --- target/i386/kvm/kvm.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index f41e190fb8..d3e6984844 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2051,8 +2051,25 @@ full: abort(); } =20 +static bool pmu_cap_set =3D false; int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) { + KVMState *s =3D kvm_state; + X86CPU *x86_cpu =3D X86_CPU(cpu); + + if (!pmu_cap_set && kvm_check_extension(s, KVM_CAP_PMU_CAPABILITY)) { + int r =3D kvm_vm_enable_cap(s, KVM_CAP_PMU_CAPABILITY, 0, + KVM_PMU_CAP_DISABLE & !x86_cpu->enable_p= mu); + if (r < 0) { + error_report("kvm: Failed to %s pmu cap: %s", + x86_cpu->enable_pmu ? "enable" : "disable", + strerror(-r)); + return r; + } + + pmu_cap_set =3D true; + } + return 0; } =20 --=20 2.40.1 From nobody Tue Apr 1 08:43:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1742800197; cv=none; d=zohomail.com; s=zohoarc; b=Fyi9rJJJ90Dvn624Wm+WFs+mBQWSyqazJ/yI1eko/ao1p3ShC/mRNzEDEGGwhdGmgCWA0D+hHW/s9LfDS2sGM8BSaXwHSl/uVOj8dkkz1yj3hIsPSEn7PSIQb6SEReHoT5+7XbKxeYfU00qObNbEmYYV2OEOJTMxiAZWmv9vqMw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742800197; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Since Sapphire Rapids starts, VMX instrocude a new bit SAVE_IA32_PERF_GLOBAL_CTRL in VMCS VM-EXIT control field to manage if vmx can save guest PERF_GLOBAL_CTRL MSR. This patch enables this feature. Signed-off-by: Dapeng Mi --- target/i386/cpu.c | 12 ++++++++---- target/i386/cpu.h | 1 + 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1b64ceaaba..317ccc8b0a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1481,7 +1481,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "vmx-exit-save-efer", "vmx-exit-load-efer", "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, - NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", + NULL, "vmx-exit-load-pkrs", "vmx-exit-save-perf-global-ctrl", + "vmx-exit-secondary-ctls", }, .msr =3D { .index =3D MSR_IA32_VMX_TRUE_EXIT_CTLS, @@ -4212,7 +4213,8 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER, + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER | + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, .features[FEAT_VMX_MISC] =3D MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | MSR_VMX_MISC_VMWRITE_VMEXIT, @@ -4368,7 +4370,8 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER, + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER | + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, .features[FEAT_VMX_MISC] =3D MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | MSR_VMX_MISC_VMWRITE_VMEXIT, @@ -4511,7 +4514,8 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER, + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER | + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, .features[FEAT_VMX_MISC] =3D MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | MSR_VMX_MISC_VMWRITE_VMEXIT, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 76f24446a5..ad387e6ee7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1312,6 +1312,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 +#define VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL 0x40000000 #define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS 0x80000000 =20 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 --=20 2.40.1