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Iglesias" , Markus Armbruster , Akihiko Odaki , qemu-ppc@nongnu.org, Richard Henderson , Thomas Huth , David Gibson , Daniel Henrique Barboza , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Ilya Leoshkevich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , Pierrick Bouvier Subject: [PATCH v2 06/11] target/arm: convert 64 bit gdbstub to new helpers Date: Mon, 24 Mar 2025 10:21:37 +0000 Message-Id: <20250324102142.67022-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250324102142.67022-1-alex.bennee@linaro.org> References: <20250324102142.67022-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742811807575116600 For some of the helpers we need a temporary variable to copy from although we could add some helpers to return pointers into env in those cases if we wanted to. Signed-off-by: Alex Benn=C3=A9e --- v2 - use MO32/MO64 varients for reg sizes - use wrappers for 32/64 bit regs - do SVE Z registers in 128bit chunks --- target/arm/gdbstub64.c | 53 ++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 20 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 1a4dbec567..6ad10368e8 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -20,7 +20,7 @@ #include "qemu/log.h" #include "cpu.h" #include "internals.h" -#include "gdbstub/helpers.h" +#include "gdbstub/registers.h" #include "gdbstub/commands.h" #include "tcg/mte_helper.h" #if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX) @@ -32,18 +32,21 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteAr= ray *mem_buf, int n) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + MemOp mop =3D MO_TE; /* TE =3D LE for registers despite SCTLR.EE/E0E */ + uint32_t pstate; =20 if (n < 31) { /* Core integer register. */ - return gdb_get_reg64(mem_buf, env->xregs[n]); + return gdb_get_reg64_value(mop | MO_64, mem_buf, &env->xregs[n]); } switch (n) { case 31: - return gdb_get_reg64(mem_buf, env->xregs[31]); + return gdb_get_reg64_value(mop | MO_64, mem_buf, &env->xregs[31]); case 32: - return gdb_get_reg64(mem_buf, env->pc); + return gdb_get_reg64_value(mop | MO_64, mem_buf, &env->pc); case 33: - return gdb_get_reg32(mem_buf, pstate_read(env)); + pstate =3D pstate_read(env); + return gdb_get_reg32_value(mop | MO_32, mem_buf, &pstate); } /* Unknown register. */ return 0; @@ -82,23 +85,27 @@ int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *b= uf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + uint32_t fpr; =20 switch (reg) { case 0 ... 31: { /* 128 bit FP register - quads are in LE order */ uint64_t *q =3D aa64_vfp_qreg(env, reg); - return gdb_get_reg128(buf, q[1], q[0]); + return gdb_get_register_value(MO_TE | MO_128, buf, q); } case 32: /* FPSR */ - return gdb_get_reg32(buf, vfp_get_fpsr(env)); + fpr =3D vfp_get_fpsr(env); + break; case 33: /* FPCR */ - return gdb_get_reg32(buf, vfp_get_fpcr(env)); + fpr =3D vfp_get_fpcr(env); + break; default: return 0; } + return gdb_get_reg32_value(MO_TE | MO_32, buf, &fpr); } =20 int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg) @@ -132,30 +139,35 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray = *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + MemOp mop =3D MO_TE; /* TE =3D LE for registers despite SCTLR.EE/E0E */ + uint32_t fpr; =20 switch (reg) { /* The first 32 registers are the zregs */ case 0 ... 31: { int vq, len =3D 0; + ARMVectorReg *zreg =3D &env->vfp.zregs[reg]; + for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { - len +=3D gdb_get_reg128(buf, - env->vfp.zregs[reg].d[vq * 2 + 1], - env->vfp.zregs[reg].d[vq * 2]); + len +=3D gdb_get_register_value(mop | MO_128, buf, &zreg->d[vq= * 2]); } return len; } case 32: - return gdb_get_reg32(buf, vfp_get_fpsr(env)); + fpr =3D vfp_get_fpsr(env); + return gdb_get_reg32_value(mop | MO_32, buf, &fpr); case 33: - return gdb_get_reg32(buf, vfp_get_fpcr(env)); + fpr =3D vfp_get_fpcr(env); + return gdb_get_reg32_value(mop | MO_32, buf, &fpr); /* then 16 predicates and the ffr */ case 34 ... 50: { int preg =3D reg - 34; int vq, len =3D 0; for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { - len +=3D gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); + len +=3D gdb_get_reg64_value(mop | MO_64, buf, + &env->vfp.pregs[preg].p[vq / 4]); } return len; } @@ -165,8 +177,8 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *b= uf, int reg) * We report in Vector Granules (VG) which is 64bit in a Z reg * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ - int vq =3D sve_vqm1_for_el(env, arm_current_el(env)) + 1; - return gdb_get_reg64(buf, vq * 2); + uint64_t vq =3D (sve_vqm1_for_el(env, arm_current_el(env)) + 1) * = 2; + return gdb_get_reg64_value(mop | MO_64, buf, &vq); } default: /* gdbstub asked for something out our range */ @@ -248,10 +260,11 @@ int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArra= y *buf, int reg) bool is_data =3D !(reg & 1); bool is_high =3D reg & 2; ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); - ARMVAParameters param; + ARMVAParameters param =3D aa64_va_parameters(env, -is_high, mm= u_idx, + is_data, false); + uint64_t pauth_mask =3D pauth_ptr_mask(param); =20 - param =3D aa64_va_parameters(env, -is_high, mmu_idx, is_data, = false); - return gdb_get_reg64(buf, pauth_ptr_mask(param)); + return gdb_get_reg64_value(MO_TE | MO_64, buf, &pauth_mask); } default: return 0; @@ -399,7 +412,7 @@ int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArra= y *buf, int reg) =20 tcf0 =3D extract64(env->cp15.sctlr_el[1], 38, 2); =20 - return gdb_get_reg64(buf, tcf0); + return gdb_get_reg64_value(MO_TE | MO_64, buf, &tcf0); } =20 int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg) --=20 2.39.5