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Iglesias" , Markus Armbruster , Akihiko Odaki , qemu-ppc@nongnu.org, Richard Henderson , Thomas Huth , David Gibson , Daniel Henrique Barboza , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Ilya Leoshkevich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand , Pierrick Bouvier Subject: [PATCH v2 05/11] target/arm: convert 32 bit gdbstub to new helpers Date: Mon, 24 Mar 2025 10:21:36 +0000 Message-Id: <20250324102142.67022-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250324102142.67022-1-alex.bennee@linaro.org> References: <20250324102142.67022-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742811846130116600 For some of the helpers we need a temporary variable to copy from although we could add some helpers to return pointers into env in those cases if we wanted to. Reviewed-by: Pierrick Bouvier Signed-off-by: Alex Benn=C3=A9e --- v2 - use new wrappers - explicit MO_32 usage and reg32/64 helpers --- target/arm/gdbstub.c | 55 +++++++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 21 deletions(-) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 30068c2262..71d672ace5 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/gdbstub.h" -#include "gdbstub/helpers.h" +#include "gdbstub/registers.h" #include "gdbstub/commands.h" #include "system/tcg.h" #include "internals.h" @@ -33,12 +33,16 @@ typedef struct RegisterSysregFeatureParam { int n; } RegisterSysregFeatureParam; =20 -/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect - whatever the target description contains. Due to a historical mishap - the FPA registers appear in between core integer regs and the CPSR. - We hack round this by giving the FPA regs zero size when talking to a - newer gdb. */ - +/* + * Old gdb always expect FPA registers. Newer (xml-aware) gdb only + * expect whatever the target description contains. Due to a + * historical mishap the FPA registers appear in between core integer + * regs and the CPSR. We hack round this by giving the FPA regs zero + * size when talking to a newer gdb. + * + * While gdb cares about the memory endianess of the target all + * registers are passed in little-endian mode. + */ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -46,15 +50,17 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) =20 if (n < 16) { /* Core integer register. */ - return gdb_get_reg32(mem_buf, env->regs[n]); + return gdb_get_reg32_value(MO_TE | MO_32, mem_buf, &env->regs[n]); } if (n =3D=3D 25) { /* CPSR, or XPSR for M-profile */ + uint32_t reg; if (arm_feature(env, ARM_FEATURE_M)) { - return gdb_get_reg32(mem_buf, xpsr_read(env)); + reg =3D xpsr_read(env); } else { - return gdb_get_reg32(mem_buf, cpsr_read(env)); + reg =3D cpsr_read(env); } + return gdb_get_reg32_value(MO_TE | MO_32, mem_buf, ®); } /* Unknown register. */ return 0; @@ -115,19 +121,21 @@ static int vfp_gdb_get_reg(CPUState *cs, GByteArray *= buf, int reg) =20 /* VFP data registers are always little-endian. */ if (reg < nregs) { - return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); + return gdb_get_reg64_value(MO_TE | MO_64, buf, aa32_vfp_dreg(env, = reg)); } if (arm_feature(env, ARM_FEATURE_NEON)) { /* Aliases for Q regs. */ nregs +=3D 16; if (reg < nregs) { uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); - return gdb_get_reg128(buf, q[0], q[1]); + return gdb_get_reg64_value(MO_TE | MO_64, buf, q); } } switch (reg - nregs) { + uint32_t fpcr; case 0: - return gdb_get_reg32(buf, vfp_get_fpscr(env)); + fpcr =3D vfp_get_fpscr(env); + return gdb_get_reg32_value(MO_TE | MO_32, buf, &fpcr); } return 0; } @@ -166,9 +174,11 @@ static int vfp_gdb_get_sysreg(CPUState *cs, GByteArray= *buf, int reg) =20 switch (reg) { case 0: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); + return gdb_get_reg32_value(MO_TE | MO_32, buf, + &env->vfp.xregs[ARM_VFP_FPSID]); case 1: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); + return gdb_get_reg32_value(MO_TE | MO_32, buf, + &env->vfp.xregs[ARM_VFP_FPEXC]); } return 0; } @@ -196,7 +206,7 @@ static int mve_gdb_get_reg(CPUState *cs, GByteArray *bu= f, int reg) =20 switch (reg) { case 0: - return gdb_get_reg32(buf, env->v7m.vpr); + return gdb_get_reg32_value(MO_TE | MO_32, buf, &env->v7m.vpr); default: return 0; } @@ -236,9 +246,11 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArray= *buf, int reg) ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); if (ri) { if (cpreg_field_is_64bit(ri)) { - return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); + uint64_t cpreg =3D read_raw_cp_reg(env, ri); + return gdb_get_register_value(MO_TEUQ, buf, (uint8_t *) &cpreg= ); } else { - return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + uint32_t cpreg =3D (uint32_t) read_raw_cp_reg(env, ri); + return gdb_get_register_value(MO_TEUL, buf, (uint8_t *) &cpreg= ); } } return 0; @@ -375,12 +387,12 @@ static uint32_t *m_sysreg_ptr(CPUARMState *env, MProf= ileSysreg reg, bool sec) static int m_sysreg_get(CPUARMState *env, GByteArray *buf, MProfileSysreg reg, bool secure) { - uint32_t *ptr =3D m_sysreg_ptr(env, reg, secure); + uint8_t *ptr =3D (uint8_t *) m_sysreg_ptr(env, reg, secure); =20 if (ptr =3D=3D NULL) { return 0; } - return gdb_get_reg32(buf, *ptr); + return gdb_get_register_value(MO_TEUL, buf, ptr); } =20 static int arm_gdb_get_m_systemreg(CPUState *cs, GByteArray *buf, int reg) @@ -393,7 +405,8 @@ static int arm_gdb_get_m_systemreg(CPUState *cs, GByteA= rray *buf, int reg) * banked and non-banked bits. */ if (reg =3D=3D M_SYSREG_CONTROL) { - return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure= )); + uint32_t reg32 =3D arm_v7m_mrs_control(env, env->v7m.secure); + return gdb_get_register_value(MO_TEUL, buf, (uint8_t *) ®32); } return m_sysreg_get(env, buf, reg, env->v7m.secure); } --=20 2.39.5