From nobody Tue Feb 10 17:13:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751685; cv=none; d=zohomail.com; s=zohoarc; b=Gm8MmvJEMHG/Na+XfYZeUrgoZniSGHTNNWTW0C7SqUAoBqza98mWgt/bo531tUIKHYd+OSbNh/SwhN1b9ddCyZL7RlAg/hbcbr+JLv6oAVY1eeu3VAghk0CA/KWqlOUXa2PomTs6oNu6RTQCwP8hn+mCjgcj+e1cvEL/ZL/ypAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751685; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9/Tq8455Xl28q7efQW3SLtflxU6Hj8gr8oQW0BIa1vs=; b=X1y91bAGJnVMhjS/vCpGXW0XB8ytESTo7vj0s4pu6JuHE0a/L9nmRQIOtC/9JeH8/0vx2Cn7EQtumKzZY8lgKM1diJg0QvbJKcmh6TjuJBBUg/MMWpovrQCAjToM041J+Vok4w/QU1lUx5DBX+jjRoclYHsV6AKurYgNw/Ckd44= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751685389953.7811973411941; Sun, 23 Mar 2025 10:41:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGX-0005qP-VU; Sun, 23 Mar 2025 13:37:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGW-0005p8-54 for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:40 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGS-0002tI-OJ for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:39 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-227a8cdd241so13077305ad.3 for ; Sun, 23 Mar 2025 10:37:36 -0700 (PDT) Received: from stoup.. (174-21-74-48.tukw.qwest.net. [174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751455; x=1743356255; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9/Tq8455Xl28q7efQW3SLtflxU6Hj8gr8oQW0BIa1vs=; b=BuMIbuMuWTXUDEPn5Nrt/GFlLu1ZItNBMZPMMIF/lrmzZkdDVt3pCgiXsWzpHWsh4a 9rETYhXY8w4XIca6rj6wPsJeCgIRRP4pUdrKfkBwrnYPmJutKy6+bp0ppT2LaJiXVW2d 84giPDVE+kLQhh7LhwmoSZ+4N5Aq+NMUdFbpBzdFrOvOtVuQ/3Z+JM1X49tyqdnP60h/ iGf52sO5/NUR49S5R36TapGM8a8UvzDFBZvokKLNi1P3FSDQxckb+i6tDGrjlql0ovrc v+vPiPyG41m452TuHUoqsAFrSTvL2QRF9tolN8frT5un/vftvYrlddSkzV5Cq08h9Ujk PQvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751455; x=1743356255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9/Tq8455Xl28q7efQW3SLtflxU6Hj8gr8oQW0BIa1vs=; b=Csk3Ep55pVvmmtMtGEl8VYTKwiD8PSWDonXUIKDWDtz06ttcHgZM0KYE+vXGUcbkWs AoqLwpif1dAJTucE9I5hzBJ3VNFquD9/xAOsoUwEmZhhD74dikTxtjlyAQw+3SzkZtq/ 79Q61M9VB/JgwQ06lcNQ0+zpWLcQFiynD8rBlhUJOk7iq4JHpCjHbfwLwdivB1cmLlly o70f15yNuB2ZRCbMJhQeORGhvTPt91nqbNX30axHvDFSHUSObEpDbkagUiuuxjnx/fuM knOToYLFhybA02Y6jHAj2pv2UJBr/W+l1AvSlnci3Nx2lY8HGzEDqJlJjZFPYwBWgQlV KZ/Q== X-Gm-Message-State: AOJu0YyamtFzS0IPYjzMu/bLcNuxRodmFxxC0iyUGWzRwTyuaW+nwpNc +QJs1kXuSi62C+zzD8q1sA7Kcsys0gmjP3aNS+NuiV3TTHhHtB6bBdkI+0qtevGSAp+X/i/Eib9 X X-Gm-Gg: ASbGnctPpRWq34olvh2+bCUOxUkmQVXGhRkrtBVdUHhCK2dym6o2YPiKpES8mupTD1u sdO7OBDR4/nv1w5IL9pWP2m4pasR4EezorFCZ2a3tlP6WiLIv4temRiV8MgiH7sFH0PVDrbsz42 GIkcrtQsGrph7y0Y0RSrw+TkCmnXqGC+6NiNpzBfdzQPVgaGBwzq/y7oMtqL7iod56Ye8t4uG+c Mxdgg9qAOu6ympnH+IQUC8mD4oSVse68P1ZjpbeOEC2jz8oD/k0HLnGW2GVrJB4ViReGI9exBEO PHNBuFEswdynT4x4cMLLToyMr7Uq8mGd3lWy2qb6IRLoVX8NcYJyQSl59u33inLmlp1/YnJNd2p F X-Google-Smtp-Source: AGHT+IGKvT8qm0wChFsqWsxeKZ+j+oxfopqxoeEguwbwTSqH4umTXD8XEjAMzuxazBVvQqgyJrHFiw== X-Received: by 2002:a17:902:e54d:b0:21f:1549:a55a with SMTP id d9443c01a7336-22780c50856mr151984365ad.1.1742751455161; Sun, 23 Mar 2025 10:37:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 05/17] target/avr: Move cpu register accesses into system memory Date: Sun, 23 Mar 2025 10:37:17 -0700 Message-ID: <20250323173730.3213964-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751685916116600 Content-Type: text/plain; charset="utf-8" Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into the cpu registers with normal address space accesses. We no longer need to trap accesses to the first page within avr_cpu_tlb_fill but can wait until a write occurs. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 7 ++ target/avr/helper.h | 3 - target/avr/cpu.c | 16 +++ target/avr/helper.c | 239 +++++++++++++++++------------------------ target/avr/translate.c | 42 ++++---- 5 files changed, 146 insertions(+), 161 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 84a8f5cc8c..be27b0152b 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memory.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" @@ -142,6 +143,9 @@ struct ArchCPU { =20 CPUAVRState env; =20 + MemoryRegion cpu_reg1; + MemoryRegion cpu_reg2; + /* Initial value of stack pointer */ uint32_t init_sp; }; @@ -242,6 +246,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +extern const MemoryRegionOps avr_cpu_reg1; +extern const MemoryRegionOps avr_cpu_reg2; + #include "exec/cpu-all.h" =20 #endif /* QEMU_AVR_CPU_H */ diff --git a/target/avr/helper.h b/target/avr/helper.h index 4d02e648fa..e8d13e925f 100644 --- a/target/avr/helper.h +++ b/target/avr/helper.h @@ -23,7 +23,4 @@ DEF_HELPER_1(debug, noreturn, env) DEF_HELPER_1(break, noreturn, env) DEF_HELPER_1(sleep, noreturn, env) DEF_HELPER_1(unsupported, noreturn, env) -DEF_HELPER_3(outb, void, env, i32, i32) -DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(fullwr, void, env, i32, i32) -DEF_HELPER_2(fullrd, tl, env, i32) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 834c7082aa..0b14b36c17 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/exec-all.h" #include "exec/translation-block.h" +#include "exec/address-spaces.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -110,6 +111,8 @@ static void avr_cpu_disas_set_info(CPUState *cpu, disas= semble_info *info) static void avr_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + CPUAVRState *env =3D cpu_env(cs); + AVRCPU *cpu =3D env_archcpu(env); AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 @@ -122,6 +125,19 @@ static void avr_cpu_realizefn(DeviceState *dev, Error = **errp) cpu_reset(cs); =20 mcc->parent_realize(dev, errp); + + /* + * Two blocks in the low data space loop back into cpu registers. + */ + memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, + "avr-cpu-reg1", 32); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA, &cpu->cpu_reg1); + + memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, + "avr-cpu-reg2", 8); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + 0x58, &cpu->cpu_reg2); } =20 static void avr_cpu_set_int(void *opaque, int irq, int level) diff --git a/target/avr/helper.c b/target/avr/helper.c index e5bf16c6b7..df7e2109d4 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -108,7 +108,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - int prot, page_size =3D TARGET_PAGE_SIZE; + int prot; uint32_t paddr; =20 address &=3D TARGET_PAGE_MASK; @@ -133,23 +133,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, /* Access to memory. */ paddr =3D OFFSET_DATA + address; prot =3D PAGE_READ | PAGE_WRITE; - if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* - * Access to CPU registers, exit and rebuilt this TB to use - * full access in case it touches specially handled registers - * like SREG or SP. For probing, set page_size =3D 1, in order - * to force tlb_fill to be called for the next access. - */ - if (probe) { - page_size =3D 1; - } else { - cpu_env(cs)->fullacc =3D 1; - cpu_loop_exit_restore(cs, retaddr); - } - } } =20 - tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } =20 @@ -203,134 +189,78 @@ void helper_wdr(CPUAVRState *env) } =20 /* - * This function implements IN instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is read and returned - * b. otherwise io address is translated to mem address and physical memo= ry - * is read. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation - * + * The first 32 bytes of the data space are mapped to the cpu regs. + * We cannot write these from normal store operations because TCG + * does not expect global temps to be modified -- a global may be + * live in a host cpu register across the store. We can however + * read these, as TCG does make sure the global temps are saved + * in case the load operation traps. */ -target_ulong helper_inb(CPUAVRState *env, uint32_t port) + +static uint64_t avr_cpu_reg1_read(void *opaque, hwaddr addr, unsigned size) { - target_ulong data =3D 0; + CPUAVRState *env =3D opaque; =20 - switch (port) { - case 0x38: /* RAMPD */ - data =3D 0xff & (env->rampD >> 16); - break; - case 0x39: /* RAMPX */ - data =3D 0xff & (env->rampX >> 16); - break; - case 0x3a: /* RAMPY */ - data =3D 0xff & (env->rampY >> 16); - break; - case 0x3b: /* RAMPZ */ - data =3D 0xff & (env->rampZ >> 16); - break; - case 0x3c: /* EIND */ - data =3D 0xff & (env->eind >> 16); - break; - case 0x3d: /* SPL */ - data =3D env->sp & 0x00ff; - break; - case 0x3e: /* SPH */ - data =3D env->sp >> 8; - break; - case 0x3f: /* SREG */ - data =3D cpu_get_sreg(env); - break; - default: - /* not a special register, pass to normal memory access */ - data =3D address_space_ldub(&address_space_memory, - OFFSET_IO_REGISTERS + port, - MEMTXATTRS_UNSPECIFIED, NULL); - } - - return data; + assert(addr < 32); + return env->r[addr]; } =20 /* - * This function implements OUT instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is written into the re= gister - * b. otherwise io address is translated to mem address and physical mem= ory - * is written. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementati= on - * + * The range 0x58-0x5f of the data space are mapped to cpu regs. + * As above, we cannot write these from normal store operations. */ -void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) -{ - data &=3D 0x000000ff; =20 - switch (port) { - case 0x38: /* RAMPD */ - if (avr_feature(env, AVR_FEATURE_RAMPD)) { - env->rampD =3D (data & 0xff) << 16; - } - break; - case 0x39: /* RAMPX */ - if (avr_feature(env, AVR_FEATURE_RAMPX)) { - env->rampX =3D (data & 0xff) << 16; - } - break; - case 0x3a: /* RAMPY */ - if (avr_feature(env, AVR_FEATURE_RAMPY)) { - env->rampY =3D (data & 0xff) << 16; - } - break; - case 0x3b: /* RAMPZ */ - if (avr_feature(env, AVR_FEATURE_RAMPZ)) { - env->rampZ =3D (data & 0xff) << 16; - } - break; - case 0x3c: /* EIDN */ - env->eind =3D (data & 0xff) << 16; - break; - case 0x3d: /* SPL */ - env->sp =3D (env->sp & 0xff00) | (data); - break; - case 0x3e: /* SPH */ - if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { - env->sp =3D (env->sp & 0x00ff) | (data << 8); - } - break; - case 0x3f: /* SREG */ - cpu_set_sreg(env, data); - break; - default: - /* not a special register, pass to normal memory access */ - address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + por= t, - data, MEMTXATTRS_UNSPECIFIED, NULL); +static uint64_t avr_cpu_reg2_read(void *opaque, hwaddr addr, unsigned size) +{ + CPUAVRState *env =3D opaque; + + switch (addr) { + case 0: /* RAMPD */ + return 0xff & (env->rampD >> 16); + case 1: /* RAMPX */ + return 0xff & (env->rampX >> 16); + case 2: /* RAMPY */ + return 0xff & (env->rampY >> 16); + case 3: /* RAMPZ */ + return 0xff & (env->rampZ >> 16); + case 4: /* EIND */ + return 0xff & (env->eind >> 16); + case 5: /* SPL */ + return env->sp & 0x00ff; + case 6: /* SPH */ + return 0xff & (env->sp >> 8); + case 7: /* SREG */ + return cpu_get_sreg(env); } + g_assert_not_reached(); } =20 -/* - * this function implements LD instruction when there is a possibility to= read - * from a CPU register - */ -target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) +static void avr_cpu_trap_write(void *opaque, hwaddr addr, + uint64_t data64, unsigned size) { - uint8_t data; + CPUAVRState *env =3D opaque; + CPUState *cs =3D env_cpu(env); =20 - env->fullacc =3D false; - - if (addr < NUMBER_OF_CPU_REGISTERS) { - /* CPU registers */ - data =3D env->r[addr]; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - data =3D helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS); - } else { - /* memory */ - data =3D address_space_ldub(&address_space_memory, OFFSET_DATA + a= ddr, - MEMTXATTRS_UNSPECIFIED, NULL); - } - return data; + env->fullacc =3D true; + cpu_loop_exit_restore(cs, cs->mem_io_pc); } =20 +const MemoryRegionOps avr_cpu_reg1 =3D { + .read =3D avr_cpu_reg1_read, + .write =3D avr_cpu_trap_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + +const MemoryRegionOps avr_cpu_reg2 =3D { + .read =3D avr_cpu_reg2_read, + .write =3D avr_cpu_trap_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + /* * this function implements ST instruction when there is a possibility to= write * into a CPU register @@ -339,19 +269,50 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, u= int32_t addr) { env->fullacc =3D false; =20 - /* Following logic assumes this: */ - assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_DATA + - NUMBER_OF_CPU_REGISTERS); - - if (addr < NUMBER_OF_CPU_REGISTERS) { + switch (addr) { + case 0 ... 31: /* CPU registers */ env->r[addr] =3D data; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data); - } else { - /* memory */ + break; + + case 0x58: /* RAMPD */ + if (avr_feature(env, AVR_FEATURE_RAMPD)) { + env->rampD =3D data << 16; + } + break; + case 0x59: /* RAMPX */ + if (avr_feature(env, AVR_FEATURE_RAMPX)) { + env->rampX =3D data << 16; + } + break; + case 0x5a: /* RAMPY */ + if (avr_feature(env, AVR_FEATURE_RAMPY)) { + env->rampY =3D data << 16; + } + break; + case 0x5b: /* RAMPZ */ + if (avr_feature(env, AVR_FEATURE_RAMPZ)) { + env->rampZ =3D data << 16; + } + break; + case 0x5c: /* EIDN */ + env->eind =3D data << 16; + break; + case 0x5d: /* SPL */ + env->sp =3D (env->sp & 0xff00) | data; + break; + case 0x5e: /* SPH */ + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { + env->sp =3D (env->sp & 0x00ff) | (data << 8); + } + break; + case 0x5f: /* SREG */ + cpu_set_sreg(env, data); + break; + + default: address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, MEMTXATTRS_UNSPECIFIED, NULL); + break; } } diff --git a/target/avr/translate.c b/target/avr/translate.c index e7f8ced9b3..0490936cd5 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -194,6 +194,9 @@ static bool avr_have_feature(DisasContext *ctx, int fea= ture) static bool decode_insn(DisasContext *ctx, uint16_t insn); #include "decode-insn.c.inc" =20 +static void gen_inb(DisasContext *ctx, TCGv data, int port); +static void gen_outb(DisasContext *ctx, TCGv data, int port); + /* * Arithmetic Instructions */ @@ -1293,9 +1296,8 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_EQ; ctx->skip_var0 =3D data; @@ -1311,9 +1313,8 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_NE; ctx->skip_var0 =3D data; @@ -1502,11 +1503,18 @@ static void gen_data_store(DisasContext *ctx, TCGv = data, TCGv addr) =20 static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { - if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { - gen_helper_fullrd(data, tcg_env, addr); - } else { - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); - } + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); +} + +static void gen_inb(DisasContext *ctx, TCGv data, int port) +{ + gen_data_load(ctx, data, tcg_constant_i32(port + NUMBER_OF_CPU_REGISTE= RS)); +} + +static void gen_outb(DisasContext *ctx, TCGv data, int port) +{ + gen_helper_fullwr(tcg_env, data, + tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS)); } =20 /* @@ -2126,9 +2134,8 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) static bool trans_IN(DisasContext *ctx, arg_IN *a) { TCGv Rd =3D cpu_r[a->rd]; - TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_inb(Rd, tcg_env, port); + gen_inb(ctx, Rd, a->imm); return true; } =20 @@ -2139,9 +2146,8 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) static bool trans_OUT(DisasContext *ctx, arg_OUT *a) { TCGv Rd =3D cpu_r[a->rd]; - TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_outb(tcg_env, port, Rd); + gen_outb(ctx, Rd, a->imm); return true; } =20 @@ -2407,11 +2413,10 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP = *a) static bool trans_SBI(DisasContext *ctx, arg_SBI *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_ori_tl(data, data, 1 << a->bit); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } =20 @@ -2422,11 +2427,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) static bool trans_CBI(DisasContext *ctx, arg_CBI *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } =20 --=20 2.43.0