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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mrolnik@gmail.com,
philmd@linaro.org,
pierrick.bouvier@linaro.org
Subject: [PATCH 10/17] target/avr: Update cpu_sp after push and pop
Date: Sun, 23 Mar 2025 10:37:22 -0700
Message-ID: <20250323173730.3213964-11-richard.henderson@linaro.org>
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Not that AVR has memory paging traps, but it's better
form to allow the memory operation to finish before
updating the cpu register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
target/avr/translate.c | 32 +++++++++++++++-----------------
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 6bb4154dff..3446007be1 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -967,40 +967,38 @@ static void gen_push_ret(DisasContext *ctx, int ret)
} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
TCGv t0 =3D tcg_constant_i32(ret & 0x00ffff);
=20
- tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
- gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_BEUW);
- tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+ gen_data_store_raw(ctx, t0, cpu_sp, -1, MO_BEUW);
+ tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
TCGv lo =3D tcg_constant_i32(ret & 0x0000ff);
TCGv hi =3D tcg_constant_i32((ret & 0xffff00) >> 8);
=20
gen_data_store_raw(ctx, lo, cpu_sp, 0, MO_UB);
- tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
- gen_data_store_raw(ctx, hi, cpu_sp, 0, MO_BEUW);
- tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+ gen_data_store_raw(ctx, hi, cpu_sp, -2, MO_BEUW);
+ tcg_gen_subi_tl(cpu_sp, cpu_sp, 3);
+ } else {
+ g_assert_not_reached();
}
}
=20
static void gen_pop_ret(DisasContext *ctx, TCGv ret)
{
if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
+ gen_data_load_raw(ctx, ret, cpu_sp, 1, MO_UB);
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
- gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_UB);
} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
- tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
- gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_BEUW);
- tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+ gen_data_load_raw(ctx, ret, cpu_sp, 1, MO_BEUW);
+ tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
- TCGv lo =3D tcg_temp_new_i32();
TCGv hi =3D tcg_temp_new_i32();
=20
- tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
- gen_data_load_raw(ctx, hi, cpu_sp, 0, MO_BEUW);
+ gen_data_load_raw(ctx, hi, cpu_sp, 1, MO_BEUW);
+ gen_data_load_raw(ctx, ret, cpu_sp, 3, MO_UB);
+ tcg_gen_addi_tl(cpu_sp, cpu_sp, 3);
=20
- tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
- gen_data_load_raw(ctx, lo, cpu_sp, 0, MO_UB);
-
- tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
+ tcg_gen_deposit_tl(ret, ret, hi, 8, 16);
+ } else {
+ g_assert_not_reached();
}
}
=20
--=20
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