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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751452; x=1743356252; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0CsTLV8c98Si7k0XcXe65xYgFmk/mGZL9wnBem+k0DA=; b=gRRCwdE4H4oCfNJw0zNmRbA/DKwcznWTBGXwypiI633iApx1o9BAn1E0AQYp3Y/5G0 LM1EqClvE8YZFoIutbrwSS+xi/YNtztM2hRfkW3XNN5gjD3y0gCkZER9urLoOplvylXe a+MhgrV4gJ1hKkE5lvXt2Zj5dsCfZSSCXXNwtNe0X1H/vekUK9i3EAO9VPg9HesJ4XQY 4ArjxEiA3XPpVwVC+5j71T4GwC+EtsSmasO/zpVdzzFmjUsxpeN0sA3h7Aoyam9KvDV+ 7CoRzhezTrAybe/QWy3ajW+f0mJZlOUqkwJA/pcsYzJNrmqJmW1+EYXhZZ3Ql6KHyA9w aa7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751452; x=1743356252; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0CsTLV8c98Si7k0XcXe65xYgFmk/mGZL9wnBem+k0DA=; b=LFS958+q6jXqa0eYR80sCselJa2ilzy7GqcSdT+fZIbtyw03LglFVSRb3bftRIvfIn weyLPONDiQ78BlOfeM7sCP6KhchZG1Txt35mnfG5eRs914qUlDiCeBJtSCJBE5N+3E3o Zywfl5Gm3V6te5xI9IZBuf7a25rr01vXdts1lvYz/5t9C5w4xgSrEzwiOG1Ye11sJW1G 2YnZGuakKWswn1rchzO5VDbCiF88qROgRZDtNCdna47gadppARxXD++PvHIH4yH0oy82 WxUknSZdCyoOsTa7IerDGxRtJapPurWdswMn24QMegrVjzoyXSTVOuhLi3oQiXxlbobA 1Dlg== X-Gm-Message-State: AOJu0YyN00YLCOJkR+2cYFhKikolUfaBuDz/aGvdlerGW2zqbCpK0glZ xZboTuXH4IWEwSHHLYSMRhLp/2ac8cacnVV22agxrX1npTBoSfTw2qnh5qgpVAix3Mgl+KajJB7 N X-Gm-Gg: ASbGncs5XkSRwPQpw6owW8y5dLvb5MM2UcaNze/hJFxZZnakrT6M3959MboY+7SFVy7 LT+b0gaAijNB2RvcE7HcWnOidw0BqNPQ5P6H11868j0CS8XTPWrM1vWcC8gEnyPMSS2tQGaDRvB VunoB8r9VTlwiIJ5Ybd2FmVWtQYdLw9FWW+E5SSGHlMPeveN9R2iCGrugeBr7rLJEjorH90h4+6 iM6DZKgZGOpPHggFWfuCEfmEjuKJj1mlHSYEQaLdAxkYMt1ef/Cu9Wsy2EXUR/R2HyULA8YbKSz QI05mR06DHiVS7L1o5h6nY9iYL163Fe7WZrPgZrHgReNg3VwupGNfM502LYOCjigoI3J9m5n079 p X-Google-Smtp-Source: AGHT+IG2X95hsRawzwhbLQ3RGAlspim9GUHMC/QvXyscJbZmJqJzclYSgQ/xg2p+o2hn0Dh49W20wg== X-Received: by 2002:a17:902:c949:b0:21f:2e:4e4e with SMTP id d9443c01a7336-2278067c0a6mr150255595ad.5.1742751451834; Sun, 23 Mar 2025 10:37:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 01/17] hw/core/cpu: Use size_t for memory_rw_debug len argument Date: Sun, 23 Mar 2025 10:37:13 -0700 Message-ID: <20250323173730.3213964-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751584636116600 Content-Type: text/plain; charset="utf-8" Match the prototype of cpu_memory_rw_debug(). Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/core/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/sparc/mmu_helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5d11d26556..abd8764e83 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -154,7 +154,7 @@ struct CPUClass { =20 int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, - uint8_t *buf, int len, bool is_write); + uint8_t *buf, size_t len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); int64_t (*get_arch_id)(CPUState *cpu); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 462bcb6c0e..68f8c21e7c 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -604,7 +604,7 @@ void dump_mmu(CPUSPARCState *env); =20 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, - uint8_t *buf, int len, bool is_write); + uint8_t *buf, size_t len, bool is_write); #endif =20 /* translate.c */ diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 7548d01777..3821cd91ec 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -389,7 +389,7 @@ void dump_mmu(CPUSPARCState *env) * that the sparc ABI is followed. */ int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address, - uint8_t *buf, int len, bool is_write) + uint8_t *buf, size_t len, bool is_write) { CPUSPARCState *env =3D cpu_env(cs); target_ulong addr =3D address; --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751685; cv=none; d=zohomail.com; s=zohoarc; b=Tc22x7hh7qeTuUyjvuF8d0+DDtXc39GX832xqJsPRsM8nL8zP4zzJSzKjjNtErThM0eD7xl03iR4S8Cle04o4MWlfg+mUckbmrnNIi31tvOW1xrXjmWi7sX4hI/MHT95zdYjE7YIfSsSxvZAZ3CwZu5gdBnEY2TBDhNf+lme1io= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751685; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=n93sFLgifoxtvFypKbIjFGlyxMVTs87sLBcre3AkoOA=; b=E11DxCKRkOE/gl4osS6oqYsJhrE0/YZKybl95nSIOhT+KU0pgKTrsSkjp7JwbDuhu4cFy9gMh2Vw6F6f4rITXFmC25vyN09JZNGWHSVkN/vWiVE2IxqXzwHjEStEWkDxwOSjC4Pxa21gyPZB+jsoD3WyvcNBzmd0iCLaYhDasSI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751685325680.9253991399114; Sun, 23 Mar 2025 10:41:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGX-0005q2-L7; Sun, 23 Mar 2025 13:37:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGU-0005ny-DU for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:38 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGQ-0002sf-11 for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:38 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2240b4de12bso49156715ad.2 for ; Sun, 23 Mar 2025 10:37:33 -0700 (PDT) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751453; x=1743356253; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n93sFLgifoxtvFypKbIjFGlyxMVTs87sLBcre3AkoOA=; b=QFKBLjBA1GmjGyL/FyySb+Ovt4VGhMGaeU/ugLvwOsydq+W1T7jTdbci9Ro4pxZCm0 TFOV3AIPiJrNjwdGx260fPVKVy31xv5bG+69vsXlCGJai0Jt9/Fd13JB7QEI3wb03qs8 tOgmSCL3cAvOYukFz2YJmFGK/a8T96hLWwjHOgvDzEaM6OFA/vPmEOZTVasY5h6q/jaQ L8mBfIH2qP0Ol3fK58LLrtEtckddQXOetG2VnFI3re77PPp8xjz1u2Fun6p4kDZq7Hou Mxy8agNE51jSo07zIQSBv05HyRDyhOW4otHYnsYilmcIO73wH+poS3HkPcSAjfLIdf87 TPVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751453; x=1743356253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n93sFLgifoxtvFypKbIjFGlyxMVTs87sLBcre3AkoOA=; b=LQkPSyxv0xpELFSHNo6c+XFuUYa1lzqFomdndpzUUMDqn/L0UPz4bfOPv/jh0MmOjZ gOM+ERjhWvt7AadOrxsDhdNb593sow/wXwf4C+E0MwtqiJqOPnD4ZZzy3YHY1f4g35tt Zajp11RlyXWnPMHP6XerjSLB4HFRG234PETkxTZEpbXim5C9xW9LGFLgoZ/mbdEMl851 AypABIu2PSs6i9J7X1HuzWylJEvXhICSBnpEHYzpg3KF8/6vESWDYH67bL2y7ahAPj1f JCVkchULE3h/e0AP4DXPbNIYvQ7eUCwiT/ZdKbgr6cZ/5zvA2xbqdVnBzJhX2cLcCe2t 8dxg== X-Gm-Message-State: AOJu0YwKTpkxdzR3jai4C1VxZIR1R2sMnJtjkvknZlVeixWuKDGHGJk8 NTWUU29lY2oNOT47jL0mxYKJAM6P0q4jjqmQEYn74IFZnqSg4z2hGVoBJKKLzPonsl5S8/0fROe / X-Gm-Gg: ASbGncsd8JBMnCTKhVQ1AXuA6A461MyVLxo9+Xy5L4fuoAr3EGXPlwa0FUTmU+0RC1T PYRlDmZHWw1Kn5oXkByAjzyrJ1xtNxK9JD0cZEgFoNPoHmHu1Ax3HK3a32p4YgrZKc/kuz7SQ7B wQ3T4bjb+zgyWFGAekY1MoJYDf18Ezp6DrXkGfwxElYAukv0nKEIBdlSjXko1BqxaesBioZYeqC riXMAFcGxaQpPHFbcYPZhBbbMhro/NRqpyzBWRTQxdaxtT/GLt5PaCTTAw9/Yo5Rut5oU1frPb3 WeQSEAiTs2pWjuR2wiJixBJ9moUjgr54ivzkRiXPRf3uJGVJJZYAaGA3mlf+lbtrTkbpV2fmaki Z X-Google-Smtp-Source: AGHT+IFeL7hfN2mvzRSrDxwvc2HFDLEUkB74qmg6B7Zgf/1gvOLDdKv22Gb/Z3AHuIG15AxxS16TKw== X-Received: by 2002:a17:902:e84f:b0:223:f639:69df with SMTP id d9443c01a7336-22780e15275mr165077675ad.41.1742751452680; Sun, 23 Mar 2025 10:37:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org, qemu-stable@nongnu.org Subject: [PATCH 02/17] target/avr: Fix buffer read in avr_print_insn Date: Sun, 23 Mar 2025 10:37:14 -0700 Message-ID: <20250323173730.3213964-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751685776116600 Content-Type: text/plain; charset="utf-8" Do not unconditionally attempt to read 4 bytes, as there may only be 2 bytes remaining in the translator cache. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/disas.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/target/avr/disas.c b/target/avr/disas.c index b7689e8d7c..d341030174 100644 --- a/target/avr/disas.c +++ b/target/avr/disas.c @@ -68,28 +68,35 @@ static bool decode_insn(DisasContext *ctx, uint16_t ins= n); =20 int avr_print_insn(bfd_vma addr, disassemble_info *info) { - DisasContext ctx; + DisasContext ctx =3D { info }; DisasContext *pctx =3D &ctx; bfd_byte buffer[4]; uint16_t insn; int status; =20 - ctx.info =3D info; - - status =3D info->read_memory_func(addr, buffer, 4, info); + status =3D info->read_memory_func(addr, buffer, 2, info); if (status !=3D 0) { info->memory_error_func(status, addr, info); return -1; } insn =3D bfd_getl16(buffer); - ctx.next_word =3D bfd_getl16(buffer + 2); - ctx.next_word_used =3D false; + + status =3D info->read_memory_func(addr + 2, buffer + 2, 2, info); + if (status =3D=3D 0) { + ctx.next_word =3D bfd_getl16(buffer + 2); + } =20 if (!decode_insn(&ctx, insn)) { output(".db", "0x%02x, 0x%02x", buffer[0], buffer[1]); } =20 - return ctx.next_word_used ? 4 : 2; + if (!ctx.next_word_used) { + return 2; + } else if (status =3D=3D 0) { + return 4; + } + info->memory_error_func(status, addr + 2, info); + return -1; } =20 =20 --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751691; cv=none; d=zohomail.com; s=zohoarc; b=c8EnuKS1+FXz0bvSLjYZ4leVuR2hiN++VaGdHnLDPzrzc0T6RUg5afpI/EVuAdedVi1MLf+mAe1YoBEESoeat/dVMz6Amz93Ijk9jQAKhNdRJWeER8QWOEEno/ECq0ZCEzpwismAsFo714M+U12Mop1T+FK5zhLYrbg5keIEUzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751691; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YGgDZgK8X2BSYVWSdj2GCRC9iMdojOu2NC7i0DOuuAA=; b=kBJJXLWbRxiRIp5PuI/K+nHaDep5upwoaIn9ZPQr6GqL8rClAlZOUZ8Lyv43yi5sMYJO8bqZfB5ahvE94NEGOS9So46hd4bjfN4nb/RfkOy9gQlipwbV/5GO1CjTbuoML66h0N9rCs/YQ8NXi2PayHohugHTPc/Bhwit/mq6QKQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751691843183.36004214649688; Sun, 23 Mar 2025 10:41:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGV-0005oM-J1; Sun, 23 Mar 2025 13:37:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGT-0005nW-T7 for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:37 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGQ-0002ss-RT for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:37 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-22435603572so61794335ad.1 for ; Sun, 23 Mar 2025 10:37:34 -0700 (PDT) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751453; x=1743356253; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YGgDZgK8X2BSYVWSdj2GCRC9iMdojOu2NC7i0DOuuAA=; b=vNYqetvcBXQCyIHKeUTj2NgIlsMrirj0MqcigE1BpeCq83c8Jk5p/fvPQ8giiPxcmc wadAC+xHQUH57/CRmqhAKgnlR3MwlbQ/VLq29Gaqa1sy6+7Z79P7TwlO2Dqqha2aH+7g L6K2W5FcN46E4MJgKolh5UKQWVx0/m9jVwzch+XFjkbCIRHc+9J83zTG3Dba++lGt1aJ kw08o1IulAMxZLnqzGoBlcsFAxj8RLOQUmLZlDClAKoxHidFG06lQNvntXm6b2FDO/Bw To5rQ90F/Ry5sJGXXsB8tT7InX+Mh9yXdt+p01aQiR2Ng8zT5f0BwX6urvjqrs2dojaB oEFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751453; x=1743356253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YGgDZgK8X2BSYVWSdj2GCRC9iMdojOu2NC7i0DOuuAA=; b=V5zRGT0xohPnUYEB2/QPzvTH+JfxI/O8+wTdbb16Djh0Sa3Kayh1oAleioK52AQY0h cXvwFkPHmk0MNn9bW1yYFTOSl0266z/Idxs7rpbG27FWwdFCgKqjEaVt2PD5w0vo4dTc AA8jIzsVsSaGTQxHAel/UccsF7ZHhK9xUioASrTBYaj7+ZYbazaYPkmPDfPjTpnMR1Rd X7Cy8EwkpzN7YGcMNpXymUJM153+PaNkQHloTpP8MniwZ2QWsenB2zhuj1AijntCQ9xX d9hPUyiRtFSGuoydY3zD5hy4CzP/KfcgjesHYZe1s3Nz2VNwd6zYfJDVbsrJBW2KlQRo 56eg== X-Gm-Message-State: AOJu0Yyodn/awgAS+GDf6p/8wxoH6rhyhsbbLnxQyxEZpZI7R/80+sCi j+jO1hr6XKmbJ4/K/QUJrelPdlof3gNyYjU/nwxlQwd9h0wZVv01R8jNSC9xPcPIVFmuCWoGzfr 6 X-Gm-Gg: ASbGnctC4MrzaD1rJmB7LjbzjIhEXwzohY2bQGUsOFUd0TNoovennQYgHsDS11QfYOP engue0zO1RyeYYPWE5qVOGBMcmS3wmzcJWON9dVv+Q4NfgSYALTUMobicwJfmrcj58JXD5rX8hJ Bp1K5nlwqSOJs1Mjc11TOI2G9cejeiu/H+zh35Vl3NQVkbwg29roMGqXOpN9EMQOlDCsZSNWGgF /nfm4mjGOvVIjL9BBKi4XTJT83AvOeQqj/0sqAcJJH5/JKh8a7jhFPLGWHWzEtc0jiX9WcNfYb/ Xi/jbg2pgYgoIHOC7MHX4f1nQJ9N3/f3hcgEV7352RRwLkzMiY8sf+7WjH0OtbzxQT6XfsvRmus tEejVN9VAFa0= X-Google-Smtp-Source: AGHT+IHHjB6B0aSiinZE2kTfMdMwJ2ciLfmNsLKY4AnB8g+LRZw0g8rAnpEja84qwoVEiW8UNlbmwA== X-Received: by 2002:a17:902:e846:b0:223:5c33:56a2 with SMTP id d9443c01a7336-22780da6237mr185737895ad.28.1742751453497; Sun, 23 Mar 2025 10:37:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org, qemu-stable@nongnu.org Subject: [PATCH 03/17] target/avr: Improve decode of LDS, STS Date: Sun, 23 Mar 2025 10:37:15 -0700 Message-ID: <20250323173730.3213964-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751693669116600 Content-Type: text/plain; charset="utf-8" The comment about not being able to define a field with zero bits is out of date since 94597b6146f3 ("decodetree: Allow !function with no input bits"). This fixes the missing load of imm in the disassembler. Cc: qemu-stable@nongnu.org Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling via option '= -d in_asm'") Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/translate.c | 2 -- target/avr/insn.decode | 7 ++----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 4ab71d8138..e7f8ced9b3 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1578,7 +1578,6 @@ static bool trans_LDS(DisasContext *ctx, arg_LDS *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D tcg_temp_new_i32(); TCGv H =3D cpu_rampD; - a->imm =3D next_word(ctx); =20 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */ tcg_gen_shli_tl(addr, addr, 16); @@ -1783,7 +1782,6 @@ static bool trans_STS(DisasContext *ctx, arg_STS *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D tcg_temp_new_i32(); TCGv H =3D cpu_rampD; - a->imm =3D next_word(ctx); =20 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */ tcg_gen_shli_tl(addr, addr, 16); diff --git a/target/avr/insn.decode b/target/avr/insn.decode index 482c23ad0c..cc302249db 100644 --- a/target/avr/insn.decode +++ b/target/avr/insn.decode @@ -118,11 +118,8 @@ BRBC 1111 01 ....... ... @op_bit_imm @io_rd_imm .... . .. ..... .... &rd_imm rd=3D%rd imm=3D%io= _imm @ldst_d .. . . .. . rd:5 . ... &rd_imm imm=3D%ldst_d_imm =20 -# The 16-bit immediate is completely in the next word. -# Fields cannot be defined with no bits, so we cannot play -# the same trick and append to a zero-bit value. -# Defer reading the immediate until trans_{LDS,STS}. -@ldst_s .... ... rd:5 .... imm=3D0 +%ldst_imm !function=3Dnext_word +@ldst_s .... ... rd:5 .... imm=3D%ldst_imm =20 MOV 0010 11 . ..... .... @op_rd_rr MOVW 0000 0001 .... .... &rd_rr rd=3D%rd_d rr=3D%r= r_d --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751511; cv=none; d=zohomail.com; s=zohoarc; b=SqYyNcTIVIiyq83klQnNOzvueujCGMgMU/G+00y6WPXBDMp4pP1/NPOJCluSoUS9tqydoiCHVHGJcUPjFJ8PsC9pLZm4A5VTWqKF8TZaE4TuuLOepkBYhBvWORiyxs44cLX8zJk73wuFyzSjW+zmvnc1QgJBzoJkOppHwf7q+qU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751511; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=V9RNNm4TR2xsqepmbMUFAdeBIjBUZTQEvJCdv4fdD0o=; b=XraeWqxqLlCDz0BbAX/cDtBEdyheoiUYBdnoPPxiDi3WiZTfNjRQlszhqtmFV6/a0zX14ZdMwylAwFH2Gwr++JDterEGPlvtd0g+T1A1QHSsghgSxI11nZWMWzAOiUuuewCFo/r//LeQq85VKiO/DlE2L2iKLFTSQzaMiETuB4A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751511718555.0908237436333; Sun, 23 Mar 2025 10:38:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGY-0005r5-JQ; Sun, 23 Mar 2025 13:37:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGV-0005oL-2c for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:39 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGS-0002tA-DG for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:38 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-22409077c06so60879885ad.1 for ; Sun, 23 Mar 2025 10:37:35 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 2 -- target/avr/helper.c | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 06f5ae4d1b..84a8f5cc8c 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -60,8 +60,6 @@ #define OFFSET_CODE 0x00000000 /* CPU registers, IO registers, and SRAM */ #define OFFSET_DATA 0x00800000 -/* CPU registers specifically, these are mapped at the start of data */ -#define OFFSET_CPU_REGISTERS OFFSET_DATA /* * IO registers, including status register, stack pointer, and memory * mapped peripherals, mapped just after CPU registers diff --git a/target/avr/helper.c b/target/avr/helper.c index 3412312ad5..e5bf16c6b7 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -340,8 +340,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uin= t32_t addr) env->fullacc =3D false; =20 /* Following logic assumes this: */ - assert(OFFSET_CPU_REGISTERS =3D=3D OFFSET_DATA); - assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_CPU_REGISTERS + + assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_DATA + NUMBER_OF_CPU_REGISTERS); =20 if (addr < NUMBER_OF_CPU_REGISTERS) { --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751685; cv=none; d=zohomail.com; s=zohoarc; b=Gm8MmvJEMHG/Na+XfYZeUrgoZniSGHTNNWTW0C7SqUAoBqza98mWgt/bo531tUIKHYd+OSbNh/SwhN1b9ddCyZL7RlAg/hbcbr+JLv6oAVY1eeu3VAghk0CA/KWqlOUXa2PomTs6oNu6RTQCwP8hn+mCjgcj+e1cvEL/ZL/ypAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751685; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9/Tq8455Xl28q7efQW3SLtflxU6Hj8gr8oQW0BIa1vs=; b=X1y91bAGJnVMhjS/vCpGXW0XB8ytESTo7vj0s4pu6JuHE0a/L9nmRQIOtC/9JeH8/0vx2Cn7EQtumKzZY8lgKM1diJg0QvbJKcmh6TjuJBBUg/MMWpovrQCAjToM041J+Vok4w/QU1lUx5DBX+jjRoclYHsV6AKurYgNw/Ckd44= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751685389953.7811973411941; Sun, 23 Mar 2025 10:41:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGX-0005qP-VU; Sun, 23 Mar 2025 13:37:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGW-0005p8-54 for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:40 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGS-0002tI-OJ for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:39 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-227a8cdd241so13077305ad.3 for ; Sun, 23 Mar 2025 10:37:36 -0700 (PDT) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751455; x=1743356255; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9/Tq8455Xl28q7efQW3SLtflxU6Hj8gr8oQW0BIa1vs=; b=BuMIbuMuWTXUDEPn5Nrt/GFlLu1ZItNBMZPMMIF/lrmzZkdDVt3pCgiXsWzpHWsh4a 9rETYhXY8w4XIca6rj6wPsJeCgIRRP4pUdrKfkBwrnYPmJutKy6+bp0ppT2LaJiXVW2d 84giPDVE+kLQhh7LhwmoSZ+4N5Aq+NMUdFbpBzdFrOvOtVuQ/3Z+JM1X49tyqdnP60h/ iGf52sO5/NUR49S5R36TapGM8a8UvzDFBZvokKLNi1P3FSDQxckb+i6tDGrjlql0ovrc v+vPiPyG41m452TuHUoqsAFrSTvL2QRF9tolN8frT5un/vftvYrlddSkzV5Cq08h9Ujk PQvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751455; x=1743356255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9/Tq8455Xl28q7efQW3SLtflxU6Hj8gr8oQW0BIa1vs=; b=Csk3Ep55pVvmmtMtGEl8VYTKwiD8PSWDonXUIKDWDtz06ttcHgZM0KYE+vXGUcbkWs AoqLwpif1dAJTucE9I5hzBJ3VNFquD9/xAOsoUwEmZhhD74dikTxtjlyAQw+3SzkZtq/ 79Q61M9VB/JgwQ06lcNQ0+zpWLcQFiynD8rBlhUJOk7iq4JHpCjHbfwLwdivB1cmLlly o70f15yNuB2ZRCbMJhQeORGhvTPt91nqbNX30axHvDFSHUSObEpDbkagUiuuxjnx/fuM knOToYLFhybA02Y6jHAj2pv2UJBr/W+l1AvSlnci3Nx2lY8HGzEDqJlJjZFPYwBWgQlV KZ/Q== X-Gm-Message-State: AOJu0YyamtFzS0IPYjzMu/bLcNuxRodmFxxC0iyUGWzRwTyuaW+nwpNc +QJs1kXuSi62C+zzD8q1sA7Kcsys0gmjP3aNS+NuiV3TTHhHtB6bBdkI+0qtevGSAp+X/i/Eib9 X X-Gm-Gg: ASbGnctPpRWq34olvh2+bCUOxUkmQVXGhRkrtBVdUHhCK2dym6o2YPiKpES8mupTD1u sdO7OBDR4/nv1w5IL9pWP2m4pasR4EezorFCZ2a3tlP6WiLIv4temRiV8MgiH7sFH0PVDrbsz42 GIkcrtQsGrph7y0Y0RSrw+TkCmnXqGC+6NiNpzBfdzQPVgaGBwzq/y7oMtqL7iod56Ye8t4uG+c Mxdgg9qAOu6ympnH+IQUC8mD4oSVse68P1ZjpbeOEC2jz8oD/k0HLnGW2GVrJB4ViReGI9exBEO PHNBuFEswdynT4x4cMLLToyMr7Uq8mGd3lWy2qb6IRLoVX8NcYJyQSl59u33inLmlp1/YnJNd2p F X-Google-Smtp-Source: AGHT+IGKvT8qm0wChFsqWsxeKZ+j+oxfopqxoeEguwbwTSqH4umTXD8XEjAMzuxazBVvQqgyJrHFiw== X-Received: by 2002:a17:902:e54d:b0:21f:1549:a55a with SMTP id d9443c01a7336-22780c50856mr151984365ad.1.1742751455161; Sun, 23 Mar 2025 10:37:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 05/17] target/avr: Move cpu register accesses into system memory Date: Sun, 23 Mar 2025 10:37:17 -0700 Message-ID: <20250323173730.3213964-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751685916116600 Content-Type: text/plain; charset="utf-8" Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into the cpu registers with normal address space accesses. We no longer need to trap accesses to the first page within avr_cpu_tlb_fill but can wait until a write occurs. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 7 ++ target/avr/helper.h | 3 - target/avr/cpu.c | 16 +++ target/avr/helper.c | 239 +++++++++++++++++------------------------ target/avr/translate.c | 42 ++++---- 5 files changed, 146 insertions(+), 161 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 84a8f5cc8c..be27b0152b 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memory.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" @@ -142,6 +143,9 @@ struct ArchCPU { =20 CPUAVRState env; =20 + MemoryRegion cpu_reg1; + MemoryRegion cpu_reg2; + /* Initial value of stack pointer */ uint32_t init_sp; }; @@ -242,6 +246,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +extern const MemoryRegionOps avr_cpu_reg1; +extern const MemoryRegionOps avr_cpu_reg2; + #include "exec/cpu-all.h" =20 #endif /* QEMU_AVR_CPU_H */ diff --git a/target/avr/helper.h b/target/avr/helper.h index 4d02e648fa..e8d13e925f 100644 --- a/target/avr/helper.h +++ b/target/avr/helper.h @@ -23,7 +23,4 @@ DEF_HELPER_1(debug, noreturn, env) DEF_HELPER_1(break, noreturn, env) DEF_HELPER_1(sleep, noreturn, env) DEF_HELPER_1(unsupported, noreturn, env) -DEF_HELPER_3(outb, void, env, i32, i32) -DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(fullwr, void, env, i32, i32) -DEF_HELPER_2(fullrd, tl, env, i32) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 834c7082aa..0b14b36c17 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/exec-all.h" #include "exec/translation-block.h" +#include "exec/address-spaces.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -110,6 +111,8 @@ static void avr_cpu_disas_set_info(CPUState *cpu, disas= semble_info *info) static void avr_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + CPUAVRState *env =3D cpu_env(cs); + AVRCPU *cpu =3D env_archcpu(env); AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 @@ -122,6 +125,19 @@ static void avr_cpu_realizefn(DeviceState *dev, Error = **errp) cpu_reset(cs); =20 mcc->parent_realize(dev, errp); + + /* + * Two blocks in the low data space loop back into cpu registers. + */ + memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, + "avr-cpu-reg1", 32); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA, &cpu->cpu_reg1); + + memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, + "avr-cpu-reg2", 8); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + 0x58, &cpu->cpu_reg2); } =20 static void avr_cpu_set_int(void *opaque, int irq, int level) diff --git a/target/avr/helper.c b/target/avr/helper.c index e5bf16c6b7..df7e2109d4 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -108,7 +108,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - int prot, page_size =3D TARGET_PAGE_SIZE; + int prot; uint32_t paddr; =20 address &=3D TARGET_PAGE_MASK; @@ -133,23 +133,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, /* Access to memory. */ paddr =3D OFFSET_DATA + address; prot =3D PAGE_READ | PAGE_WRITE; - if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* - * Access to CPU registers, exit and rebuilt this TB to use - * full access in case it touches specially handled registers - * like SREG or SP. For probing, set page_size =3D 1, in order - * to force tlb_fill to be called for the next access. - */ - if (probe) { - page_size =3D 1; - } else { - cpu_env(cs)->fullacc =3D 1; - cpu_loop_exit_restore(cs, retaddr); - } - } } =20 - tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } =20 @@ -203,134 +189,78 @@ void helper_wdr(CPUAVRState *env) } =20 /* - * This function implements IN instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is read and returned - * b. otherwise io address is translated to mem address and physical memo= ry - * is read. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation - * + * The first 32 bytes of the data space are mapped to the cpu regs. + * We cannot write these from normal store operations because TCG + * does not expect global temps to be modified -- a global may be + * live in a host cpu register across the store. We can however + * read these, as TCG does make sure the global temps are saved + * in case the load operation traps. */ -target_ulong helper_inb(CPUAVRState *env, uint32_t port) + +static uint64_t avr_cpu_reg1_read(void *opaque, hwaddr addr, unsigned size) { - target_ulong data =3D 0; + CPUAVRState *env =3D opaque; =20 - switch (port) { - case 0x38: /* RAMPD */ - data =3D 0xff & (env->rampD >> 16); - break; - case 0x39: /* RAMPX */ - data =3D 0xff & (env->rampX >> 16); - break; - case 0x3a: /* RAMPY */ - data =3D 0xff & (env->rampY >> 16); - break; - case 0x3b: /* RAMPZ */ - data =3D 0xff & (env->rampZ >> 16); - break; - case 0x3c: /* EIND */ - data =3D 0xff & (env->eind >> 16); - break; - case 0x3d: /* SPL */ - data =3D env->sp & 0x00ff; - break; - case 0x3e: /* SPH */ - data =3D env->sp >> 8; - break; - case 0x3f: /* SREG */ - data =3D cpu_get_sreg(env); - break; - default: - /* not a special register, pass to normal memory access */ - data =3D address_space_ldub(&address_space_memory, - OFFSET_IO_REGISTERS + port, - MEMTXATTRS_UNSPECIFIED, NULL); - } - - return data; + assert(addr < 32); + return env->r[addr]; } =20 /* - * This function implements OUT instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is written into the re= gister - * b. otherwise io address is translated to mem address and physical mem= ory - * is written. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementati= on - * + * The range 0x58-0x5f of the data space are mapped to cpu regs. + * As above, we cannot write these from normal store operations. */ -void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) -{ - data &=3D 0x000000ff; =20 - switch (port) { - case 0x38: /* RAMPD */ - if (avr_feature(env, AVR_FEATURE_RAMPD)) { - env->rampD =3D (data & 0xff) << 16; - } - break; - case 0x39: /* RAMPX */ - if (avr_feature(env, AVR_FEATURE_RAMPX)) { - env->rampX =3D (data & 0xff) << 16; - } - break; - case 0x3a: /* RAMPY */ - if (avr_feature(env, AVR_FEATURE_RAMPY)) { - env->rampY =3D (data & 0xff) << 16; - } - break; - case 0x3b: /* RAMPZ */ - if (avr_feature(env, AVR_FEATURE_RAMPZ)) { - env->rampZ =3D (data & 0xff) << 16; - } - break; - case 0x3c: /* EIDN */ - env->eind =3D (data & 0xff) << 16; - break; - case 0x3d: /* SPL */ - env->sp =3D (env->sp & 0xff00) | (data); - break; - case 0x3e: /* SPH */ - if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { - env->sp =3D (env->sp & 0x00ff) | (data << 8); - } - break; - case 0x3f: /* SREG */ - cpu_set_sreg(env, data); - break; - default: - /* not a special register, pass to normal memory access */ - address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + por= t, - data, MEMTXATTRS_UNSPECIFIED, NULL); +static uint64_t avr_cpu_reg2_read(void *opaque, hwaddr addr, unsigned size) +{ + CPUAVRState *env =3D opaque; + + switch (addr) { + case 0: /* RAMPD */ + return 0xff & (env->rampD >> 16); + case 1: /* RAMPX */ + return 0xff & (env->rampX >> 16); + case 2: /* RAMPY */ + return 0xff & (env->rampY >> 16); + case 3: /* RAMPZ */ + return 0xff & (env->rampZ >> 16); + case 4: /* EIND */ + return 0xff & (env->eind >> 16); + case 5: /* SPL */ + return env->sp & 0x00ff; + case 6: /* SPH */ + return 0xff & (env->sp >> 8); + case 7: /* SREG */ + return cpu_get_sreg(env); } + g_assert_not_reached(); } =20 -/* - * this function implements LD instruction when there is a possibility to= read - * from a CPU register - */ -target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) +static void avr_cpu_trap_write(void *opaque, hwaddr addr, + uint64_t data64, unsigned size) { - uint8_t data; + CPUAVRState *env =3D opaque; + CPUState *cs =3D env_cpu(env); =20 - env->fullacc =3D false; - - if (addr < NUMBER_OF_CPU_REGISTERS) { - /* CPU registers */ - data =3D env->r[addr]; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - data =3D helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS); - } else { - /* memory */ - data =3D address_space_ldub(&address_space_memory, OFFSET_DATA + a= ddr, - MEMTXATTRS_UNSPECIFIED, NULL); - } - return data; + env->fullacc =3D true; + cpu_loop_exit_restore(cs, cs->mem_io_pc); } =20 +const MemoryRegionOps avr_cpu_reg1 =3D { + .read =3D avr_cpu_reg1_read, + .write =3D avr_cpu_trap_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + +const MemoryRegionOps avr_cpu_reg2 =3D { + .read =3D avr_cpu_reg2_read, + .write =3D avr_cpu_trap_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + /* * this function implements ST instruction when there is a possibility to= write * into a CPU register @@ -339,19 +269,50 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, u= int32_t addr) { env->fullacc =3D false; =20 - /* Following logic assumes this: */ - assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_DATA + - NUMBER_OF_CPU_REGISTERS); - - if (addr < NUMBER_OF_CPU_REGISTERS) { + switch (addr) { + case 0 ... 31: /* CPU registers */ env->r[addr] =3D data; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data); - } else { - /* memory */ + break; + + case 0x58: /* RAMPD */ + if (avr_feature(env, AVR_FEATURE_RAMPD)) { + env->rampD =3D data << 16; + } + break; + case 0x59: /* RAMPX */ + if (avr_feature(env, AVR_FEATURE_RAMPX)) { + env->rampX =3D data << 16; + } + break; + case 0x5a: /* RAMPY */ + if (avr_feature(env, AVR_FEATURE_RAMPY)) { + env->rampY =3D data << 16; + } + break; + case 0x5b: /* RAMPZ */ + if (avr_feature(env, AVR_FEATURE_RAMPZ)) { + env->rampZ =3D data << 16; + } + break; + case 0x5c: /* EIDN */ + env->eind =3D data << 16; + break; + case 0x5d: /* SPL */ + env->sp =3D (env->sp & 0xff00) | data; + break; + case 0x5e: /* SPH */ + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { + env->sp =3D (env->sp & 0x00ff) | (data << 8); + } + break; + case 0x5f: /* SREG */ + cpu_set_sreg(env, data); + break; + + default: address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, MEMTXATTRS_UNSPECIFIED, NULL); + break; } } diff --git a/target/avr/translate.c b/target/avr/translate.c index e7f8ced9b3..0490936cd5 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -194,6 +194,9 @@ static bool avr_have_feature(DisasContext *ctx, int fea= ture) static bool decode_insn(DisasContext *ctx, uint16_t insn); #include "decode-insn.c.inc" =20 +static void gen_inb(DisasContext *ctx, TCGv data, int port); +static void gen_outb(DisasContext *ctx, TCGv data, int port); + /* * Arithmetic Instructions */ @@ -1293,9 +1296,8 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_EQ; ctx->skip_var0 =3D data; @@ -1311,9 +1313,8 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_NE; ctx->skip_var0 =3D data; @@ -1502,11 +1503,18 @@ static void gen_data_store(DisasContext *ctx, TCGv = data, TCGv addr) =20 static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { - if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { - gen_helper_fullrd(data, tcg_env, addr); - } else { - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); - } + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); +} + +static void gen_inb(DisasContext *ctx, TCGv data, int port) +{ + gen_data_load(ctx, data, tcg_constant_i32(port + NUMBER_OF_CPU_REGISTE= RS)); +} + +static void gen_outb(DisasContext *ctx, TCGv data, int port) +{ + gen_helper_fullwr(tcg_env, data, + tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS)); } =20 /* @@ -2126,9 +2134,8 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) static bool trans_IN(DisasContext *ctx, arg_IN *a) { TCGv Rd =3D cpu_r[a->rd]; - TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_inb(Rd, tcg_env, port); + gen_inb(ctx, Rd, a->imm); return true; } =20 @@ -2139,9 +2146,8 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) static bool trans_OUT(DisasContext *ctx, arg_OUT *a) { TCGv Rd =3D cpu_r[a->rd]; - TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_outb(tcg_env, port, Rd); + gen_outb(ctx, Rd, a->imm); return true; } =20 @@ -2407,11 +2413,10 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP = *a) static bool trans_SBI(DisasContext *ctx, arg_SBI *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_ori_tl(data, data, 1 << a->bit); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } =20 @@ -2422,11 +2427,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) static bool trans_CBI(DisasContext *ctx, arg_CBI *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } =20 --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Make use of the softmmu cache of the i/o page. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index df7e2109d4..7cfd3d1093 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,10 +23,10 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/getpc.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" -#include "exec/address-spaces.h" #include "exec/helper-proto.h" =20 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -67,6 +67,11 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_= request) return false; } =20 +static void do_stb(CPUAVRState *env, uint32_t addr, uint8_t data, uintptr_= t ra) +{ + cpu_stb_mmuidx_ra(env, addr, data, MMU_DATA_IDX, ra); +} + void avr_cpu_do_interrupt(CPUState *cs) { CPUAVRState *env =3D cpu_env(cs); @@ -311,8 +316,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uin= t32_t addr) break; =20 default: - address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, - MEMTXATTRS_UNSPECIFIED, NULL); + do_stb(env, addr, data, GETPC()); break; } } --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751501; cv=none; d=zohomail.com; s=zohoarc; b=bfxItyci4CuQuMw7oSlSyY2nXbNbKQUGACAZY3nLAO0CF8r13caNIGGPdczoKOXvkNx5lYSq+KG87AsMxQ0+Tsmk1jOZ51RfmyESpdm7QOkcdl90tmANq4+oHQlAmf85DwYbf1TEDGJwCnXX2sXsGpKhRBhHT06hemBiYI/Agwg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751501; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kuaWE3TjFjqiJm1M4aj1btd/FSbEJW/CWHj5+bscQKY=; b=ZfF8fAzrBYt1Ab/zwxciDZSnuH3vqLkapIg4YhDoQdyy/qAWWjBoOVpsFcUN6jXe/aVlEf5+x4oHFBjYPo/GModEnJ4H5vJ9dp5mTx0XcuCQtb7SIa1plqpQxtK3smr0rP6hMSzS18PSnujjCMGRBDnnGuj8oe+PLmG2mRRN+sc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751500994864.9655395753406; Sun, 23 Mar 2025 10:38:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGY-0005qr-Au; Sun, 23 Mar 2025 13:37:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGV-0005p0-NY for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:39 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGU-0002tf-2W for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:39 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-22398e09e39so70809405ad.3 for ; Sun, 23 Mar 2025 10:37:37 -0700 (PDT) Received: from stoup.. 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Sun, 23 Mar 2025 10:37:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 07/17] target/avr: Use do_stb in avr_cpu_do_interrupt Date: Sun, 23 Mar 2025 10:37:19 -0700 Message-ID: <20250323173730.3213964-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751501678116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/avr/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index 7cfd3d1093..9608e59584 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -88,14 +88,14 @@ void avr_cpu_do_interrupt(CPUState *cs) } =20 if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); - cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); + do_stb(env, env->sp--, ret >> 16, 0); } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); } else { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); + do_stb(env, env->sp--, ret, 0); } =20 env->pc_w =3D base + vector * size; --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751487; cv=none; d=zohomail.com; s=zohoarc; b=fKRjLBAQ6fSO8uiE55jD2dh0JEqbEg0u52Mw6QeJz7rCn+/8UO8BhXALQmCeLlUuLnHv9n1kkEL4678X3LEiyPCRv2Pd35IPRw+8KcjLWe0Yk0kGeyO+eIZKwE8tiUF03XRYoZYkSJaa3iqRyXrBOEa6P1aTND4lvpmSlPQ/wik= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751487; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rA9BN8KH+TQHBF8y80g6NTHRuQA2RHpbRpcidozR5So=; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751457; x=1743356257; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rA9BN8KH+TQHBF8y80g6NTHRuQA2RHpbRpcidozR5So=; b=mf1Z64jOULGRXw1/xLSETzXbYNLRj4w/bGhpiMPw/5kISuh4Bl4Ho3O8c7U/+d/QvR ykGZ/OuGgbto3AN5YJwBnWtrZzklHlAD0vaRDJ4XPKkvZTDuVUpZHN/ETfBPnJRB0LLm 6rQAe9QHniUFzZ8YmcpPgneklmLrRNw3brdUysHrq5OgS4RoD7TFZSR92aadqiMEmYQC qSAZbYNTNIfka/qrEVVF5o3XVF+VaSi5/+UJYJbikwVeH12UO3LlOpF0xhaaFCBymPi3 +tWG7uHCICObli1mtuaHn45pUOp4Y/LeT73lKVLTmisYG0/PP9rctsI95McS3NkggFdw NK+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751457; x=1743356257; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rA9BN8KH+TQHBF8y80g6NTHRuQA2RHpbRpcidozR5So=; b=tuGy8u+48FZsYzoiUYizLHx/U6+pjn75IOhRvIXfaXTyHR9EgAxQF++5vt5f/lwuq1 AyU53csQQZGYODBWYIlozLtoXmsGkKi4FPwZz7CtpL4VQhsNjNUmWi6IvgXGmwcRvlQv 3I7GkG1iJANPQCtIR0n6Hvnx2XR6t3caiRqp1aAnPZRMaJ1rOGg6luWjYSzkHmcMg7gn 3FaVXMDYpPQ7U+Yf9RhpD2BqvCwG+BGOcaWXVKeXFllyzr/XZBBa5MzAxHFnHSYUi2Gl bNsvY/sByG2zJl/8ZA8hZO3EgaXBigyBJR7WrVvAzihv5LtnqyQU2cJxfKBYuxBrV2nJ Jm1A== X-Gm-Message-State: AOJu0YyRhRfJ8Nz4aA8KK1/FLv6XDf/btWxLMq4MVmiTLVRwndpTiAid hL76i84DyayTJKSX1uUoFfBT7k4Fr77zMTU69vPMAEE+E26jSALevMnpinobnA38bY5z5K03UlE U X-Gm-Gg: ASbGncv9UDxAHvmkpxXmAhgShdG5EiW+7gOF9oWCiTj+eX+qnAkSZY57HXVeIw5gkif H1dYM/tFaxPl4Ae6ef9Wq/66GJ+mezdtw57pBFdjER+QzY80YrAuqP/fEVKA9inb84DIELBtUP5 olJ5qQgu9P6z+KTw5rg+WUP2vM7RC8d8IK1Z47dRERbRtJ7q6VdXLNyTTsLYn1ivJ3CKZDqBuM3 y3JMe8NdkWYkdFSDgwk2unnNZdBjSL8MXbIFRHSZPRdBFquka334hRrt0HqrFSkyz2GqcuCGwIM Glv2J5NDoZwuLhafIRzQ3vSZl3fSfPGkRKbrKHAaoUDikJlk8MejpMyHaHT1w1aIQwAQ6dGmAHs bE5AY9qw9snY= X-Google-Smtp-Source: AGHT+IHkOjuzjmhJgV6JaV/SXtj5NUSPfXQWfBo5RzZy8Hq2cwFPpGSc09FzCDwtT/9LWFsMMcLYVw== X-Received: by 2002:a17:903:1aac:b0:220:df73:b639 with SMTP id d9443c01a7336-22780e0b2efmr153799675ad.36.1742751457346; Sun, 23 Mar 2025 10:37:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 08/17] target/avr: Add offset-io cpu property Date: Sun, 23 Mar 2025 10:37:20 -0700 Message-ID: <20250323173730.3213964-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751489665116600 Content-Type: text/plain; charset="utf-8" Communicate the offset of io within the first page between the board, the cpu, and the translator. So far this is always 0. This will be used to optimize memory layout. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 2 ++ hw/avr/atmega.c | 2 ++ target/avr/cpu.c | 1 + target/avr/translate.c | 2 ++ 4 files changed, 7 insertions(+) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index be27b0152b..0f5e1a53bc 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -148,6 +148,8 @@ struct ArchCPU { =20 /* Initial value of stack pointer */ uint32_t init_sp; + /* Offset of the beginning of I/O within the first page. */ + uint32_t offset_io; }; =20 /** diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index f6844bf118..273582b8af 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -236,6 +236,8 @@ static void atmega_realize(DeviceState *dev, Error **er= rp) =20 object_property_set_uint(OBJECT(&s->cpu), "init-sp", mc->io_size + mc->sram_size - 1, &error_abort= ); + object_property_set_uint(OBJECT(&s->cpu), "offset-io", + 0, &error_abort); =20 qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev =3D DEVICE(&s->cpu); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0b14b36c17..080f6f30d3 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -169,6 +169,7 @@ static void avr_cpu_initfn(Object *obj) =20 static const Property avr_cpu_properties[] =3D { DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0), + DEFINE_PROP_UINT32("offset-io", AVRCPU, offset_io, 0), }; =20 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) diff --git a/target/avr/translate.c b/target/avr/translate.c index 0490936cd5..e9fef1aaad 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -92,6 +92,7 @@ struct DisasContext { =20 /* Routine used to access memory */ int memidx; + uint32_t offset_io; =20 /* * some AVR instructions can make the following instruction to be skip= ped @@ -2664,6 +2665,7 @@ static void avr_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->env =3D cpu_env(cs); ctx->npc =3D ctx->base.pc_first / 2; + ctx->offset_io =3D env_archcpu(ctx->env)->offset_io; =20 ctx->skip_cond =3D TCG_COND_NEVER; if (tb_flags & TB_FLAGS_SKIP) { --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751511; cv=none; d=zohomail.com; s=zohoarc; b=KMOQE26uojJyYaQ/Rm2KOf8aYdJUAaejTrd7dcmbrFx9hgnWPnFrFA6XvgxlFhwnd6W3yG3Loz3KC1qKWIBUWVwuay90z1AdRaP2S7lkdRwZvQQ3m+xC/60xxFRytPWnqQ/U56AKvCH8az08TwB+2qWQxlODz1geLvf1akozO7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751511; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mKxBSROc4fhAqj5Wcj6941rZxM/sEBCStnSlK0YH6kE=; b=J/ZmogyG9cXcHUrqeIvPRBEWnkFfPEv5AbxR+0QDhXMBk4U2fsJRYywA86UpSWT5LrWJmqQMhRR3cSuh4YZWl5aG6uwtnQhX3zKKx/ujmBLrQHBK2W98V2Hd5mOxV8otUL1w3pnsyKSPOlGPcxK4FcC2LoNcmkr0NDRtaj+uFqM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751511633476.1425863616555; Sun, 23 Mar 2025 10:38:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGb-0005sb-C6; Sun, 23 Mar 2025 13:37:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGX-0005q6-NI for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:41 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGV-0002uD-Uo for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:41 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-301cda78d48so7017751a91.0 for ; Sun, 23 Mar 2025 10:37:39 -0700 (PDT) Received: from stoup.. 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So far, all offsets are 0. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/translate.c | 42 ++++++++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index e9fef1aaad..6bb4154dff 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -198,6 +198,28 @@ static bool decode_insn(DisasContext *ctx, uint16_t in= sn); static void gen_inb(DisasContext *ctx, TCGv data, int port); static void gen_outb(DisasContext *ctx, TCGv data, int port); =20 +static void gen_data_store_raw(DisasContext *ctx, TCGv data, + TCGv addr, int offset, MemOp mop) +{ + if (ctx->offset_io + offset) { + TCGv t =3D tcg_temp_new(); + tcg_gen_addi_tl(t, addr, ctx->offset_io + offset); + addr =3D t; + } + tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, mop); +} + +static void gen_data_load_raw(DisasContext *ctx, TCGv data, + TCGv addr, int offset, MemOp mop) +{ + if (ctx->offset_io + offset) { + TCGv t =3D tcg_temp_new(); + tcg_gen_addi_tl(t, addr, ctx->offset_io + offset); + addr =3D t; + } + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, mop); +} + /* * Arithmetic Instructions */ @@ -940,21 +962,21 @@ static void gen_push_ret(DisasContext *ctx, int ret) if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { TCGv t0 =3D tcg_constant_i32(ret & 0x0000ff); =20 - tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); + gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_UB); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { TCGv t0 =3D tcg_constant_i32(ret & 0x00ffff); =20 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); - tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); + gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_BEUW); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { TCGv lo =3D tcg_constant_i32(ret & 0x0000ff); TCGv hi =3D tcg_constant_i32((ret & 0xffff00) >> 8); =20 - tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); + gen_data_store_raw(ctx, lo, cpu_sp, 0, MO_UB); tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); - tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); + gen_data_store_raw(ctx, hi, cpu_sp, 0, MO_BEUW); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); } } @@ -963,20 +985,20 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret) { if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB); + gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_UB); } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW); + gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_BEUW); tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { TCGv lo =3D tcg_temp_new_i32(); TCGv hi =3D tcg_temp_new_i32(); =20 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); + gen_data_load_raw(ctx, hi, cpu_sp, 0, MO_BEUW); =20 tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); - tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); + gen_data_load_raw(ctx, lo, cpu_sp, 0, MO_UB); =20 tcg_gen_deposit_tl(ret, lo, hi, 8, 16); } @@ -1498,13 +1520,13 @@ static void gen_data_store(DisasContext *ctx, TCGv = data, TCGv addr) if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { gen_helper_fullwr(tcg_env, data, addr); } else { - tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB); + gen_data_store_raw(ctx, data, addr, 0, MO_UB); } } =20 static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); + gen_data_load_raw(ctx, data, addr, 0, MO_UB); } =20 static void gen_inb(DisasContext *ctx, TCGv data, int port) --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751459; x=1743356259; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x+vLIWb2Nw1GLPq2/BHeGFtpTQCooqKOLeKJY8lQCig=; b=DAkiNHvGRsS2k3c48YfAaog5bKI+lqpkPoryIG0abF8K0hIfyuBPUYvze1rHiMihYk V+KUSL4qCNR8gABd5ic4nL3jCnMLy1/NrBVuLaZah700RnTJwlSoq/8HibfqNeJKtsvH /3Mu5TVJRznBaAW0NtxJMYN4rIUR//Hv/98n6IecopfxtpXqhFpOsZodMWUmu95iqj7t 06iEPfX/6heyW2gBNdFcjwBPC5mWuDbMg334GgAsVZ2GSkxKt0dkt461lpn/XevD33jQ DFRBAZIFpSn2iaO42+buW7nWAX6mC7J1/55uYBijfT6wZlcwa6Dm+jLwWebwYHTKEZPV RVkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751459; x=1743356259; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x+vLIWb2Nw1GLPq2/BHeGFtpTQCooqKOLeKJY8lQCig=; b=LpTfP4rYRed+NS7JI/cSE6Cmu0lFbkbiDTP/1mvZbYA3SJ/dlLwISo9uIFWozpQxP1 z1aQWIa0i/8G/lk0i1BJYYjB/TWmgNe++IGC4KOOXrpwUvpaFRFuDnJ1iR2MTVQXj4eM HmdUEBfkrpIF7w1Gs9aKW0K83fN+5A5ZD+QlZLFZaD1WK3RAAnA0J6NjAadg6SeOzL4Y uPTat+wLBGoeGr460QhH1pcCcKFi0akbCTDCBxHKcGC1Zgw64ocQIMpcOVFJwnaZxNZr Al/y6FfZye/U07LoDfYA/K2DUvj2c2zkS4obYtzLJClKLyXbFNK5y4hAcseC8QGqFA2j THKg== X-Gm-Message-State: AOJu0YyJ16MCQTt5SzACrTBcKUGETw4rdDVaCr+nNFBhBOCC4/HsPT8c yXLvb/GDXRggZ/f9vv5V3kFO4fNZgfaizxwSNU8IAadBOXIeLyb/wHj1gUymErjvW/F0e5TAkKu / X-Gm-Gg: ASbGnct4pW4DnLMYxKP75xbYSr2RUzwZL6A8tApSi3IREearOmuTs90Sy0qHwLDohR2 gY8qlkWXcuCxXdR+JATZIJLw3JhJZGHdXBsBBNj4GnOOtHt1r3LWPdkOtmB2Lqkb7GC/meQGxYK Wc7r6FY+mCxFbnu9E203o+0AoZTKoVo9eC/YzLzVp9eqBQrQ/q4xSkhNSNxVzh5LDvQFu9Z088j FNQGp5z9vq55MtaX7850Q5QRLQvcImjLQxQXcILE55OSRGtI03lmi+WFEKKrhKW2jL3n8qPz5dX qZ3XiQyQgJ1+rFZXU7DPv6Y+/9fD9UO5uPgvxxlELCJc++a/4pmhkTZqRHfklleW7NwhS5x+0nQ c X-Google-Smtp-Source: AGHT+IF0rn6volJhof4Cblgwxtyuw23K5pkcWeEqt9RzdZlH9qmfjGipBE1VOhJ4TECBUyJ5i0nJsA== X-Received: by 2002:a17:903:2284:b0:220:cb6c:2e30 with SMTP id d9443c01a7336-22780e312bbmr174358795ad.49.1742751458814; Sun, 23 Mar 2025 10:37:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 10/17] target/avr: Update cpu_sp after push and pop Date: Sun, 23 Mar 2025 10:37:22 -0700 Message-ID: <20250323173730.3213964-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751855172116600 Content-Type: text/plain; charset="utf-8" Not that AVR has memory paging traps, but it's better form to allow the memory operation to finish before updating the cpu register. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/translate.c | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 6bb4154dff..3446007be1 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -967,40 +967,38 @@ static void gen_push_ret(DisasContext *ctx, int ret) } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { TCGv t0 =3D tcg_constant_i32(ret & 0x00ffff); =20 - tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); - gen_data_store_raw(ctx, t0, cpu_sp, 0, MO_BEUW); - tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); + gen_data_store_raw(ctx, t0, cpu_sp, -1, MO_BEUW); + tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { TCGv lo =3D tcg_constant_i32(ret & 0x0000ff); TCGv hi =3D tcg_constant_i32((ret & 0xffff00) >> 8); =20 gen_data_store_raw(ctx, lo, cpu_sp, 0, MO_UB); - tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); - gen_data_store_raw(ctx, hi, cpu_sp, 0, MO_BEUW); - tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); + gen_data_store_raw(ctx, hi, cpu_sp, -2, MO_BEUW); + tcg_gen_subi_tl(cpu_sp, cpu_sp, 3); + } else { + g_assert_not_reached(); } } =20 static void gen_pop_ret(DisasContext *ctx, TCGv ret) { if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { + gen_data_load_raw(ctx, ret, cpu_sp, 1, MO_UB); tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_UB); } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { - tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - gen_data_load_raw(ctx, ret, cpu_sp, 0, MO_BEUW); - tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); + gen_data_load_raw(ctx, ret, cpu_sp, 1, MO_BEUW); + tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { - TCGv lo =3D tcg_temp_new_i32(); TCGv hi =3D tcg_temp_new_i32(); =20 - tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); - gen_data_load_raw(ctx, hi, cpu_sp, 0, MO_BEUW); + gen_data_load_raw(ctx, hi, cpu_sp, 1, MO_BEUW); + gen_data_load_raw(ctx, ret, cpu_sp, 3, MO_UB); + tcg_gen_addi_tl(cpu_sp, cpu_sp, 3); =20 - tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); - gen_data_load_raw(ctx, lo, cpu_sp, 0, MO_UB); - - tcg_gen_deposit_tl(ret, lo, hi, 8, 16); + tcg_gen_deposit_tl(ret, ret, hi, 8, 16); + } else { + g_assert_not_reached(); } } =20 --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751541; cv=none; d=zohomail.com; s=zohoarc; b=eTER0Qc3t0fL7FsuzLuu/myEpepKaL463cghTomDQKmEPydSjBqrmcd4FgNv9Wvo5qZm90fscjUDckAPCyjo4nFthszy16Tn9HaO5CI3IHGOY2izMjxmByuO+Ryb7xlt9jbqDzoN8p0k9hUFwChPoK+/vZfkpv2eqSctKSto4Gs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751541; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oGR007VvjFffVl8PvgR+T2VNJf200xt2PbQ7cdgNESw=; b=iJiNsttAASV7Koc+8qhE9LStNUWnZLcCaNy3UPij1GncVbwAHgbeXmOnrg53fifadc+vscXI3H8AAb4dxWzyCzBxUjlnlYj6xQkZK7C0yI6GwqfCNTvE/voQShcrcnFi23NXdCYK09/T+g/THKYfB0BnZCmKCefyWyzouWcbepM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751541663225.87571207459007; Sun, 23 Mar 2025 10:39:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGb-0005sa-C4; Sun, 23 Mar 2025 13:37:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGY-0005r7-MK for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:42 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGW-0002un-UE for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:42 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-223fd89d036so64755695ad.1 for ; Sun, 23 Mar 2025 10:37:40 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/avr/cpu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 080f6f30d3..e4011004b4 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -68,6 +68,35 @@ static void avr_restore_state_to_opc(CPUState *cs, cpu_env(cs)->pc_w =3D data[0]; } =20 +static int avr_memory_rw_debug(CPUState *cpu, vaddr addr, + uint8_t *buf, size_t len, bool is_write) +{ + if (addr < OFFSET_DATA) { + size_t len_code; + int ret; + + if (addr + len <=3D OFFSET_DATA) { + return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); + } + + len_code =3D addr + len - OFFSET_DATA; + ret =3D cpu_memory_rw_debug(cpu, addr, buf, len_code, is_write); + if (ret !=3D 0) { + return ret; + } + addr =3D OFFSET_DATA; + len -=3D len_code; + } + + /* + * Data is biased such that SRAM begins at TARGET_PAGE_SIZE, + * and I/O is immediately prior. This leave a hole between + * OFFSET_DATA and the relative start of the address space. + */ + addr +=3D env_archcpu(cpu_env(cpu))->offset_io; + return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); +} + static void avr_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); @@ -262,6 +291,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->gdb_write_register =3D avr_cpu_gdb_write_register; cc->gdb_adjust_breakpoint =3D avr_cpu_gdb_adjust_breakpoint; cc->gdb_core_xml_file =3D "avr-cpu.xml"; + cc->memory_rw_debug =3D avr_memory_rw_debug; cc->tcg_ops =3D &avr_tcg_ops; } =20 --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751718; cv=none; d=zohomail.com; s=zohoarc; b=Oex8QPJbvALhnQ8iKNN1pmMJlG7Zxf/RNUZRwxqGOJUdx3Md/ky+Grt9O/MSuIn8tzUnreXgCUEWMbPcjJg4q4hmWmp5sCj0xIrJyx8MR1zx/g+7KKg4Kn9JJOqlcXDzV0JFx3PdtJN0oEn9EKoPkO3Crva1KSF2SpDvf7ack3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751718; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=n5/rrT9rGaCRyYHGfR9L9lev75C870EJXXZh29se8QE=; b=CNqa5QSA+cM2fLyy6ymg0jjCmkbkkWwIG+WJbr9+l8KBda7n7wyXQyd1hGsdUCF8RRlmvaUMDSLHMAbfg1QDagdzULlHyboG4ApIT3t7H48jKQkFBVkxkWuIAAprMtV9AgDroFkzy2kC+oFspjmwqMjRpxNga0OCLvZxz8oe+ok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751718963619.7235671471072; Sun, 23 Mar 2025 10:41:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGd-0005u7-5S; Sun, 23 Mar 2025 13:37:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGZ-0005rN-9P for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:44 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGX-0002v0-Lx for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:43 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2255003f4c6so66876955ad.0 for ; Sun, 23 Mar 2025 10:37:41 -0700 (PDT) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751460; x=1743356260; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n5/rrT9rGaCRyYHGfR9L9lev75C870EJXXZh29se8QE=; b=V0kcn3QfBPvZI+tew/CR1Mc65ccpVAYzDu4sL/tEYVGo4RveRAvX3H1+vO0zzo/SIr LItWujIk8rCJ676QV1GvoPUE8D8hg8+Ht+qbbpwr5CIwQe/DO10wBkmuR3/0hT4k5pYs FaVibqyEMff7OY5bWaJRUNEHt+9527jodFo7daNZI2omAg0RZueIAzmrPCPK+gl/hYXg lZswQkpt0M0AAoXKhM+LyAwrVhKHktpBeriAI0v1BhVWD9Z2PvvrnGqdzJ02Ke7sWdu8 Zo3+q8PSRprseD9VzCnk8NZHybP1QMWEPdC1Z47Fj9bkkA2ZqQlZ5m7QKS93nwyPnJBX e9+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751460; x=1743356260; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n5/rrT9rGaCRyYHGfR9L9lev75C870EJXXZh29se8QE=; b=YA+rCNcBxMhYdVzgmHmrq/Gq9YyxmHHh0JyzJGH5RBoG/m6ypXeO6nSnZiIJQ2eKLj +ppKYb7OyvB8JxtOr72dkroYwtrGs83qALbYC1nUdHv3ZGXNjZmhUZkBy9lTxdFA8EVj g59kJo7Y04fm+xzNZtQbhMUxD67YeYUsm9PpGHzYLDxYgLZElY42iTiyIldh1vX13guD Z1fXjFrmxldsS9cBZ/K6TZv0kQqGeu7ZWlBDIrMEP9VMHd2jAjZC+nTqjLVy2Ifq6EC3 XBUs4TYvqmUbQ+ExJAqwy4oJOlNxF2wqw+G7uKlXyk3HMfDprrSSnjpwXW706CJas9q8 k45w== X-Gm-Message-State: AOJu0Yyua2AT2sveXHqHTZwsdRlf69NtGBmsm/HDXpHSUOGPIGFUA5F2 YHbUWCmA5NQkkzXjT+YRLaCDYYps0mfcPN7dy104aPG7iKgIMkRP8aA8qSY2MBx2hkXRE8Ke9Vg d X-Gm-Gg: ASbGncuuITguODO20uTJamKYUwP1uNZeYYbnwg/pILCdseEIodVXj+xjqrTE/owKcJN dUF0hJ8M+kDmzaoEjjRxlcv2qg1nVCO1Uk67UexcK9qZTNALhVG8BsRm093JT4YUZuFwdju94AN GyRfVd5XrRVsahLzc7grAFxKMhYtaH+SAmmqLT5zussnrp1ckRLfI93kqcWgGHACIbMg32sy4yW fKudnYdgy1s1ld4/94MumiDRmkBtigNP0wzRXoU/p0eTKfTXoisFz/La//zLpjrB4XIQU+8lwTA TO/YQqMUrtiRoHWNO3ipxBdu/Ji44E6uQeTn6ylP4E6By4tjOpsWdBCxw/sxXqglQLakU4gPljx LEqivXm7UwKw= X-Google-Smtp-Source: AGHT+IH/b1yUzgQ+kNOeWXZv97pYh9WAiXHTeLCP/1q17A19wPjHihwThAzrv9MMFbpd9mE3VVPK3w== X-Received: by 2002:a17:902:cccb:b0:223:65dc:4580 with SMTP id d9443c01a7336-22780e45f67mr141878385ad.52.1742751460212; Sun, 23 Mar 2025 10:37:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 12/17] target/avr: Handle offset_io in helper.c Date: Sun, 23 Mar 2025 10:37:24 -0700 Message-ID: <20250323173730.3213964-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751719892116600 Content-Type: text/plain; charset="utf-8" Prepare for offset_io being non-zero in do_stb. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/avr/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index 9608e59584..3323f32c22 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -69,7 +69,8 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) =20 static void do_stb(CPUAVRState *env, uint32_t addr, uint8_t data, uintptr_= t ra) { - cpu_stb_mmuidx_ra(env, addr, data, MMU_DATA_IDX, ra); + cpu_stb_mmuidx_ra(env, addr + env_archcpu(env)->offset_io, + data, MMU_DATA_IDX, ra); } =20 void avr_cpu_do_interrupt(CPUState *cs) --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751724; cv=none; d=zohomail.com; s=zohoarc; b=dorQvQbOH5S+t1sdQ8OXGuI9Qz3cY5g7kaORzvzN4OPwvpfDscaVfIxENkKMXUgGAlGnywEPv5LMdlCJWqLGCqIGk787TBSFS3dDeePYJaq3B9iXKaJmG+8ubQH5//ycfUjAc3kGp1XbAvNF/jK/o+o8zjMrKBVj84/vMJbzwE0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742751724; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ewSa7YLsmr/V8RFNcj2I2xqcVJc7xLcAd7Q9LXiEnxw=; b=cm9yI63lDK0zgaCDyHJpoXOgLNGekqozXvDFF0zohiOWBzB36cvgMrTfxRO5/ZodC58RJa5IinEYOTGDHROhO8U5IPhH/39YRjlCjxeAAXOZmLI90RNa2iUHhCe/OpPCI8tXyltaq/8N2z68wwfiiFm3T8ue/de/Ud8jsDq5onc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742751724145931.8743157722237; Sun, 23 Mar 2025 10:42:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1twPGc-0005tR-GP; Sun, 23 Mar 2025 13:37:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1twPGZ-0005rt-P8 for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:43 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1twPGY-0002v7-3k for qemu-devel@nongnu.org; Sun, 23 Mar 2025 13:37:43 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-225fbdfc17dso54026345ad.3 for ; Sun, 23 Mar 2025 10:37:41 -0700 (PDT) Received: from stoup.. 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Sun, 23 Mar 2025 10:37:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 13/17] target/avr: Handle offset_io in avr_cpu_realizefn Date: Sun, 23 Mar 2025 10:37:25 -0700 Message-ID: <20250323173730.3213964-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751725889116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/avr/cpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index e4011004b4..538fcbc215 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -161,12 +161,14 @@ static void avr_cpu_realizefn(DeviceState *dev, Error= **errp) memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, "avr-cpu-reg1", 32); memory_region_add_subregion(get_system_memory(), - OFFSET_DATA, &cpu->cpu_reg1); + OFFSET_DATA + cpu->offset_io, + &cpu->cpu_reg1); =20 memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, "avr-cpu-reg2", 8); memory_region_add_subregion(get_system_memory(), - OFFSET_DATA + 0x58, &cpu->cpu_reg2); + OFFSET_DATA + cpu->offset_io + 0x58, + &cpu->cpu_reg2); } =20 static void avr_cpu_set_int(void *opaque, int irq, int level) --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751461; x=1743356261; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1diLEzRhOjCtwJkuJyBuZiDuZxnU+3/mKXg0OjzXEDE=; b=lX7wCGfpEsGZt0SDiucwxbgAl/ey6bKkgaa+Xkp7x/LyZ+M0qpFTM6EakI6h+CsK87 Gh29RO56w9Cfsb/NzNuEL9q1Elej6J5VcNJL59ezA0xiYRO8DJ0761ekUIceu3vnuorD h/quOwteyNcOkkj22QFKKIz6VOKBi3ls/anh4/IXXsgS4UCupNWEpbay5t2G36q6ERPL 5vU59gv4nXlzy0ex842gMCFg8r3z98Nf7VkF6ZU79tddhfKwc3AYLr+6HRa16NeJaPbK NthD7OKk7ZkzjeLgt5Jjvf5v4pWpl0dPjXqDDcTKqn+FErusosjmV5bCEXJHc6C62ise kYKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751461; x=1743356261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1diLEzRhOjCtwJkuJyBuZiDuZxnU+3/mKXg0OjzXEDE=; b=M06JAkChCff1sV9KTWEFaLdnw0VKyFjtdh2u8gsBBPo4/3HykXZRZXgqDpp2LD/Qrv ufjLsq6H3rm9e1kBDwQ454ZQs+N7oT+nzsGOG4HEHJinTG6qab3H18UhFDqp2gYpNfZK 8ua76uCeAiwUEfvFG+DZbBFnZ7mXgiV/hfpDZLQCi2GZxlcowW8KRmJ3b2m5f6S003Yq bmaqpM+56NZp17k2/6m9di5yfnaYmynjBnemsXR8qEw63nxkSCZkoTn2ljGQH/SnL22K 2ybRt16JvYaFbdAMagbYRv35ubLiFvOF334NHHiKhaagXkPNBl2oa0e0hTCoR5X6yH4l EPiQ== X-Gm-Message-State: AOJu0YxAHJmhev7yH9+rcJWItth8OobyRF0TkXTZgve/izAzkxD+aa4O 0alnzGl/zsgyuOYZ5yQsRggSk1B+Vpu3hvn8sNX7pGh6Z4+b3f2zea5UTdUphdw0AxBJj0fV6o7 B X-Gm-Gg: ASbGncvqyFjJ/HULaSbMQWXtl7304W6z2EspHVssUaASeLBtr3UXvwLo99e+pVd0dQ0 ouwEmIgS/TFwpONdrmiQOA6VENiLBpedyLH5JcrQ/XGAQsREYe26Luzs7cQCPSISr1yYMpxyS4W o1izSfxZyy7QtzRHwdnPxQ5d4eF8HZ0ISBy5aozWS1yXMhxd6zwaUwh4HOxDosCKUsanCzHhkvM PiXA43palHT7fEmrl7tXIxW+Fp1cDAsxVf0DLMT2blrRuU9yfGiIxnjW5oQGe6V0ZufZdJHrg4o /eanvkJPQhYHxtAP8kzgnmyfZUmyX4H+hzPifXC1lpEy6WhDWBw3a5zfQrhGB3t/UcMDmioijW1 c X-Google-Smtp-Source: AGHT+IGW3mvxhvtAAZqftWK9jo4R2yWEsTwtWwCEH163/f+UaXvGCVr2MAqFHX50J63Vs+xNm4VbxQ== X-Received: by 2002:a17:902:c94a:b0:224:93e:b5d7 with SMTP id d9443c01a7336-22780e3fb00mr161436935ad.34.1742751461520; Sun, 23 Mar 2025 10:37:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 14/17] hw/avr: Set offset_io and increase page size to 1k Date: Sun, 23 Mar 2025 10:37:26 -0700 Message-ID: <20250323173730.3213964-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751651344116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu-param.h | 8 +------ hw/avr/atmega.c | 54 ++++++++++++++++++++++++++---------------- 2 files changed, 35 insertions(+), 27 deletions(-) diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 81f3f49ee1..f5248ce9e7 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,13 +21,7 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H =20 -/* - * TARGET_PAGE_BITS cannot be more than 8 bits because - * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and they - * should be implemented as a device and not memory - * 2. SRAM starts at the address 0x0100 - */ -#define TARGET_PAGE_BITS 8 +#define TARGET_PAGE_BITS 10 #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 273582b8af..d4fc9c4aee 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "exec/memory.h" #include "exec/address-spaces.h" +#include "exec/target_page.h" #include "system/system.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" @@ -222,6 +223,7 @@ static void atmega_realize(DeviceState *dev, Error **er= rp) DeviceState *cpudev; SysBusDevice *sbd; char *devname; + uint32_t offset_io, offset_sram; size_t i; =20 assert(mc->io_size <=3D 0x200); @@ -231,13 +233,25 @@ static void atmega_realize(DeviceState *dev, Error **= errp) return; } =20 + /* + * Bias the virtual data section so that the start of RAM is at + * the start of the second page of the physical data section. + * This puts all of the I/O at the end of the first page of the + * physical data section. + */ + offset_io =3D TARGET_PAGE_SIZE - mc->io_size; + offset_sram =3D TARGET_PAGE_SIZE; + /* CPU */ object_initialize_child(OBJECT(dev), "cpu", &s->cpu, mc->cpu_type); =20 object_property_set_uint(OBJECT(&s->cpu), "init-sp", mc->io_size + mc->sram_size - 1, &error_abort= ); object_property_set_uint(OBJECT(&s->cpu), "offset-io", - 0, &error_abort); + offset_io, &error_abort); + + offset_io +=3D OFFSET_DATA; + offset_sram +=3D OFFSET_DATA; =20 qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev =3D DEVICE(&s->cpu); @@ -245,8 +259,7 @@ static void atmega_realize(DeviceState *dev, Error **er= rp) /* SRAM */ memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size, &error_abort); - memory_region_add_subregion(get_system_memory(), - OFFSET_DATA + mc->io_size, &s->sram); + memory_region_add_subregion(get_system_memory(), offset_sram, &s->sram= ); =20 /* Flash */ memory_region_init_rom(&s->flash, OBJECT(dev), @@ -258,13 +271,14 @@ static void atmega_realize(DeviceState *dev, Error **= errp) * * 0x00 - 0x1f: Registers * 0x20 - 0x5f: I/O memory - * 0x60 - 0xff: Extended I/O + * 0x60 - 0x[1]ff: Extended I/O */ s->io =3D qdev_new(TYPE_UNIMPLEMENTED_DEVICE); qdev_prop_set_string(s->io, "name", "I/O"); qdev_prop_set_uint64(s->io, "size", mc->io_size); sysbus_realize_and_unref(SYS_BUS_DEVICE(s->io), &error_fatal); - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->io), 0, OFFSET_DATA, -1234); + + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->io), 0, offset_io, -1234); =20 /* Power Reduction */ for (i =3D 0; i < POWER_MAX; i++) { @@ -277,7 +291,7 @@ static void atmega_realize(DeviceState *dev, Error **er= rp) TYPE_AVR_MASK); sysbus_realize(SYS_BUS_DEVICE(&s->pwr[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwr[i]), 0, - OFFSET_DATA + mc->dev[idx].addr); + offset_io + mc->dev[idx].addr); g_free(devname); } =20 @@ -289,7 +303,7 @@ static void atmega_realize(DeviceState *dev, Error **er= rp) } devname =3D g_strdup_printf("atmega-gpio-%c", 'a' + (char)i); create_unimplemented_device(devname, - OFFSET_DATA + mc->dev[idx].addr, 3); + offset_io + mc->dev[idx].addr, 3); g_free(devname); } =20 @@ -305,7 +319,7 @@ static void atmega_realize(DeviceState *dev, Error **er= rp) qdev_prop_set_chr(DEVICE(&s->usart[i]), "chardev", serial_hd(i)); sbd =3D SYS_BUS_DEVICE(&s->usart[i]); sysbus_realize(sbd, &error_abort); - sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[USART(i)].addr); + sysbus_mmio_map(sbd, 0, offset_io + mc->dev[USART(i)].addr); connect_peripheral_irq(mc, sbd, 0, cpudev, USART_RXC_IRQ(i)); connect_peripheral_irq(mc, sbd, 1, cpudev, USART_DRE_IRQ(i)); connect_peripheral_irq(mc, sbd, 2, cpudev, USART_TXC_IRQ(i)); @@ -321,12 +335,12 @@ static void atmega_realize(DeviceState *dev, Error **= errp) } if (!mc->dev[idx].is_timer16) { create_unimplemented_device("avr-timer8", - OFFSET_DATA + mc->dev[idx].addr, 5= ); + offset_io + mc->dev[idx].addr, 5); create_unimplemented_device("avr-timer8-intmask", - OFFSET_DATA + offset_io + mc->dev[idx].intmask_addr, 1); create_unimplemented_device("avr-timer8-intflag", - OFFSET_DATA + offset_io + mc->dev[idx].intflag_addr, 1); continue; } @@ -337,9 +351,9 @@ static void atmega_realize(DeviceState *dev, Error **er= rp) s->xtal_freq_hz, &error_abort); sbd =3D SYS_BUS_DEVICE(&s->timer[i]); sysbus_realize(sbd, &error_abort); - sysbus_mmio_map(sbd, 0, OFFSET_DATA + mc->dev[idx].addr); - sysbus_mmio_map(sbd, 1, OFFSET_DATA + mc->dev[idx].intmask_addr); - sysbus_mmio_map(sbd, 2, OFFSET_DATA + mc->dev[idx].intflag_addr); + sysbus_mmio_map(sbd, 0, offset_io + mc->dev[idx].addr); + sysbus_mmio_map(sbd, 1, offset_io + mc->dev[idx].intmask_addr); + sysbus_mmio_map(sbd, 2, offset_io + mc->dev[idx].intflag_addr); connect_peripheral_irq(mc, sbd, 0, cpudev, TIMER_CAPT_IRQ(i)); connect_peripheral_irq(mc, sbd, 1, cpudev, TIMER_COMPA_IRQ(i)); connect_peripheral_irq(mc, sbd, 2, cpudev, TIMER_COMPB_IRQ(i)); @@ -349,12 +363,12 @@ static void atmega_realize(DeviceState *dev, Error **= errp) g_free(devname); } =20 - create_unimplemented_device("avr-twi", OFFSET_DATA + 0x0b8, 6= ); - create_unimplemented_device("avr-adc", OFFSET_DATA + 0x078, 8= ); - create_unimplemented_device("avr-ext-mem-ctrl", OFFSET_DATA + 0x074, 2= ); - create_unimplemented_device("avr-watchdog", OFFSET_DATA + 0x060, 1= ); - create_unimplemented_device("avr-spi", OFFSET_DATA + 0x04c, 3= ); - create_unimplemented_device("avr-eeprom", OFFSET_DATA + 0x03f, 3= ); + create_unimplemented_device("avr-twi", offset_io + 0x0b8, 6); + create_unimplemented_device("avr-adc", offset_io + 0x078, 8); + create_unimplemented_device("avr-ext-mem-ctrl", offset_io + 0x074, 2); + create_unimplemented_device("avr-watchdog", offset_io + 0x060, 1); + create_unimplemented_device("avr-spi", offset_io + 0x04c, 3); + create_unimplemented_device("avr-eeprom", offset_io + 0x03f, 3); } =20 static const Property atmega_props[] =3D { --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742751614; cv=none; d=zohomail.com; s=zohoarc; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742751462; x=1743356262; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yV8UPagoDasIkYgoCkaTjilWFltLUaMj7KB+817IG98=; b=Tl3PuUJJnRg3U19qvXlXGVzXUcNoiI3RsMvDS94oQzDP4v1rkkDbpJ9W7lkdD0mCJq qWfekwmMzS4hBRVN1OXIvAHrPk+mhswf+YfnHqqhnXFKRLkioQtuTbvukeDo6pH2zw8F PA8aNX6KiySWi/gtWsyQQs3xUdn1TugKcV7slSRmf8/n+lhsiqc+H/bPghZPWYGaGHC9 yB1Lt/IZ9UGFJXjBYXP/NJdzjrHgG8497dJXZuyyKUEXa2edszSt4N0+6Tp5JSbcdV6H hDl1b9TDMtr/JxFw+69yizr9gBzVgPlbnAltwaj43TyviUriB62f3dvhOSa3KzQFrlJT c4jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742751462; x=1743356262; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yV8UPagoDasIkYgoCkaTjilWFltLUaMj7KB+817IG98=; b=XWqtfwi+AIWPSq72mMqAPlkzrE1TUsIsm3MnYWhZjOK+Ds6DOuKrfesJh1zlZU/VO8 4PMvTfnDEuoJ9Z3RY55zVXrpCbPIprlbIPhgCAXwT07wADj79y0sEuGiDDwEMtMEhMPQ djeDpuvj6Me9pf8KJfHI16C6er+AMS88vT3J8zZLl/413XStxwhMGODAMNGkj8oNOSzS fGRBWLe9llQLeD0L3zu0S3eqAK3aYGOG/y5f0QTMlENLhaLf/Jn7q0X4CIa1GQ3CYMb3 GPLwYUvaGi/zDkFbOuibKbNAQlcd4hgvzIiC+QR7nl5337Oru6alcSfqawq2Pr9ww4qw 0kSA== X-Gm-Message-State: AOJu0YxcBZzCyoHcsAO3V9CPE47GpXkUARV9ee1MPbu1aD9mNEtdvoBc NnMftLppBNmal/Q7pWh4hcmjHwyjgfA8s/Y1EsH5C9VBzROgKkAsrfVhAIvcrG/fL154u5NQz7f U X-Gm-Gg: ASbGncsuwHC8/k6c80elYmHcC+xtq4rugg/iWOPMLOrEY7W5emwgW5URGKe9PUox4Fq WF/JzdqX5+uBkXibxDkd52MT8UKsoOTzHl9xtgsmLL9IS1edNjcu5TsIiGjLHMfSVdD/KXfCaQ0 WqOTyOEwmhjpnbifGc174x5sy1LpwkOlqlxHqRDxPpPYG3RjJX/AcHcxaDQOwscgVXktnv49x+j pVZz240RKvOlTMhOad5zM+8ZrPgZD4IcBN/sv27ZMITw3XdebOBnLeNHQ4X9ct5A+Ua/+CVyr3O AqnCsn3viR9OvB1KR0gv08F6fD82A3C6hCrkTzv4NDSYlcNioIW1vqXmke0C+Jxxk93CDuWAp1X c X-Google-Smtp-Source: AGHT+IE9oDlQco/2y1TGo8E15QrNuI5/Mx2hOuD4VZZ3dLMJinx76SxGrg2+fqvGdftllnWFWiucxg== X-Received: by 2002:a17:902:f642:b0:21d:3bd7:afdd with SMTP id d9443c01a7336-22780ba18cdmr166709665ad.0.1742751462263; Sun, 23 Mar 2025 10:37:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 15/17] hw/avr: Pass mcu_type to class_base_init via .class_data Date: Sun, 23 Mar 2025 10:37:27 -0700 Message-ID: <20250323173730.3213964-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751616928116600 Content-Type: text/plain; charset="utf-8" We want to be able to do more common work on MachineClass. Pass the class name as a string in .class_data. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/avr/arduino.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c index 48ef478346..29cb776848 100644 --- a/hw/avr/arduino.c +++ b/hw/avr/arduino.c @@ -69,6 +69,13 @@ static void arduino_machine_class_init(ObjectClass *oc, = void *data) mc->no_parallel =3D 1; } =20 +static void arduino_machine_class_base_init(ObjectClass *oc, void *data) +{ + ArduinoMachineClass *amc =3D ARDUINO_MACHINE_CLASS(oc); + + amc->mcu_type =3D data; +} + static void arduino_duemilanove_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -80,7 +87,6 @@ static void arduino_duemilanove_class_init(ObjectClass *o= c, void *data) */ mc->desc =3D "Arduino Duemilanove (ATmega168)", mc->alias =3D "2009"; - amc->mcu_type =3D TYPE_ATMEGA168_MCU; amc->xtal_hz =3D 16 * 1000 * 1000; }; =20 @@ -95,7 +101,6 @@ static void arduino_uno_class_init(ObjectClass *oc, void= *data) */ mc->desc =3D "Arduino UNO (ATmega328P)"; mc->alias =3D "uno"; - amc->mcu_type =3D TYPE_ATMEGA328_MCU; amc->xtal_hz =3D 16 * 1000 * 1000; }; =20 @@ -110,7 +115,6 @@ static void arduino_mega_class_init(ObjectClass *oc, vo= id *data) */ mc->desc =3D "Arduino Mega (ATmega1280)"; mc->alias =3D "mega"; - amc->mcu_type =3D TYPE_ATMEGA1280_MCU; amc->xtal_hz =3D 16 * 1000 * 1000; }; =20 @@ -125,7 +129,6 @@ static void arduino_mega2560_class_init(ObjectClass *oc= , void *data) */ mc->desc =3D "Arduino Mega 2560 (ATmega2560)"; mc->alias =3D "mega2560"; - amc->mcu_type =3D TYPE_ATMEGA2560_MCU; amc->xtal_hz =3D 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */ }; =20 @@ -134,24 +137,29 @@ static const TypeInfo arduino_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("arduino-duemilanove"), .parent =3D TYPE_ARDUINO_MACHINE, .class_init =3D arduino_duemilanove_class_init, + .class_data =3D (void *)TYPE_ATMEGA168_MCU, }, { .name =3D MACHINE_TYPE_NAME("arduino-uno"), .parent =3D TYPE_ARDUINO_MACHINE, .class_init =3D arduino_uno_class_init, + .class_data =3D (void *)TYPE_ATMEGA328_MCU, }, { .name =3D MACHINE_TYPE_NAME("arduino-mega"), .parent =3D TYPE_ARDUINO_MACHINE, .class_init =3D arduino_mega_class_init, + .class_data =3D (void *)TYPE_ATMEGA1280_MCU, }, { .name =3D MACHINE_TYPE_NAME("arduino-mega-2560-v3"), .parent =3D TYPE_ARDUINO_MACHINE, .class_init =3D arduino_mega2560_class_init, + .class_data =3D (void *)TYPE_ATMEGA2560_MCU, }, { .name =3D TYPE_ARDUINO_MACHINE, .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(ArduinoMachineState), .class_size =3D sizeof(ArduinoMachineClass), .class_init =3D arduino_machine_class_init, + .class_base_init =3D arduino_machine_class_base_init, .abstract =3D true, } }; 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Sun, 23 Mar 2025 10:37:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 16/17] hw/avr: Move AtmegaMcuClass to atmega.h Date: Sun, 23 Mar 2025 10:37:28 -0700 Message-ID: <20250323173730.3213964-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250323173730.3213964-1-richard.henderson@linaro.org> References: <20250323173730.3213964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742751620951116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- hw/avr/atmega.h | 20 ++++++++++++++++++++ hw/avr/atmega.c | 22 +--------------------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h index a99ee15c7e..f031e6c10a 100644 --- a/hw/avr/atmega.h +++ b/hw/avr/atmega.h @@ -23,6 +23,10 @@ #define TYPE_ATMEGA1280_MCU "ATmega1280" #define TYPE_ATMEGA2560_MCU "ATmega2560" =20 +typedef struct AtmegaMcuClass AtmegaMcuClass; +DECLARE_CLASS_CHECKERS(AtmegaMcuClass, ATMEGA_MCU, + TYPE_ATMEGA_MCU) + typedef struct AtmegaMcuState AtmegaMcuState; DECLARE_INSTANCE_CHECKER(AtmegaMcuState, ATMEGA_MCU, TYPE_ATMEGA_MCU) @@ -32,6 +36,22 @@ DECLARE_INSTANCE_CHECKER(AtmegaMcuState, ATMEGA_MCU, #define TIMER_MAX 6 #define GPIO_MAX 12 =20 +struct AtmegaMcuClass { + /*< private >*/ + SysBusDeviceClass parent_class; + /*< public >*/ + const char *uc_name; + const char *cpu_type; + size_t flash_size; + size_t eeprom_size; + size_t sram_size; + size_t io_size; + size_t gpio_count; + size_t adc_count; + const uint8_t *irq; + const struct peripheral_cfg *dev; +}; + struct AtmegaMcuState { /*< private >*/ SysBusDevice parent_obj; diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index d4fc9c4aee..96e36743bc 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -36,7 +36,7 @@ enum AtmegaPeripheral { #define TIMER(n) (n + TIMER0) #define POWER(n) (n + POWER0) =20 -typedef struct { +typedef struct peripheral_cfg { uint16_t addr; enum AtmegaPeripheral power_index; uint8_t power_bit; @@ -46,26 +46,6 @@ typedef struct { bool is_timer16; } peripheral_cfg; =20 -struct AtmegaMcuClass { - /*< private >*/ - SysBusDeviceClass parent_class; - /*< public >*/ - const char *uc_name; - const char *cpu_type; - size_t flash_size; - size_t eeprom_size; - size_t sram_size; - size_t io_size; - size_t gpio_count; - size_t adc_count; - const uint8_t *irq; - const peripheral_cfg *dev; -}; -typedef struct AtmegaMcuClass AtmegaMcuClass; - -DECLARE_CLASS_CHECKERS(AtmegaMcuClass, ATMEGA_MCU, - TYPE_ATMEGA_MCU) - static const peripheral_cfg dev168_328[PERIFMAX] =3D { [USART0] =3D { 0xc0, POWER0, 1 }, [TIMER2] =3D { 0xb0, POWER0, 6, 0x70, 0x37, false }, --=20 2.43.0 From nobody Tue Apr 1 08:41:19 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Select the page size based on the size of sram. This leaves sram on exactly one page and minimizes the number of pages required to span the flash. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu-param.h | 11 +++++++++-- hw/avr/arduino.c | 15 +++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f5248ce9e7..a18bf39bb9 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,8 +21,15 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H =20 -#define TARGET_PAGE_BITS 10 -#define TARGET_PHYS_ADDR_SPACE_BITS 24 +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 10 + +/* + * The real value for TARGET_PHYS_ADDR_SPACE_BITS is 24, but selecting + * an overly small value will assert in tb-maint.c when selecting the + * shape of the page_table tree. This allows an 8k page size. + */ +#define TARGET_PHYS_ADDR_SPACE_BITS 28 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 #define TCG_GUEST_DEFAULT_MO 0 diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c index 29cb776848..f309aa5597 100644 --- a/hw/avr/arduino.c +++ b/hw/avr/arduino.c @@ -71,9 +71,24 @@ static void arduino_machine_class_init(ObjectClass *oc, = void *data) =20 static void arduino_machine_class_base_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); ArduinoMachineClass *amc =3D ARDUINO_MACHINE_CLASS(oc); + AtmegaMcuClass *acc; + int page_bits; =20 amc->mcu_type =3D data; + + /* Find the mcu class that we will instantiate. */ + acc =3D ATMEGA_MCU_CLASS(object_class_by_name(amc->mcu_type)); + + /* + * Select a page size based on the size of sram. + * This will result in a page size between 1k and 8k + * and minimize the number of pages to span flash. + */ + page_bits =3D ctz32(acc->sram_size); + assert(page_bits >=3D TARGET_PAGE_BITS_MIN && page_bits <=3D 13); + mc->minimum_page_bits =3D page_bits; } =20 static void arduino_duemilanove_class_init(ObjectClass *oc, void *data) --=20 2.43.0