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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9b5b8dsm3042786f8f.59.2025.03.21.11.16.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 21 Mar 2025 11:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742580977; x=1743185777; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JOCpET3EdD3I12B9WLSxV6AoEDFAj5uepUX92kpSCz4=; b=l2GEYY7F8AYhetnBCzMZNQsgjB6cQ+aUHupYBPKgJmWkEGNHttSyBxgGpRyYwDBhLw sA2L7FUOzZreb9ew6VOUN9922c1tpd+st9s5+yb6qOFwB4n84NCfFvc0M/s2HGbJ7JFP h55IrRBw4kLdJlVqSMF39T3bsVhIdYbYo2CJGvsbec6nr1obkOT7mN8XwLzaCDEUF1JB 523YMm7kdEGiliDLRZcjvsP6AdR7ggTfIDuZCVq2t2vfKDFrbeW8t6EtLju7BJg4GE4i 6DFywKJ4scBEGaZydAzAph4Qlr4QW8Y7TuxsIpeWIeX4IhU07vKXly+p45RLV63+ME/O 8lCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742580977; x=1743185777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JOCpET3EdD3I12B9WLSxV6AoEDFAj5uepUX92kpSCz4=; b=rwcShTjNgoppBQrCldUO8OYpTMQuAvCdXWB/GNs+7pOwM/QhkMV84LrJ2wPjSQFUbt cOMzWID2OB3I+F8Mvms68y8uFzjQL+WFoTBu2T8+evxHtFLFBUOjecfMTdpWNk7jvASo GEo6vqgtqKudB70b+kfaYCwaAi94W9NCNFkNBn84DppRQau/MWek/N1BA/r7aNoEL6PS ky20VvK8VlMcQR5qFewgxeSCi4x1RUbO5/rwsxPHhQ6Ayv5VNE6fitxsn2PkFAah0E1G fVy+UwBl8/bj1UbURYvV6tYyLX4NHjrWD1fTWM+JNg6jLzngujpqp8km5fbUu4h5wE8C QB0A== X-Gm-Message-State: AOJu0YyAW9fWzqdT57lVS+2LKwRx1ZA6zCeewajRCdXkxzdfqIwJsI/J blZHppNfW1Ajvj/g1Dl0ywgOkKKYbnNOa8EV3k642ojNb4ATINE5r49vpn3AvpMGY2kO/+wzTME s X-Gm-Gg: ASbGncu7QK85lhXTF82mBMLegYQfhn0VFkHixNNgJo/8N+kJ0I5ZYDoFSwFTF+oO/mF qvpswsxr77hFzWkrOyBI8TKkRAw6AMzAbheKHUSyFxs6+hYnZOsdykOND70QvmvOyOIr4s6bLoW L5AJuUMKuFfxtWGdadfXoTZWREX/Vx6nyg/vYR//pKGW1R3JJjuCJdGuQhsL6VfavsDrfb7CT+v 6Sg5T1t7qL9Ln/ciwrc7Zq9JWbzLvYVdphbAr7h8NkkmWZ89rEZ+uGV9DD/6ZfOOPZL7KEJEWz1 Vyvj7x5abwezzF4bpKk+393VJz4sK/efPkJlaYzPc78SxOcaFglMy0QMapZaZeXfxmg57DtcoK+ UK/qZYkwLH8jbsWdaeRk= X-Google-Smtp-Source: AGHT+IGXUKUy7FOnzDFtwHOvPokcEjY9gUA/07C+0fs8Y1LazF886mUln5h/wl5ZTR7SbHxy7yswHA== X-Received: by 2002:a05:6000:21c2:b0:399:6d53:68d9 with SMTP id ffacd0b85a97d-3997f939949mr3205803f8f.38.1742580976682; Fri, 21 Mar 2025 11:16:16 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Cc: Paolo Bonzini , Pierrick Bouvier , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Anton Johansson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH-for-10.1 v2 5/7] tcg: Propagate CPUState argument to cpu_req_mo() Date: Fri, 21 Mar 2025 19:15:47 +0100 Message-ID: <20250321181549.3331-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250321181549.3331-1-philmd@linaro.org> References: <20250321181549.3331-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742581079838019000 In preparation of having tcg_req_mo() access CPUState in the next commit, pass it to cpu_req_mo(), its single caller. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/internal-target.h | 3 ++- accel/tcg/cputlb.c | 20 ++++++++++---------- accel/tcg/user-exec.c | 20 ++++++++++---------- 3 files changed, 22 insertions(+), 21 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 1cb35dba99e..992362be7e6 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -57,12 +57,13 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); =20 /** * cpu_req_mo: + * @cpu: CPUState * @type: TCGBar * * If tcg_req_mo indicates a barrier for @type is required * for the guest memory model, issue a host memory barrier. */ -#define cpu_req_mo(type) \ +#define cpu_req_mo(cpu, type) \ do { \ if (tcg_req_mo(type)) { \ smp_mb(); \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index fb22048876e..b6713efdb81 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2321,7 +2321,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); tcg_debug_assert(!crosspage); =20 @@ -2336,7 +2336,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2360,7 +2360,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint32_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2381,7 +2381,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint64_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2404,7 +2404,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, Int128 ret; int first; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { @@ -2732,7 +2732,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); tcg_debug_assert(!crosspage); =20 @@ -2746,7 +2746,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, bool crosspage; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2768,7 +2768,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2789,7 +2789,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2812,7 +2812,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, uint64_t a, b; int first; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 2322181b151..5bda8fb5514 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1059,7 +1059,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, void *haddr; uint8_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, access_type); ret =3D ldub_p(haddr); clear_helper_retaddr(); @@ -1073,7 +1073,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_2(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1091,7 +1091,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint32_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_4(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1109,7 +1109,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint64_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_8(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1128,7 +1128,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr, MemOp mop =3D get_memop(oi); =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_LOAD); ret =3D load_atom_16(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1144,7 +1144,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, { void *haddr; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, MMU_DATA_STORE); stb_p(haddr, val); clear_helper_retaddr(); @@ -1156,7 +1156,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1172,7 +1172,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1188,7 +1188,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1204,7 +1204,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, void *haddr; MemOpIdx mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { --=20 2.47.1