From nobody Wed Apr 2 14:30:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549478; cv=none; d=zohomail.com; s=zohoarc; b=D1fFgWnHiR8t+EzVg73PQ3HY4BPB+sIQebyX+iGEALXrn6kQE1joA/gQLTrg3/VUQJy7gnbYzT+W+lfKDdRPWRLj36/fWGw5NglExSqNscyaw72M4hJFytLKfz+0cvh8ABRW9CgkCMK+J7XHMWSK/NPBL6Dk6G0PWk8yAP8hx5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549478; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=RQTnYq57e1TcnXjDuq5PW3lJbkd9JhDCJdHQpokdz80=; b=e7HqfAaMLYykiurPqVrNDejWqevnCcSLAZRD4FR79sKrVQyJBp6fNKjv0/x/Ux1eg0Kodoklq9y2ZYbzfizaMK8xPaKObk9DkR1u4q0H4LhZb/CjrK+wcRkWEzNdQCUIapnPrQOGGP52DX1QUe5HlG5H6kpShvuWgDgGyYhIR5o= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174254947883313.058941984408989; Fri, 21 Mar 2025 02:31:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYfr-0001ht-BT; Fri, 21 Mar 2025 05:28:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYfk-0001M5-Nu; Fri, 21 Mar 2025 05:28:13 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYfh-0005jH-P2; Fri, 21 Mar 2025 05:28:12 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:30 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:30 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 20/22] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Date: Fri, 21 Mar 2025 17:26:16 +0800 Message-ID: <20250321092623.2097234-21-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549480480019000 Content-Type: text/plain; charset="utf-8" Added "src_hi" and "dest_hi" fields to "AspeedMasks" for 64-bit addresses t= est. Updated "aspeed_test_addresses" to validate "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI". Ensured correct masking of 64-bit addresses by checking both lower and upper 32-bit registers. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- tests/qtest/aspeed-hace-utils.h | 2 ++ tests/qtest/aspeed-hace-utils.c | 15 ++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index d8684d3f83..de8055a1db 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -51,6 +51,8 @@ struct AspeedMasks { uint32_t src; uint32_t dest; uint32_t len; + uint32_t src_hi; + uint32_t dest_hi; }; =20 void aspeed_test_md5(const char *machine, const uint32_t base, diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 8d9c464f72..fc209353f3 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -588,30 +588,43 @@ void aspeed_test_addresses(const char *machine, const= uint32_t base, */ g_assert_cmphex(qtest_readl(s, base + HACE_CMD), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 - /* Check that the address masking is correct */ qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, expected= ->src); =20 + qtest_writel(s, base + HACE_HASH_SRC_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), + =3D=3D, expected->src_hi); + qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, expected->dest); =20 + qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, + expected->dest_hi); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, expected->len); =20 /* Reset to zero */ qtest_writel(s, base + HACE_HASH_SRC, 0); + qtest_writel(s, base + HACE_HASH_SRC_HI, 0); qtest_writel(s, base + HACE_HASH_DIGEST, 0); + qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0); qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); =20 /* Check that all bits are now zero */ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 qtest_quit(s); --=20 2.43.0