From nobody Wed Apr 2 14:30:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549463; cv=none; d=zohomail.com; s=zohoarc; b=EDjPdMwJr3if0nfZxUqWCKb68MdLS4/26ZAlxmY0NouDXD7yUbnOzWFB15pExPEe16Vlg76EOZjfyzaSllW2XXBhU0zDBpB4MRgF2ZFGnrhymDkV/FVT9Ru3TfSbqpDp4MxBBHgMQI04GEwX7WUHG0upofspKw5+/ko34u4o2Ps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549463; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ue5BEwpzBa6QOnWJbqXrv2dCki1jrKRmbOGKO/ey/2Y=; b=hRBVxZTKdYcsLTzwsamdSZA/Hr1x9EFfyjTH5y3kHqT3CAsvf2QlGkhnpw33+jwtSU3UeyBXbRZNU9sJHyRAYn3jC1nxdxxzNiCNkx7M9eUs7gJ/KvQhfFQtJhltgC4T/rB0LnfVxXGs0CfsYBHAt/Cx02q6LclgAEYXdvvFFto= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742549463872874.1963794207085; Fri, 21 Mar 2025 02:31:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYfc-0000q6-Bb; Fri, 21 Mar 2025 05:28:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYfa-0000gl-KN; Fri, 21 Mar 2025 05:28:02 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYfY-0005EC-Hd; Fri, 21 Mar 2025 05:28:02 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:30 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:30 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 18/22] test/qtest/hace: Update source data and digest data type to 64-bit Date: Fri, 21 Mar 2025 17:26:14 +0800 Message-ID: <20250321092623.2097234-19-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549465862019100 Content-Type: text/plain; charset="utf-8" Currently, the hash data source and digest result buffer addresses are set = to 32-bit. However, the AST2700 CPU is a 64-bit Cortex-A35 architecture, and i= ts DRAM base address is also 64-bit. To support AST2700, update the hash data source address and digest result b= uffer address to use 64-bit addressing. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 20 +++---- tests/qtest/aspeed-hace-utils.c | 96 ++++++++++++++++----------------- 2 files changed, 58 insertions(+), 58 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index f4440561de..0382570fa2 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -51,25 +51,25 @@ struct AspeedMasks { }; =20 void aspeed_test_md5(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha256(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha384(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha512(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha256_sg(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha384_sg(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha512_sg(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha256_accum(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha384_accum(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha512_accum(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_addresses(const char *machine, const uint32_t base, const struct AspeedMasks *expected); =20 diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index d3146898c2..f39bb8ea48 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -153,22 +153,22 @@ static const uint8_t test_result_accum_sha256[] =3D { 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; =20 -static void write_regs(QTestState *s, uint32_t base, uint32_t src, - uint32_t length, uint32_t out, uint32_t method) +static void write_regs(QTestState *s, uint32_t base, uint64_t src, + uint32_t length, uint64_t out, uint32_t method) { - qtest_writel(s, base + HACE_HASH_SRC, src); - qtest_writel(s, base + HACE_HASH_DIGEST, out); + qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32)); + qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0, 32)); qtest_writel(s, base + HACE_HASH_DATA_LEN, length); qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); } =20 void aspeed_test_md5(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) =20 { QTestState *s =3D qtest_init(machine); =20 - uint32_t digest_addr =3D src_addr + 0x010000; + uint64_t digest_addr =3D src_addr + 0x010000; uint8_t digest[16] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -198,11 +198,11 @@ void aspeed_test_md5(const char *machine, const uint3= 2_t base, } =20 void aspeed_test_sha256(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x10000; uint8_t digest[32] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -232,11 +232,11 @@ void aspeed_test_sha256(const char *machine, const ui= nt32_t base, } =20 void aspeed_test_sha384(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x10000; uint8_t digest[32] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -266,11 +266,11 @@ void aspeed_test_sha384(const char *machine, const ui= nt32_t base, } =20 void aspeed_test_sha512(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x10000; uint8_t digest[64] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -300,22 +300,22 @@ void aspeed_test_sha512(const char *machine, const ui= nt32_t base, } =20 void aspeed_test_sha256_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x10000; - const uint32_t src_addr_2 =3D src_addr + 0x20000; - const uint32_t src_addr_3 =3D src_addr + 0x30000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t src_addr_1 =3D src_addr + 0x10000; + const uint64_t src_addr_2 =3D src_addr + 0x20000; + const uint64_t src_addr_3 =3D src_addr + 0x30000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, + cpu_to_le64(src_addr_1) }, { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, + cpu_to_le64(src_addr_2) }, { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, + cpu_to_le64(src_addr_3) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -351,22 +351,22 @@ void aspeed_test_sha256_sg(const char *machine, const= uint32_t base, } =20 void aspeed_test_sha384_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x10000; - const uint32_t src_addr_2 =3D src_addr + 0x20000; - const uint32_t src_addr_3 =3D src_addr + 0x30000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t src_addr_1 =3D src_addr + 0x10000; + const uint64_t src_addr_2 =3D src_addr + 0x20000; + const uint64_t src_addr_3 =3D src_addr + 0x30000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, + cpu_to_le64(src_addr_1) }, { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, + cpu_to_le64(src_addr_2) }, { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, + cpu_to_le64(src_addr_3) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -402,22 +402,22 @@ void aspeed_test_sha384_sg(const char *machine, const= uint32_t base, } =20 void aspeed_test_sha512_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x10000; - const uint32_t src_addr_2 =3D src_addr + 0x20000; - const uint32_t src_addr_3 =3D src_addr + 0x30000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t src_addr_1 =3D src_addr + 0x10000; + const uint64_t src_addr_2 =3D src_addr + 0x20000; + const uint64_t src_addr_3 =3D src_addr + 0x30000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, + cpu_to_le64(src_addr_1) }, { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, + cpu_to_le64(src_addr_2) }, { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, + cpu_to_le64(src_addr_3) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -453,16 +453,16 @@ void aspeed_test_sha512_sg(const char *machine, const= uint32_t base, } =20 void aspeed_test_sha256_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x10000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t buffer_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, + cpu_to_le64(buffer_addr) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -494,16 +494,16 @@ void aspeed_test_sha256_accum(const char *machine, co= nst uint32_t base, } =20 void aspeed_test_sha384_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x10000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t buffer_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_384) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, + cpu_to_le64(buffer_addr) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -535,16 +535,16 @@ void aspeed_test_sha384_accum(const char *machine, co= nst uint32_t base, } =20 void aspeed_test_sha512_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x10000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t buffer_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, + cpu_to_le64(buffer_addr) }, }; =20 /* Check engine is idle, no busy or irq bits set */ --=20 2.43.0