From nobody Wed Apr 2 14:25:06 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549385; cv=none; d=zohomail.com; s=zohoarc; b=gHIo53tqLS3rQ+6DwD/2SiGp5SOBpFdFf703yJug/BSzdo4TeyxrMezpDNHpYN0XLWj+9ubSX/r1AzYFf4SBDorm/GFZlWKmdOJ+dpJx0hzk+F8K8Y+dCJK8iU+XKyzkbqt+szQORysXsL/j9+CcDFD56lnspBiuIfXnAh0GgyA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549385; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=mmD/hTDTVJl2Hr2T1lzXVYz+zCt4j+rrSoLPK7sKlzU=; b=IGH73ugTRpzZt5Fml7sb6zgzWqHk/tNESI5hm/h8T4Qg5VloB/On9U6d0rEZlFXM6rL45GZhqjTp61kZK8AaPrUQ5x8xYbga72zr0JDP3izydjNIzAhAZ7bRJKe+ikRsNMz+cIjdEUGurJJSuOKrlpWLd9jrL8WNIjQ9jGoooD8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742549385909578.3109323787526; Fri, 21 Mar 2025 02:29:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYeb-0006aH-NL; Fri, 21 Mar 2025 05:27:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeR-0006T7-Sf; Fri, 21 Mar 2025 05:26:51 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeP-00056F-Ed; Fri, 21 Mar 2025 05:26:51 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:26 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:26 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 09/22] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Date: Fri, 21 Mar 2025 17:26:05 +0800 Message-ID: <20250321092623.2097234-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549387471019000 Content-Type: text/plain; charset="utf-8" Currently, if the program encounters an unsupported algorithm, it does not = set the HASH_IRQ bit in the status register and send an interrupt to indicate command completion. As a result, the FW gets stuck waiting for a completion signal from the HACE module. Additionally, in do_hash_operation, if an error occurs within the condition= al statement, the HASH_IRQ bit is not set in the status register. This causes = the firmware to continuously send HASH commands, as it is unaware that the HACE model has completed processing the command. To fix this, the HASH_IRQ bit in the status register must always be set to ensure that the firmware receives an interrupt from the HACE module, preven= ting it from getting stuck or repeatedly sending HASH commands. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_hace.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 8f333fc97e..d4f653670e 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -311,12 +311,6 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, iov[i - 1].iov_len, false, iov[i - 1].iov_len); } - - /* - * Set status bits to indicate completion. Testing shows hardware sets - * these irrespective of HASH_IRQ_EN. - */ - s->regs[R_STATUS] |=3D HASH_IRQ; } =20 static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int s= ize) @@ -400,10 +394,16 @@ static void aspeed_hace_write(void *opaque, hwaddr ad= dr, uint64_t data, qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid hash algorithm selection 0x%"PRIx64"\= n", __func__, data & ahc->hash_mask); - break; + } else { + do_hash_operation(s, algo, data & HASH_SG_EN, + ((data & HASH_HMAC_MASK) =3D=3D HASH_DIGEST_ACCUM)); } - do_hash_operation(s, algo, data & HASH_SG_EN, - ((data & HASH_HMAC_MASK) =3D=3D HASH_DIGEST_ACCUM)); + + /* + * Set status bits to indicate completion. Testing shows hardware = sets + * these irrespective of HASH_IRQ_EN. + */ + s->regs[R_STATUS] |=3D HASH_IRQ; =20 if (data & HASH_IRQ_EN) { qemu_irq_raise(s->irq); --=20 2.43.0