From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549215; cv=none; d=zohomail.com; s=zohoarc; b=dwfTUrrH70YfYRaktVb28/WxBjly80ZB+G5jKl/KJS4A5VjSjU9JRHFFGYlGLR9xSRNP7WLf4nvs5vlO2tRhhQt3HS5xE8LeV0cZ5cnZokTjG4H8S8+1hsNJfSBSeW9yWSl2siNCYTCnbtJFfx/rGglOjRCa+MY+EwMoy8dmiwY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549215; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=1TpNJYBcRLkN193LTkREhVc4u5EDV2mxw0Hk041GZDo=; b=kZJm3smhGcLffiE+8aEt/964mPVm3dImrDx89IfmdlZBkkouz/6DQKK4FK1qE8xUk13+j+mHNIvuL3Of0pyPlx1NDRaT6uW0cWJs+HMocBfWUck84Rwfdz17hd6/MHfKyCOzKOsv8Nf/xNRlhy8RFYpUzFCmJ3QaEb4MWDkU3zg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174254921584253.05508331233557; Fri, 21 Mar 2025 02:26:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYeN-0006NG-RR; Fri, 21 Mar 2025 05:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeG-0006EC-3I; Fri, 21 Mar 2025 05:26:40 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeE-00056m-93; Fri, 21 Mar 2025 05:26:39 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:24 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:24 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 01/22] hw/misc/aspeed_hace: Remove unused code for better readability Date: Fri, 21 Mar 2025 17:25:57 +0800 Message-ID: <20250321092623.2097234-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549218627019100 Content-Type: text/plain; charset="utf-8" This cleanup follows significant changes in commit 4c1d0af4a28d, making the model more readable. - Deleted "iov_cache" and "iov_count" from "AspeedHACEState". - Removed "reconstruct_iov" function and related logic. - Simplified "do_hash_operation" by eliminating redundant checks. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 2 -- hw/misc/aspeed_hace.c | 35 ----------------------------------- 2 files changed, 37 deletions(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index 5d4aa19cfe..b69a038d35 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -31,10 +31,8 @@ struct AspeedHACEState { MemoryRegion iomem; qemu_irq irq; =20 - struct iovec iov_cache[ASPEED_HACE_MAX_SG]; uint32_t regs[ASPEED_HACE_NR_REGS]; uint32_t total_req_len; - uint32_t iov_count; =20 MemoryRegion *dram_mr; AddressSpace dram_as; diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 32a5dbded3..8e7e8113a5 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -137,25 +137,6 @@ static bool has_padding(AspeedHACEState *s, struct iov= ec *iov, return false; } =20 -static int reconstruct_iov(AspeedHACEState *s, struct iovec *iov, int id, - uint32_t *pad_offset) -{ - int i, iov_count; - if (*pad_offset !=3D 0) { - s->iov_cache[s->iov_count].iov_base =3D iov[id].iov_base; - s->iov_cache[s->iov_count].iov_len =3D *pad_offset; - ++s->iov_count; - } - for (i =3D 0; i < s->iov_count; i++) { - iov[i].iov_base =3D s->iov_cache[i].iov_base; - iov[i].iov_len =3D s->iov_cache[i].iov_len; - } - iov_count =3D s->iov_count; - s->iov_count =3D 0; - s->total_req_len =3D 0; - return iov_count; -} - static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, bool acc_mode) { @@ -237,19 +218,6 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, iov[0].iov_base =3D haddr; iov[0].iov_len =3D len; i =3D 1; - - if (s->iov_count) { - /* - * In aspeed sdk kernel driver, sg_mode is disabled in hash_fi= nal(). - * Thus if we received a request with sg_mode disabled, it is - * required to check whether cache is empty. If no, we should - * combine cached iov and the current iov. - */ - s->total_req_len +=3D len; - if (has_padding(s, iov, len, &total_msg_len, &pad_offset)) { - i =3D reconstruct_iov(s, iov, 0, &pad_offset); - } - } } =20 if (acc_mode) { @@ -273,7 +241,6 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, qcrypto_hash_free(s->hash_ctx); =20 s->hash_ctx =3D NULL; - s->iov_count =3D 0; s->total_req_len =3D 0; } } else if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, @@ -432,7 +399,6 @@ static void aspeed_hace_reset(DeviceState *dev) } =20 memset(s->regs, 0, sizeof(s->regs)); - s->iov_count =3D 0; s->total_req_len =3D 0; } =20 @@ -469,7 +435,6 @@ static const VMStateDescription vmstate_aspeed_hace =3D= { .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS), VMSTATE_UINT32(total_req_len, AspeedHACEState), - VMSTATE_UINT32(iov_count, AspeedHACEState), VMSTATE_END_OF_LIST(), } }; --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549230; cv=none; d=zohomail.com; s=zohoarc; b=ftiwm3dUyOXn0YWD3ZBECpGD1IUMFaNztl+ci7NN+5/1mAYcn4BKJXZ+BDukyTi69AHkoggnJxHUoLr1VY5AToF+yEI4b0I/yz5q2B9Z3h41djsyBAHjozSDA7qG2XSLnuwBe3tKwqIZZ44rY7dft41yGCQBBrg5HR27Ghqhmzc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549230; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=lS3FkQ2VqpT1/sWjVFenG4tgwxR2XSSMyU72uOLfBMY=; b=mn34z6fPmVR+NFBYWLfU0fTJVR59SH6R+5RzigV+N5bVwFEQtnUJj9AnbIJbGtfJv8uyB+ucST3PkanHe85x7wbc1QVV/lE60rQXzRFolX/IXdslxz8Zdxc5cnFxh+D8igZAf6R+1ATDiBWlpEuz/A77Uxg87Q4w+CMvp6SQPR4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742549230077542.4430659694277; Fri, 21 Mar 2025 02:27:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYeK-0006Ju-U7; Fri, 21 Mar 2025 05:26:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeF-0006Dv-TD; Fri, 21 Mar 2025 05:26:39 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeD-00056F-Rp; Fri, 21 Mar 2025 05:26:39 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:24 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:24 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 02/22] hw/misc/aspeed_hace: Fix buffer overflow in has_padding function Date: Fri, 21 Mar 2025 17:25:58 +0800 Message-ID: <20250321092623.2097234-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549231345019000 Content-Type: text/plain; charset="utf-8" The maximum padding size is either 64 or 128 bytes and should always be sma= ller than "req_len". If "padding_size" exceeds "req_len", then "req_len - padding_size" underflows due to "uint32_t" data type, leading to= a large incorrect value (e.g., `0xFFXXXXXX`). This causes an out-of-bounds me= mory access, potentially leading to a buffer overflow. Added a check to ensure "padding_size" does not exceed "req_len" before computing "pad_offset". This prevents "req_len - padding_size" from underfl= owing and avoids accessing invalid memory. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_hace.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 8e7e8113a5..d8b5f048bb 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -128,6 +128,11 @@ static bool has_padding(AspeedHACEState *s, struct iov= ec *iov, if (*total_msg_len <=3D s->total_req_len) { uint32_t padding_size =3D s->total_req_len - *total_msg_len; uint8_t *padding =3D iov->iov_base; + + if (padding_size > req_len) { + return false; + } + *pad_offset =3D req_len - padding_size; if (padding[*pad_offset] =3D=3D 0x80) { return true; --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549240; cv=none; d=zohomail.com; s=zohoarc; b=TL6W8md3OJTNPDr1RYH3u92u3khMnvrybrtIadbdu9+mgqBLWVqG9AqUY1xu2PDS7KWhGTJPMuHqJPpPzQImG7xV3yzWo3f6rpj6cE7ELXAxIvtjVAdV52TDpCvDHjnkLjcYEirAQiMqD6Zcht8gr8xoXs9odQWUMLsnQ/OOtTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549240; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=fR38OvfEPtxAfBY9/vqmCtT5ZvmUqWsVlZfslM2Guvw=; b=BTPnbJbfJVEifA7FInZTuYgOQv+om362BSSNETq3XsJ8373ygW/sFVmRx8x3l9xyCobj/P4aofaysL8mvzZiDYnsfrR3C3LH9uBQsXvSi8GO6bTdBEAX2+K7kQ2O55ygIUeOKkmzUESk2GAmXIeMUNBsYxjuShi2MOILeAoPZ8M= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742549240625285.6068744758145; Fri, 21 Mar 2025 02:27:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYeN-0006N9-RY; Fri, 21 Mar 2025 05:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeI-0006Hj-Tw; Fri, 21 Mar 2025 05:26:43 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeG-00056F-Tk; Fri, 21 Mar 2025 05:26:42 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:24 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:24 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 03/22] hw/misc/aspeed_hace: Improve readability and consistency in variable naming Date: Fri, 21 Mar 2025 17:25:59 +0800 Message-ID: <20250321092623.2097234-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549242903019000 Content-Type: text/plain; charset="utf-8" Currently, users define multiple local variables within different if-statem= ents. To improve readability and maintain consistency in variable naming, rename = the variables accordingly. Introduced "sg_addr" to clearly indicate the scatter-gather mode buffer add= ress. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index d8b5f048bb..4bcf6ed074 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -145,15 +145,19 @@ static bool has_padding(AspeedHACEState *s, struct io= vec *iov, static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, bool acc_mode) { + bool sg_acc_mode_final_request =3D false; + g_autofree uint8_t *digest_buf =3D NULL; struct iovec iov[ASPEED_HACE_MAX_SG]; + Error *local_err =3D NULL; uint32_t total_msg_len; - uint32_t pad_offset; - g_autofree uint8_t *digest_buf =3D NULL; size_t digest_len =3D 0; - bool sg_acc_mode_final_request =3D false; - int i; + uint32_t sg_addr =3D 0; + uint32_t pad_offset; + uint32_t len =3D 0; + uint32_t src =3D 0; void *haddr; - Error *local_err =3D NULL; + hwaddr plen; + int i; =20 if (acc_mode && s->hash_ctx =3D=3D NULL) { s->hash_ctx =3D qcrypto_hash_new(algo, &local_err); @@ -166,12 +170,7 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, } =20 if (sg_mode) { - uint32_t len =3D 0; - for (i =3D 0; !(len & SG_LIST_LEN_LAST); i++) { - uint32_t addr, src; - hwaddr plen; - if (i =3D=3D ASPEED_HACE_MAX_SG) { qemu_log_mask(LOG_GUEST_ERROR, "aspeed_hace: guest failed to set end of sg list m= arker\n"); @@ -183,12 +182,12 @@ static void do_hash_operation(AspeedHACEState *s, int= algo, bool sg_mode, len =3D address_space_ldl_le(&s->dram_as, src, MEMTXATTRS_UNSPECIFIED, NULL); =20 - addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_S= IZE, - MEMTXATTRS_UNSPECIFIED, NULL); - addr &=3D SG_LIST_ADDR_MASK; + sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LE= N_SIZE, + MEMTXATTRS_UNSPECIFIED, NULL); + sg_addr &=3D SG_LIST_ADDR_MASK; =20 plen =3D len & SG_LIST_LEN_MASK; - haddr =3D address_space_map(&s->dram_as, addr, &plen, false, + haddr =3D address_space_map(&s->dram_as, sg_addr, &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { qemu_log_mask(LOG_GUEST_ERROR, @@ -212,16 +211,16 @@ static void do_hash_operation(AspeedHACEState *s, int= algo, bool sg_mode, } } } else { - hwaddr len =3D s->regs[R_HASH_SRC_LEN]; + plen =3D s->regs[R_HASH_SRC_LEN]; =20 haddr =3D address_space_map(&s->dram_as, s->regs[R_HASH_SRC], - &len, false, MEMTXATTRS_UNSPECIFIED); + &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func_= _); return; } iov[0].iov_base =3D haddr; - iov[0].iov_len =3D len; + iov[0].iov_len =3D plen; i =3D 1; } =20 --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549282; cv=none; d=zohomail.com; s=zohoarc; b=mDTkGGo5pvdS2Xth5WCG1S5iX5FGVXSTXXG1iNMmrlBIZJ6OsxmOgYCrrB5fhAVIll387nM1jlrLyp3fCBEz7Bo7lOqVr1kjIW1QhcVcQj0YdC5h5Jqz472KIvvnC53ty1ctU0ASwWLwl+75Bca4xhXq9IjHxdBbbHYysHz3YVE= ARC-Message-Signature: i=1; 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Fri, 21 Mar 2025 05:26:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeI-0006Hi-Ty; Fri, 21 Mar 2025 05:26:43 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeH-00056m-Ai; Fri, 21 Mar 2025 05:26:42 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:25 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:25 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 04/22] hw/misc/aspeed_hace: Update hash source address handling to 64-bit for AST2700 Date: Fri, 21 Mar 2025 17:26:00 +0800 Message-ID: <20250321092623.2097234-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549282965019100 Content-Type: text/plain; charset="utf-8" The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and its DR= AM address space is also 64-bit. To support future AST2700 updates, the source hash buffer address data type is being updated to 64-bit. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 4bcf6ed074..9771d6e490 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -154,7 +154,7 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, uint32_t sg_addr =3D 0; uint32_t pad_offset; uint32_t len =3D 0; - uint32_t src =3D 0; + uint64_t src =3D 0; void *haddr; hwaddr plen; int i; @@ -177,7 +177,8 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, break; } =20 - src =3D s->regs[R_HASH_SRC] + (i * SG_LIST_ENTRY_SIZE); + src =3D deposit64(src, 0, 32, s->regs[R_HASH_SRC]); + src +=3D i * SG_LIST_ENTRY_SIZE; =20 len =3D address_space_ldl_le(&s->dram_as, src, MEMTXATTRS_UNSPECIFIED, NULL); @@ -212,8 +213,9 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, } } else { plen =3D s->regs[R_HASH_SRC_LEN]; + src =3D deposit64(src, 0, 32, s->regs[R_HASH_SRC]); =20 - haddr =3D address_space_map(&s->dram_as, s->regs[R_HASH_SRC], + haddr =3D address_space_map(&s->dram_as, src, &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func_= _); --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549376; cv=none; d=zohomail.com; s=zohoarc; b=Wc3zJOmvVajth9koc9gH/HUGtJSQ2Jn6m71YPpoRg6S+5Ks/KxcjSrjEDjs4LJCvE8Yo0gBcHN88PUqDeHOOCCmdK5nmDw7Kn4AL+13OeSxYA2NppGe/OX0vQQVS44/banwl7ugu1GMeCs3o5dPm8ZGD2OfCBCAuYK06et4/Xf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549376; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 21 Mar 2025 05:26:44 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:25 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:25 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 05/22] hw/misc/aspeed_hace: Introduce 64-bit digest_addr variable for AST2700 Date: Fri, 21 Mar 2025 17:26:01 +0800 Message-ID: <20250321092623.2097234-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549379382019100 Content-Type: text/plain; charset="utf-8" The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor with a 64-b= it DRAM address space. To support future AST2700 updates, a new "digest_addr" variable is introduced with a 64-bit data type. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 9771d6e490..8cf3f194a5 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -148,6 +148,7 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, bool sg_acc_mode_final_request =3D false; g_autofree uint8_t *digest_buf =3D NULL; struct iovec iov[ASPEED_HACE_MAX_SG]; + uint64_t digest_addr =3D 0; Error *local_err =3D NULL; uint32_t total_msg_len; size_t digest_len =3D 0; @@ -257,7 +258,8 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, return; } =20 - if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST], + digest_addr =3D deposit64(digest_addr, 0, 32, s->regs[R_HASH_DEST]); + if (address_space_write(&s->dram_as, digest_addr, MEMTXATTRS_UNSPECIFIED, digest_buf, digest_len)) { qemu_log_mask(LOG_GUEST_ERROR, --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 21 Mar 2025 17:26:25 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:25 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 06/22] hw/misc/aspeed_hace: Support accumulative mode for direct access mode Date: Fri, 21 Mar 2025 17:26:02 +0800 Message-ID: <20250321092623.2097234-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549468149019000 Content-Type: text/plain; charset="utf-8" Enable accumulative mode for direct access mode operations. In direct access mode, only a single source buffer is used, so the "iovec" count is set to 1. If "acc_mode" is enabled: 1. Accumulate "total_req_len" with the current request length ("plen"). 2. Check for padding and determine whether this is the final request. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 8cf3f194a5..d06158dffd 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -223,8 +223,21 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, return; } iov[0].iov_base =3D haddr; - iov[0].iov_len =3D plen; i =3D 1; + if (acc_mode) { + s->total_req_len +=3D plen; + + if (has_padding(s, &iov[0], plen, &total_msg_len, + &pad_offset)) { + /* Padding being present indicates the final request */ + sg_acc_mode_final_request =3D true; + iov[0].iov_len =3D pad_offset; + } else { + iov[0].iov_len =3D plen; + } + } else { + iov[0].iov_len =3D plen; + } } =20 if (acc_mode) { --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742549273237200.57380417269508; Fri, 21 Mar 2025 02:27:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYf0-00070R-8t; Fri, 21 Mar 2025 05:27:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeO-0006OO-M7; Fri, 21 Mar 2025 05:26:48 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeM-00056m-Pa; Fri, 21 Mar 2025 05:26:48 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:26 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:26 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 07/22] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses Date: Fri, 21 Mar 2025 17:26:03 +0800 Message-ID: <20250321092623.2097234-8-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549274965019100 Content-Type: text/plain; charset="utf-8" According to the AST2700 design, the data source address is 64-bit, with R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0]. Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits [63:32] and R_HASH_DEST storing bits [31:0]. The HMAC key buffer address is= also 64-bit, with R_HASH_KEY_BUFF_HI storing bits [63:32] and R_HASH_KEY_BUFF st= oring bits [31:0]. The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM addressable r= ange from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this range fits within 34 bits, = only bits [33:0] are needed to store the DRAM offset. To optimize address storag= e, the high physical address bits [1:0] of the source, digest and key buffer addresses are stored as dram_offset bits [33:32]. To achieve this, a src_hi_mask with a mask value of 0x3 is introduced, ensu= ring that src_addr_hi consists of bits [1:0]. The final src_addr is computed as (src_addr_hi[1:0] << 32) | src_addr[31:0], representing the DRAM offset wit= hin bits [33:0]. Similarly, a dest_hi_mask with a mask value of 0x3 is introduced to ensure = that dest_addr_hi consists of bits [1:0]. The final dest_addr is calculated as (dest_addr_hi[1:0] << 32) | dest_addr[31:0], representing the DRAM offset w= ithin bits [33:0]. Additionally, a key_hi_mask with a mask value of 0x3 is introduced to ensure that key_buf_addr_hi consists of bits [1:0]. The final key_buf_addr is determined as (key_buf_addr_hi[1:0] << 32) | key_buf_addr[31:0], representi= ng the DRAM offset within bits [33:0]. This approach eliminates the need to reduce the high part of the DRAM physi= cal address for DMA operations. Previously, this was calculated as (high physical address bits [7:0] - 4), since the DRAM start address is 0x4_00000000, making the high part address [7:0] - 4. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 5 ++++- hw/misc/aspeed_hace.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index b69a038d35..a4479bd383 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -22,7 +22,7 @@ =20 OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) =20 -#define ASPEED_HACE_NR_REGS (0x64 >> 2) +#define ASPEED_HACE_NR_REGS (0x9C >> 2) #define ASPEED_HACE_MAX_SG 256 /* max number of entries */ =20 struct AspeedHACEState { @@ -49,6 +49,9 @@ struct AspeedHACEClass { uint32_t key_mask; uint32_t hash_mask; bool raise_crypt_interrupt_workaround; + uint32_t src_hi_mask; + uint32_t dest_hi_mask; + uint32_t key_hi_mask; }; =20 #endif /* ASPEED_HACE_H */ diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index d06158dffd..51c6523fab 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -30,6 +30,9 @@ #define R_HASH_DEST (0x24 / 4) #define R_HASH_KEY_BUFF (0x28 / 4) #define R_HASH_SRC_LEN (0x2c / 4) +#define R_HASH_SRC_HI (0x90 / 4) +#define R_HASH_DEST_HI (0x94 / 4) +#define R_HASH_KEY_BUFF_HI (0x98 / 4) =20 #define R_HASH_CMD (0x30 / 4) /* Hash algorithm selection */ @@ -393,6 +396,15 @@ static void aspeed_hace_write(void *opaque, hwaddr add= r, uint64_t data, } } break; + case R_HASH_SRC_HI: + data &=3D ahc->src_hi_mask; + break; + case R_HASH_DEST_HI: + data &=3D ahc->dest_hi_mask; + break; + case R_HASH_KEY_BUFF_HI: + data &=3D ahc->key_hi_mask; + break; default: break; } @@ -566,6 +578,23 @@ static void aspeed_ast2700_hace_class_init(ObjectClass= *klass, void *data) ahc->key_mask =3D 0x7FFFFFF8; ahc->hash_mask =3D 0x00147FFF; =20 + /* + * The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM + * addressable range from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this r= ange + * fits within 34 bits, only bits [33:0] are needed to store the DRAM + * offset. To optimize address storage, the high physical address bits + * [1:0] of the source, digest and key buffer addresses are stored as + * dram_offset bits [33:32]. + * + * This approach eliminates the need to reduce the high part of the DR= AM + * physical address for DMA operations. Previously, this was calculate= d as + * (high physical address bits [7:0] - 4), since the DRAM start addres= s is + * 0x4_00000000, making the high part address [7:0] - 4. + */ + ahc->src_hi_mask =3D 0x00000003; + ahc->dest_hi_mask =3D 0x00000003; + ahc->key_hi_mask =3D 0x00000003; + /* * Currently, it does not support the CRYPT command. Instead, it only * sends an interrupt to notify the firmware that the crypt command --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549443; cv=none; d=zohomail.com; s=zohoarc; b=m+6RKOXABMFg9NMlOO51KrQ1AIkTyJCPe/1JG0rRxSHeH9XLVnYc1+swhT36qhTJk3R9nXJc61ooG+kuV4C3n7c2c+T9IohYgKzlKnYhSi4X022gzzI4h+engw3gdDDimQ+aWpiSrDu8LiIcYmDcKRY+UoXRsoLEIo/i98TkAZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549443; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=o25z2Aw2XQ4HMWyGJjYrliXQ0pRCoSEywsz//LHZDb8=; b=jd4wbBADKMsx1qrUo+YWWbe9IH1wytB/1JBkjZrCZ9wyHg2dJz0RkvPzwg7PswZRIlQbQpFls0oPRXJVjS8vtnJ2P2U74CWzKLMfBSL204e6z8msYx5lcd4FejjJpTQe0pTBGTqd3LX9FNhheSxSPRee5KG41B3yGiJp+6nQNos= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742549443237436.31567885189963; Fri, 21 Mar 2025 02:30:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYer-0006dX-JL; Fri, 21 Mar 2025 05:27:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeO-0006ON-Ly; Fri, 21 Mar 2025 05:26:48 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeM-00056F-P6; Fri, 21 Mar 2025 05:26:48 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:26 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:26 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 08/22] hw/misc/aspeed_hace: Support DMA 64 bits dram address. Date: Fri, 21 Mar 2025 17:26:04 +0800 Message-ID: <20250321092623.2097234-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549444011019000 Content-Type: text/plain; charset="utf-8" According to the AST2700 design, the data source address is 64-bit, with R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0]. Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits [63:32] and R_HASH_DEST storing bits [31:0]. Ideally, sg_addr should be 64-bit for the AST2700, using the following prog= ram to obtain the 64-bit sg_addr and convert it to a DRAM offset: ``` sg_addr =3D deposit64(sg_addr, 32, 32, address_space_ldl_le(&s->dram_as, src + SG_LIST_ADDR_SI= ZE, MEMTXATTRS_UNSPECIFIED, NULL); sg_addr -=3D 0x400000000; ``` To maintain compatibility with older SoCs such as the AST2600, the AST2700 = HW HACE controllers automatically set bit 34 of the 64-bit sg_addr. As a resul= t, the firmware only needs to provide a 32-bit sg_addr containing bits [31:0]. This is sufficient for the AST2700, as it uses a DRAM offset rather than a = DRAM address. Introduce a has_dma64 class attribute and set it to true for the AST2700. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 1 + hw/misc/aspeed_hace.c | 27 ++++++++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index a4479bd383..58fb66009a 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -52,6 +52,7 @@ struct AspeedHACEClass { uint32_t src_hi_mask; uint32_t dest_hi_mask; uint32_t key_hi_mask; + bool has_dma64; }; =20 #endif /* ASPEED_HACE_H */ diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 51c6523fab..8f333fc97e 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -148,6 +148,7 @@ static bool has_padding(AspeedHACEState *s, struct iove= c *iov, static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, bool acc_mode) { + AspeedHACEClass *ahc =3D ASPEED_HACE_GET_CLASS(s); bool sg_acc_mode_final_request =3D false; g_autofree uint8_t *digest_buf =3D NULL; struct iovec iov[ASPEED_HACE_MAX_SG]; @@ -182,6 +183,9 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, } =20 src =3D deposit64(src, 0, 32, s->regs[R_HASH_SRC]); + if (ahc->has_dma64) { + src =3D deposit64(src, 32, 32, s->regs[R_HASH_SRC_HI]); + } src +=3D i * SG_LIST_ENTRY_SIZE; =20 len =3D address_space_ldl_le(&s->dram_as, src, @@ -190,6 +194,21 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LE= N_SIZE, MEMTXATTRS_UNSPECIFIED, NULL); sg_addr &=3D SG_LIST_ADDR_MASK; + /* + * Ideally, sg_addr should be 64-bit for the AST2700, using the + * following program to obtain the 64-bit sg_addr and convert = it + * to a DRAM offset: + * sg_addr =3D deposit64(sg_addr, 32, 32, + * address_space_ldl_le(&s->dram_as, src + SG_ADDR_LEN_SI= ZE, + * MEMTXATTRS_UNSPECIFIED, NULL); + * sg_addr -=3D 0x400000000; + * + * To maintain compatibility with older SoCs such as the AST26= 00, + * the AST2700 HW automatically set bit 34 of the 64-bit sg_ad= dr. + * As a result, the firmware only needs to provide a 32-bit sg= _addr + * containing bits [31:0]. This is sufficient for the AST2700,= as + * it uses a DRAM offset rather than a DRAM address. + */ =20 plen =3D len & SG_LIST_LEN_MASK; haddr =3D address_space_map(&s->dram_as, sg_addr, &plen, false, @@ -218,7 +237,9 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, } else { plen =3D s->regs[R_HASH_SRC_LEN]; src =3D deposit64(src, 0, 32, s->regs[R_HASH_SRC]); - + if (ahc->has_dma64) { + src =3D deposit64(src, 32, 32, s->regs[R_HASH_SRC_HI]); + } haddr =3D address_space_map(&s->dram_as, src, &plen, false, MEMTXATTRS_UNSPECIFIED); if (haddr =3D=3D NULL) { @@ -275,6 +296,9 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, } =20 digest_addr =3D deposit64(digest_addr, 0, 32, s->regs[R_HASH_DEST]); + if (ahc->has_dma64) { + digest_addr =3D deposit64(digest_addr, 32, 32, s->regs[R_HASH_DEST= _HI]); + } if (address_space_write(&s->dram_as, digest_addr, MEMTXATTRS_UNSPECIFIED, digest_buf, digest_len)) { @@ -601,6 +625,7 @@ static void aspeed_ast2700_hace_class_init(ObjectClass = *klass, void *data) * has completed. It is a temporary workaround. */ ahc->raise_crypt_interrupt_workaround =3D true; + ahc->has_dma64 =3D true; } =20 static const TypeInfo aspeed_ast2700_hace_info =3D { --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549385; cv=none; d=zohomail.com; s=zohoarc; b=gHIo53tqLS3rQ+6DwD/2SiGp5SOBpFdFf703yJug/BSzdo4TeyxrMezpDNHpYN0XLWj+9ubSX/r1AzYFf4SBDorm/GFZlWKmdOJ+dpJx0hzk+F8K8Y+dCJK8iU+XKyzkbqt+szQORysXsL/j9+CcDFD56lnspBiuIfXnAh0GgyA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549385; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=mmD/hTDTVJl2Hr2T1lzXVYz+zCt4j+rrSoLPK7sKlzU=; b=IGH73ugTRpzZt5Fml7sb6zgzWqHk/tNESI5hm/h8T4Qg5VloB/On9U6d0rEZlFXM6rL45GZhqjTp61kZK8AaPrUQ5x8xYbga72zr0JDP3izydjNIzAhAZ7bRJKe+ikRsNMz+cIjdEUGurJJSuOKrlpWLd9jrL8WNIjQ9jGoooD8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742549385909578.3109323787526; Fri, 21 Mar 2025 02:29:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYeb-0006aH-NL; Fri, 21 Mar 2025 05:27:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeR-0006T7-Sf; Fri, 21 Mar 2025 05:26:51 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeP-00056F-Ed; Fri, 21 Mar 2025 05:26:51 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:26 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:26 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 09/22] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang Date: Fri, 21 Mar 2025 17:26:05 +0800 Message-ID: <20250321092623.2097234-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549387471019000 Content-Type: text/plain; charset="utf-8" Currently, if the program encounters an unsupported algorithm, it does not = set the HASH_IRQ bit in the status register and send an interrupt to indicate command completion. As a result, the FW gets stuck waiting for a completion signal from the HACE module. Additionally, in do_hash_operation, if an error occurs within the condition= al statement, the HASH_IRQ bit is not set in the status register. This causes = the firmware to continuously send HASH commands, as it is unaware that the HACE model has completed processing the command. To fix this, the HASH_IRQ bit in the status register must always be set to ensure that the firmware receives an interrupt from the HACE module, preven= ting it from getting stuck or repeatedly sending HASH commands. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 8f333fc97e..d4f653670e 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -311,12 +311,6 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, iov[i - 1].iov_len, false, iov[i - 1].iov_len); } - - /* - * Set status bits to indicate completion. Testing shows hardware sets - * these irrespective of HASH_IRQ_EN. - */ - s->regs[R_STATUS] |=3D HASH_IRQ; } =20 static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int s= ize) @@ -400,10 +394,16 @@ static void aspeed_hace_write(void *opaque, hwaddr ad= dr, uint64_t data, qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid hash algorithm selection 0x%"PRIx64"\= n", __func__, data & ahc->hash_mask); - break; + } else { + do_hash_operation(s, algo, data & HASH_SG_EN, + ((data & HASH_HMAC_MASK) =3D=3D HASH_DIGEST_ACCUM)); } - do_hash_operation(s, algo, data & HASH_SG_EN, - ((data & HASH_HMAC_MASK) =3D=3D HASH_DIGEST_ACCUM)); + + /* + * Set status bits to indicate completion. Testing shows hardware = sets + * these irrespective of HASH_IRQ_EN. + */ + s->regs[R_STATUS] |=3D HASH_IRQ; =20 if (data & HASH_IRQ_EN) { qemu_irq_raise(s->irq); --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549292; cv=none; d=zohomail.com; s=zohoarc; b=dv4uptPPTJ27ybwOQXT1elIs6Cp0jOtC70plP/HyzrNZlj8EojCMnoG5Hp/fKRP9glN7lYeLjTobsrGtX/fJRxvsndIi8Vx5+ug3rof8ymCB1u2UiWmMcnFS8rPjm1RPVTvHC7VCSvNPOV/ZtHwKqORGNwhT+U/RxYvEa+w4Ogs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549292; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=inpvI2tLmMmJRYewBkqsi55iju6JfoXM08iq6C9L6lY=; b=AF+4qbUg5je7D/JQIdZyHu+FfJiBAqKjBfgvl4odqcu6UV43aUi7qwEYTAY1tDt8aukQA5Ksy6BDbqTdOmuH2fB+huCcdlBnRF5hDcRHEcMssP8LBZUDpK3y8nAEcZKQMSnBFI/MDlpS3/iBavx66JNFBsSgolqK4yEteD6I31I= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742549292862109.04134060605202; Fri, 21 Mar 2025 02:28:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYez-0006vq-8r; Fri, 21 Mar 2025 05:27:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeR-0006TC-SQ; Fri, 21 Mar 2025 05:26:51 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYeP-00056m-Fi; Fri, 21 Mar 2025 05:26:51 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:27 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:27 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 10/22] hw/misc/aspeed_hace:: Support setting different memory size Date: Fri, 21 Mar 2025 17:26:06 +0800 Message-ID: <20250321092623.2097234-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549295128019000 Content-Type: text/plain; charset="utf-8" The memory size was previously hardcoded to 0x1000 (4K). However, the actual memory size of the HACE controller varies across different models: 1. AST2400/AST2500: 0x1000 (4K) 2. AST2600/AST1030: 0x10000 (64K) 3. AST2700: 0x100 (256 bytes) To address this, a new class attribute, mem_size, has been introduced to dynamically set the appropriate memory size for each HACE model, ensuring correct allocation across AST2400, AST2500, AST2600, AST1030 and AST2700. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 1 + hw/misc/aspeed_hace.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index 58fb66009a..db95f2fd4b 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -53,6 +53,7 @@ struct AspeedHACEClass { uint32_t dest_hi_mask; uint32_t key_hi_mask; bool has_dma64; + uint64_t mem_size; }; =20 #endif /* ASPEED_HACE_H */ diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index d4f653670e..53b3b390e3 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -463,11 +463,12 @@ static void aspeed_hace_realize(DeviceState *dev, Err= or **errp) { AspeedHACEState *s =3D ASPEED_HACE(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedHACEClass *ahc =3D ASPEED_HACE_GET_CLASS(s); =20 sysbus_init_irq(sbd, &s->irq); =20 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_hace_ops, s, - TYPE_ASPEED_HACE, 0x1000); + TYPE_ASPEED_HACE, ahc->mem_size); =20 if (!s->dram_mr) { error_setg(errp, TYPE_ASPEED_HACE ": 'dram' link not set"); @@ -521,6 +522,7 @@ static void aspeed_ast2400_hace_class_init(ObjectClass = *klass, void *data) =20 dc->desc =3D "AST2400 Hash and Crypto Engine"; =20 + ahc->mem_size =3D 0x1000; ahc->src_mask =3D 0x0FFFFFFF; ahc->dest_mask =3D 0x0FFFFFF8; ahc->key_mask =3D 0x0FFFFFC0; @@ -540,6 +542,7 @@ static void aspeed_ast2500_hace_class_init(ObjectClass = *klass, void *data) =20 dc->desc =3D "AST2500 Hash and Crypto Engine"; =20 + ahc->mem_size =3D 0x1000; ahc->src_mask =3D 0x3fffffff; ahc->dest_mask =3D 0x3ffffff8; ahc->key_mask =3D 0x3FFFFFC0; @@ -559,6 +562,7 @@ static void aspeed_ast2600_hace_class_init(ObjectClass = *klass, void *data) =20 dc->desc =3D "AST2600 Hash and Crypto Engine"; =20 + ahc->mem_size =3D 0x10000; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; @@ -578,6 +582,7 @@ static void aspeed_ast1030_hace_class_init(ObjectClass = *klass, void *data) =20 dc->desc =3D "AST1030 Hash and Crypto Engine"; =20 + ahc->mem_size =3D 0x10000; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; @@ -597,6 +602,7 @@ static void aspeed_ast2700_hace_class_init(ObjectClass = *klass, void *data) =20 dc->desc =3D "AST2700 Hash and Crypto Engine"; =20 + ahc->mem_size =3D 0x100; ahc->src_mask =3D 0x7FFFFFFF; ahc->dest_mask =3D 0x7FFFFFF8; ahc->key_mask =3D 0x7FFFFFF8; --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549335; cv=none; d=zohomail.com; s=zohoarc; b=ZN/G5qlBAYAGiplLO44D990fic6H5bmmwWQ+PM6rkZC/MprJSN0wXQp6tEcHuWQc6l1tyIxn2yk6vvTrfpzXpOxj87bDFOIL5TEgA0ygOlfuD+zaR6BXzYOZeaBjLBQUk9wecTPmFieTmJuJ2u+EsMTX8rLAmGR+r316yGAWvc8= ARC-Message-Signature: i=1; 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Fri, 21 Mar 2025 05:27:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYet-0006pm-QY; Fri, 21 Mar 2025 05:27:22 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYep-00056F-UI; Fri, 21 Mar 2025 05:27:19 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:27 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:27 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 11/22] hw/misc/aspeed_hace: Add trace-events for better debugging Date: Fri, 21 Mar 2025 17:26:07 +0800 Message-ID: <20250321092623.2097234-12-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549337403019000 Content-Type: text/plain; charset="utf-8" Introduced "trace_aspeed_hace_addr", "trace_aspeed_hace_sg", "trace_aspeed_hace_read", and "trace_aspeed_hace_write" trace events. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 8 ++++++++ hw/misc/trace-events | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 53b3b390e3..b8e473ee3f 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -18,6 +18,7 @@ #include "crypto/hash.h" #include "hw/qdev-properties.h" #include "hw/irq.h" +#include "trace.h" =20 #define R_CRYPT_CMD (0x10 / 4) =20 @@ -186,6 +187,7 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, if (ahc->has_dma64) { src =3D deposit64(src, 32, 32, s->regs[R_HASH_SRC_HI]); } + trace_aspeed_hace_addr("src", src); src +=3D i * SG_LIST_ENTRY_SIZE; =20 len =3D address_space_ldl_le(&s->dram_as, src, @@ -194,6 +196,7 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, sg_addr =3D address_space_ldl_le(&s->dram_as, src + SG_LIST_LE= N_SIZE, MEMTXATTRS_UNSPECIFIED, NULL); sg_addr &=3D SG_LIST_ADDR_MASK; + trace_aspeed_hace_sg(i, sg_addr, len); /* * Ideally, sg_addr should be 64-bit for the AST2700, using the * following program to obtain the 64-bit sg_addr and convert = it @@ -237,6 +240,7 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, } else { plen =3D s->regs[R_HASH_SRC_LEN]; src =3D deposit64(src, 0, 32, s->regs[R_HASH_SRC]); + trace_aspeed_hace_addr("src", src); if (ahc->has_dma64) { src =3D deposit64(src, 32, 32, s->regs[R_HASH_SRC_HI]); } @@ -299,6 +303,7 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, if (ahc->has_dma64) { digest_addr =3D deposit64(digest_addr, 32, 32, s->regs[R_HASH_DEST= _HI]); } + trace_aspeed_hace_addr("digest", digest_addr); if (address_space_write(&s->dram_as, digest_addr, MEMTXATTRS_UNSPECIFIED, digest_buf, digest_len)) { @@ -326,6 +331,7 @@ static uint64_t aspeed_hace_read(void *opaque, hwaddr a= ddr, unsigned int size) return 0; } =20 + trace_aspeed_hace_read(addr << 2, s->regs[addr]); return s->regs[addr]; } =20 @@ -344,6 +350,8 @@ static void aspeed_hace_write(void *opaque, hwaddr addr= , uint64_t data, return; } =20 + trace_aspeed_hace_write(addr << 2, data); + switch (addr) { case R_STATUS: if (data & HASH_IRQ) { diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 4383808d7a..cf96e68cfa 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -302,6 +302,12 @@ aspeed_peci_read(uint64_t offset, uint64_t data) "offs= et 0x%" PRIx64 " data 0x%" aspeed_peci_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " da= ta 0x%" PRIx64 aspeed_peci_raise_interrupt(uint32_t ctrl, uint32_t status) "ctrl 0x%" PRI= x32 " status 0x%" PRIx32 =20 +# aspeed_hace.c +aspeed_hace_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " dat= a 0x%" PRIx64 +aspeed_hace_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " da= ta 0x%" PRIx64 +aspeed_hace_sg(int index, uint64_t addr, uint32_t len) "%d: addr 0x%" PRIx= 64 " len 0x%" PRIx32 +aspeed_hace_addr(const char *s, uint64_t addr) "%s: 0x%" PRIx64 + # bcm2835_property.c bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbo= x property tag:0x%08x in_sz:%u out_sz:%zu" =20 --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 21 Mar 2025 17:26:27 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:27 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 12/22] hw/misc/aspeed_hace Support to dump plaintext and digest for better debugging Date: Fri, 21 Mar 2025 17:26:08 +0800 Message-ID: <20250321092623.2097234-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549369356019100 Content-Type: text/plain; charset="utf-8" 1. Disabled by default. Uncomment "#define DEBUG_HACE 1" to enable it. 2. Uses the "qemu_hexdump" API to dump the digest result. 3. Uses the "iov_hexdump" API to dump the source vector, which contains the source plaintext. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index b8e473ee3f..ae4d2fa687 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -10,8 +10,10 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "qemu/iov.h" #include "hw/misc/aspeed_hace.h" #include "qapi/error.h" #include "migration/vmstate.h" @@ -20,6 +22,8 @@ #include "hw/irq.h" #include "trace.h" =20 +/* #define DEBUG_HACE 1 */ + #define R_CRYPT_CMD (0x10 / 4) =20 #define R_STATUS (0x1c / 4) @@ -268,6 +272,10 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, } } =20 +#ifdef DEBUG_HACE + iov_hexdump(iov, i, stdout, "plaintext", 0xa000); +#endif + if (acc_mode) { if (qcrypto_hash_updatev(s->hash_ctx, iov, i, &local_err) < 0) { qemu_log_mask(LOG_GUEST_ERROR, "qcrypto hash update failed : %= s", @@ -311,6 +319,10 @@ static void do_hash_operation(AspeedHACEState *s, int = algo, bool sg_mode, "aspeed_hace: address space write failed\n"); } =20 +#ifdef DEBUG_HACE + qemu_hexdump(stdout, "digest", digest_buf, digest_len); +#endif + for (; i > 0; i--) { address_space_unmap(&s->dram_as, iov[i - 1].iov_base, iov[i - 1].iov_len, false, --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549413; cv=none; d=zohomail.com; s=zohoarc; b=f7k0K10ixxLIuJjDYt3S+PJA6KybuqW2ERuRkzHqjru9xQjwemhEB5ySRKkH/KqzOshs0oZRHOC0kHtrLCxGGbGxkQCaG7yoTCdQVEvUXaY2mCMzQSUtXes7U7eRz/i1Egt+TgMF3xq9zDXB9E023/VTDAMmgmvq8cJPDlHvJ7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549413; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 21 Mar 2025 05:27:27 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:28 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:28 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 13/22] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases Date: Fri, 21 Mar 2025 17:26:09 +0800 Message-ID: <20250321092623.2097234-14-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549415837019000 Content-Type: text/plain; charset="utf-8" The test cases for the ASPEED HACE model were originally placed in aspeed_hace-test.c. However, this test file only supports ARM32. To enable compatibility with all ASPEED SoCs, including the AST2700, which uses the AArch64 architecture, this update introduces a new source file, aspeed-hace-utils.c. All common APIs and test cases have been moved from aspeed_hace-test.c to aspeed-hace-utils.c to facilitate reuse across different ASPEED SoCs. As a result, these test cases can now be reused for AST2700 and future ASPE= ED SoC testing. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 71 +++++ tests/qtest/aspeed-hace-utils.c | 455 ++++++++++++++++++++++++++++ tests/qtest/aspeed_hace-test.c | 515 ++------------------------------ tests/qtest/meson.build | 1 + 4 files changed, 547 insertions(+), 495 deletions(-) create mode 100644 tests/qtest/aspeed-hace-utils.h create mode 100644 tests/qtest/aspeed-hace-utils.c diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h new file mode 100644 index 0000000000..598577c69b --- /dev/null +++ b/tests/qtest/aspeed-hace-utils.h @@ -0,0 +1,71 @@ +/* + * QTest testcase for the ASPEED Hash and Crypto Engine + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright 2021 IBM Corp. + */ + +#ifndef TESTS_ASPEED_HACE_UTILS_H +#define TESTS_ASPEED_HACE_UTILS_H + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "qemu/bitops.h" + +#define HACE_CMD 0x10 +#define HACE_SHA_BE_EN BIT(3) +#define HACE_MD5_LE_EN BIT(2) +#define HACE_ALGO_MD5 0 +#define HACE_ALGO_SHA1 BIT(5) +#define HACE_ALGO_SHA224 BIT(6) +#define HACE_ALGO_SHA256 (BIT(4) | BIT(6)) +#define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) +#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) +#define HACE_SG_EN BIT(18) +#define HACE_ACCUM_EN BIT(8) + +#define HACE_STS 0x1c +#define HACE_RSA_ISR BIT(13) +#define HACE_CRYPTO_ISR BIT(12) +#define HACE_HASH_ISR BIT(9) +#define HACE_RSA_BUSY BIT(2) +#define HACE_CRYPTO_BUSY BIT(1) +#define HACE_HASH_BUSY BIT(0) +#define HACE_HASH_SRC 0x20 +#define HACE_HASH_DIGEST 0x24 +#define HACE_HASH_KEY_BUFF 0x28 +#define HACE_HASH_DATA_LEN 0x2c +#define HACE_HASH_CMD 0x30 + +/* Scatter-Gather Hash */ +#define SG_LIST_LEN_LAST BIT(31) +struct AspeedSgList { + uint32_t len; + uint32_t addr; +} __attribute__ ((__packed__)); + +struct AspeedMasks { + uint32_t src; + uint32_t dest; + uint32_t len; +}; + +void aspeed_test_md5(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha256(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha512(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha256_sg(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha512_sg(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha256_accum(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_sha512_accum(const char *machine, const uint32_t base, + const uint32_t src_addr); +void aspeed_test_addresses(const char *machine, const uint32_t base, + const struct AspeedMasks *expected); + +#endif /* TESTS_ASPEED_HACE_UTILS_H */ + diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c new file mode 100644 index 0000000000..8582847945 --- /dev/null +++ b/tests/qtest/aspeed-hace-utils.c @@ -0,0 +1,455 @@ +/* + * QTest testcase for the ASPEED Hash and Crypto Engine + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright 2021 IBM Corp. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "qemu/bitops.h" +#include "aspeed-hace-utils.h" + +/* + * Test vector is the ascii "abc" + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abc' | dd of=3D/tmp/test + * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done + * + */ +static const uint8_t test_vector[] =3D {0x61, 0x62, 0x63}; + +static const uint8_t test_result_sha512[] =3D { + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, + 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, + 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, + 0xa5, 0x4c, 0xa4, 0x9f}; + +static const uint8_t test_result_sha256[] =3D { + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, + 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; + +static const uint8_t test_result_md5[] =3D { + 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, + 0x28, 0xe1, 0x7f, 0x72}; + +/* + * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken + * into blocks of 3 characters as shown + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abcdefghijkl' | dd of=3D/tmp/test + * for hash in sha512sum sha256sum; do $hash /tmp/test; done + * + */ +static const uint8_t test_vector_sg1[] =3D {0x61, 0x62, 0x63, 0x64, 0x65, = 0x66}; +static const uint8_t test_vector_sg2[] =3D {0x67, 0x68, 0x69}; +static const uint8_t test_vector_sg3[] =3D {0x6a, 0x6b, 0x6c}; + +static const uint8_t test_result_sg_sha512[] =3D { + 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, + 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, + 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, + 0xd5, 0xb7, 0x3f, 0xc3, 0x96, 0xc1, 0x2b, 0xe3, 0x8b, 0x2b, 0xd5, 0xd8, + 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, + 0xf8, 0x6d, 0xda, 0x2e}; + +static const uint8_t test_result_sg_sha256[] =3D { + 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, + 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, + 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; + +/* + * The accumulative mode requires firmware to provide internal initial sta= te + * and message padding (including length L at the end of padding). + * + * This test vector is a ascii text "abc" with padding message. + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abc' | dd of=3D/tmp/test + * for hash in sha512sum sha256sum; do $hash /tmp/test; done + */ +static const uint8_t test_vector_accum_512[] =3D { + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; + +static const uint8_t test_vector_accum_256[] =3D { + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; + +static const uint8_t test_result_accum_sha512[] =3D { + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, + 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, + 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, + 0xa5, 0x4c, 0xa4, 0x9f}; + +static const uint8_t test_result_accum_sha256[] =3D { + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, + 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; + +static void write_regs(QTestState *s, uint32_t base, uint32_t src, + uint32_t length, uint32_t out, uint32_t method) +{ + qtest_writel(s, base + HACE_HASH_SRC, src); + qtest_writel(s, base + HACE_HASH_DIGEST, out); + qtest_writel(s, base + HACE_HASH_DATA_LEN, length); + qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); +} + +void aspeed_test_md5(const char *machine, const uint32_t base, + const uint32_t src_addr) + +{ + QTestState *s =3D qtest_init(machine); + + uint32_t digest_addr =3D src_addr + 0x01000000; + uint8_t digest[16] =3D {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), + digest_addr, HACE_ALGO_MD5); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_md5, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha256(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t digest_addr =3D src_addr + 0x1000000; + uint8_t digest[32] =3D {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, + HACE_ALGO_SHA256); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sha256, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha512(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t digest_addr =3D src_addr + 0x1000000; + uint8_t digest[64] =3D {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, + HACE_ALGO_SHA512); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sha512, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha256_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t src_addr_1 =3D src_addr + 0x1000000; + const uint32_t src_addr_2 =3D src_addr + 0x2000000; + const uint32_t src_addr_3 =3D src_addr + 0x3000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[32] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_sg1)), + cpu_to_le32(src_addr_1) }, + { cpu_to_le32(sizeof(test_vector_sg2)), + cpu_to_le32(src_addr_2) }, + { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), + cpu_to_le32(src_addr_3) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha256, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha512_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t src_addr_1 =3D src_addr + 0x1000000; + const uint32_t src_addr_2 =3D src_addr + 0x2000000; + const uint32_t src_addr_3 =3D src_addr + 0x3000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[64] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_sg1)), + cpu_to_le32(src_addr_1) }, + { cpu_to_le32(sizeof(test_vector_sg2)), + cpu_to_le32(src_addr_2) }, + { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), + cpu_to_le32(src_addr_3) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha512, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha256_accum(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t buffer_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[32] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), + cpu_to_le32(buffer_addr) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, buffer_addr, test_vector_accum_256, + sizeof(test_vector_accum_256)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, sizeof(test_vector_accum_256), + digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_accum_sha256, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_sha512_accum(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t buffer_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x4000000; + uint8_t digest[64] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), + cpu_to_le32(buffer_addr) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, buffer_addr, test_vector_accum_512, + sizeof(test_vector_accum_512)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, sizeof(test_vector_accum_512), + digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_accum_sha512, sizeof(digest)); + + qtest_quit(s); +} + +void aspeed_test_addresses(const char *machine, const uint32_t base, + const struct AspeedMasks *expected) +{ + QTestState *s =3D qtest_init(machine); + + /* + * Check command mode is zero, meaning engine is in direct access mode, + * as this affects the masking behavior of the HASH_SRC register. + */ + g_assert_cmphex(qtest_readl(s, base + HACE_CMD), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); + + + /* Check that the address masking is correct */ + qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, expected= ->src); + + qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, + expected->dest); + + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, + expected->len); + + /* Reset to zero */ + qtest_writel(s, base + HACE_HASH_SRC, 0); + qtest_writel(s, base + HACE_HASH_DIGEST, 0); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); + + /* Check that all bits are now zero */ + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); + + qtest_quit(s); +} + diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index ce86a44672..42a306af2a 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -6,584 +6,109 @@ */ =20 #include "qemu/osdep.h" - #include "libqtest.h" #include "qemu/bitops.h" +#include "aspeed-hace-utils.h" =20 -#define HACE_CMD 0x10 -#define HACE_SHA_BE_EN BIT(3) -#define HACE_MD5_LE_EN BIT(2) -#define HACE_ALGO_MD5 0 -#define HACE_ALGO_SHA1 BIT(5) -#define HACE_ALGO_SHA224 BIT(6) -#define HACE_ALGO_SHA256 (BIT(4) | BIT(6)) -#define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) -#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) -#define HACE_SG_EN BIT(18) -#define HACE_ACCUM_EN BIT(8) - -#define HACE_STS 0x1c -#define HACE_RSA_ISR BIT(13) -#define HACE_CRYPTO_ISR BIT(12) -#define HACE_HASH_ISR BIT(9) -#define HACE_RSA_BUSY BIT(2) -#define HACE_CRYPTO_BUSY BIT(1) -#define HACE_HASH_BUSY BIT(0) -#define HACE_HASH_SRC 0x20 -#define HACE_HASH_DIGEST 0x24 -#define HACE_HASH_KEY_BUFF 0x28 -#define HACE_HASH_DATA_LEN 0x2c -#define HACE_HASH_CMD 0x30 -/* Scatter-Gather Hash */ -#define SG_LIST_LEN_LAST BIT(31) -struct AspeedSgList { - uint32_t len; - uint32_t addr; -} __attribute__ ((__packed__)); - -/* - * Test vector is the ascii "abc" - * - * Expected results were generated using command line utitiles: - * - * echo -n -e 'abc' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done - * - */ -static const uint8_t test_vector[] =3D {0x61, 0x62, 0x63}; - -static const uint8_t test_result_sha512[] =3D { - 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, - 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, - 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, - 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, - 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, - 0xa5, 0x4c, 0xa4, 0x9f}; - -static const uint8_t test_result_sha256[] =3D { - 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, - 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, - 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; - -static const uint8_t test_result_md5[] =3D { - 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, - 0x28, 0xe1, 0x7f, 0x72}; - -/* - * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken - * into blocks of 3 characters as shown - * - * Expected results were generated using command line utitiles: - * - * echo -n -e 'abcdefghijkl' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum; do $hash /tmp/test; done - * - */ -static const uint8_t test_vector_sg1[] =3D {0x61, 0x62, 0x63, 0x64, 0x65, = 0x66}; -static const uint8_t test_vector_sg2[] =3D {0x67, 0x68, 0x69}; -static const uint8_t test_vector_sg3[] =3D {0x6a, 0x6b, 0x6c}; - -static const uint8_t test_result_sg_sha512[] =3D { - 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, - 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, - 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, - 0xd5, 0xb7, 0x3f, 0xc3, 0x96, 0xc1, 0x2b, 0xe3, 0x8b, 0x2b, 0xd5, 0xd8, - 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, - 0xf8, 0x6d, 0xda, 0x2e}; - -static const uint8_t test_result_sg_sha256[] =3D { - 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, - 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, - 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; - -/* - * The accumulative mode requires firmware to provide internal initial sta= te - * and message padding (including length L at the end of padding). - * - * This test vector is a ascii text "abc" with padding message. - * - * Expected results were generated using command line utitiles: - * - * echo -n -e 'abc' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum; do $hash /tmp/test; done - */ -static const uint8_t test_vector_accum_512[] =3D { - 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; - -static const uint8_t test_vector_accum_256[] =3D { - 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; - -static const uint8_t test_result_accum_sha512[] =3D { - 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, - 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, - 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, - 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, - 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, - 0xa5, 0x4c, 0xa4, 0x9f}; - -static const uint8_t test_result_accum_sha256[] =3D { - 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, - 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, - 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; - -static void write_regs(QTestState *s, uint32_t base, uint32_t src, - uint32_t length, uint32_t out, uint32_t method) -{ - qtest_writel(s, base + HACE_HASH_SRC, src); - qtest_writel(s, base + HACE_HASH_DIGEST, out); - qtest_writel(s, base + HACE_HASH_DATA_LEN, length); - qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); -} - -static void test_md5(const char *machine, const uint32_t base, - const uint32_t src_addr) - -{ - QTestState *s =3D qtest_init(machine); - - uint32_t digest_addr =3D src_addr + 0x01000000; - uint8_t digest[16] =3D {0}; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); - - write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_A= LGO_MD5); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_md5, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha256(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t digest_addr =3D src_addr + 0x1000000; - uint8_t digest[32] =3D {0}; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); - - write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_A= LGO_SHA256); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_sha256, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha512(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t digest_addr =3D src_addr + 0x1000000; - uint8_t digest[64] =3D {0}; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); - - write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_A= LGO_SHA512); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_sha512, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha256_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; - uint8_t digest[32] =3D {0}; - struct AspeedSgList array[] =3D { - { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, - { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, - { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, - }; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); - qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); - qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); - qtest_memwrite(s, src_addr, array, sizeof(array)); - - write_regs(s, base, src_addr, - (sizeof(test_vector_sg1) - + sizeof(test_vector_sg2) - + sizeof(test_vector_sg3)), - digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_sg_sha256, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha512_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; - uint8_t digest[64] =3D {0}; - struct AspeedSgList array[] =3D { - { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, - { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, - { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, - }; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); - qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); - qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); - qtest_memwrite(s, src_addr, array, sizeof(array)); - - write_regs(s, base, src_addr, - (sizeof(test_vector_sg1) - + sizeof(test_vector_sg2) - + sizeof(test_vector_sg3)), - digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_sg_sha512, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha256_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; - uint8_t digest[32] =3D {0}; - struct AspeedSgList array[] =3D { - { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, - }; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, buffer_addr, test_vector_accum_256, - sizeof(test_vector_accum_256)); - qtest_memwrite(s, src_addr, array, sizeof(array)); - - write_regs(s, base, src_addr, sizeof(test_vector_accum_256), - digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_accum_sha256, sizeof(digest)); - - qtest_quit(s); -} - -static void test_sha512_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) -{ - QTestState *s =3D qtest_init(machine); - - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; - uint8_t digest[64] =3D {0}; - struct AspeedSgList array[] =3D { - { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, - }; - - /* Check engine is idle, no busy or irq bits set */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Write test vector into memory */ - qtest_memwrite(s, buffer_addr, test_vector_accum_512, - sizeof(test_vector_accum_512)); - qtest_memwrite(s, src_addr, array, sizeof(array)); - - write_regs(s, base, src_addr, sizeof(test_vector_accum_512), - digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN); - - /* Check hash IRQ status is asserted */ - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); - - /* Clear IRQ status and check status is deasserted */ - qtest_writel(s, base + HACE_STS, 0x00000200); - g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); - - /* Read computed digest from memory */ - qtest_memread(s, digest_addr, digest, sizeof(digest)); - - /* Check result of computation */ - g_assert_cmpmem(digest, sizeof(digest), - test_result_accum_sha512, sizeof(digest)); - - qtest_quit(s); -} - -struct masks { - uint32_t src; - uint32_t dest; - uint32_t len; -}; - -static const struct masks ast2600_masks =3D { +static const struct AspeedMasks ast2600_masks =3D { .src =3D 0x7fffffff, .dest =3D 0x7ffffff8, .len =3D 0x0fffffff, }; =20 -static const struct masks ast2500_masks =3D { +static const struct AspeedMasks ast2500_masks =3D { .src =3D 0x3fffffff, .dest =3D 0x3ffffff8, .len =3D 0x0fffffff, }; =20 -static const struct masks ast2400_masks =3D { +static const struct AspeedMasks ast2400_masks =3D { .src =3D 0x0fffffff, .dest =3D 0x0ffffff8, .len =3D 0x0fffffff, }; =20 -static void test_addresses(const char *machine, const uint32_t base, - const struct masks *expected) -{ - QTestState *s =3D qtest_init(machine); - - /* - * Check command mode is zero, meaning engine is in direct access mode, - * as this affects the masking behavior of the HASH_SRC register. - */ - g_assert_cmphex(qtest_readl(s, base + HACE_CMD), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); - - - /* Check that the address masking is correct */ - qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, expected= ->src); - - qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, expec= ted->dest); - - qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, exp= ected->len); - - /* Reset to zero */ - qtest_writel(s, base + HACE_HASH_SRC, 0); - qtest_writel(s, base + HACE_HASH_DIGEST, 0); - qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); - - /* Check that all bits are now zero */ - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); - g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); - - qtest_quit(s); -} - /* ast2600 */ static void test_md5_ast2600(void) { - test_md5("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_md5("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha256_ast2600(void) { - test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha256_sg_ast2600(void) { - test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha512_ast2600(void) { - test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha512_sg_ast2600(void) { - test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 static void test_sha256_accum_ast2600(void) { - test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); } =20 static void test_sha512_accum_ast2600(void) { - test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); + aspeed_test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); } =20 static void test_addresses_ast2600(void) { - test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks); + aspeed_test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_mas= ks); } =20 /* ast2500 */ static void test_md5_ast2500(void) { - test_md5("-machine ast2500-evb", 0x1e6e3000, 0x80000000); + aspeed_test_md5("-machine ast2500-evb", 0x1e6e3000, 0x80000000); } =20 static void test_sha256_ast2500(void) { - test_sha256("-machine ast2500-evb", 0x1e6e3000, 0x80000000); + aspeed_test_sha256("-machine ast2500-evb", 0x1e6e3000, 0x80000000); } =20 static void test_sha512_ast2500(void) { - test_sha512("-machine ast2500-evb", 0x1e6e3000, 0x80000000); + aspeed_test_sha512("-machine ast2500-evb", 0x1e6e3000, 0x80000000); } =20 static void test_addresses_ast2500(void) { - test_addresses("-machine ast2500-evb", 0x1e6e3000, &ast2500_masks); + aspeed_test_addresses("-machine ast2500-evb", 0x1e6e3000, &ast2500_mas= ks); } =20 /* ast2400 */ static void test_md5_ast2400(void) { - test_md5("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); + aspeed_test_md5("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); } =20 static void test_sha256_ast2400(void) { - test_sha256("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); + aspeed_test_sha256("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); } =20 static void test_sha512_ast2400(void) { - test_sha512("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); + aspeed_test_sha512("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); } =20 static void test_addresses_ast2400(void) { - test_addresses("-machine palmetto-bmc", 0x1e6e3000, &ast2400_masks); + aspeed_test_addresses("-machine palmetto-bmc", 0x1e6e3000, &ast2400_ma= sks); } =20 int main(int argc, char **argv) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 8a6243382a..62fc8f9868 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -383,6 +383,7 @@ qtests =3D { 'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'), 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'), 'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'), + 'aspeed_hace-test': files('aspeed-hace-utils.c', 'aspeed_hace-test.c'), } =20 if vnc.found() --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549476; cv=none; d=zohomail.com; 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Fri, 21 Mar 2025 17:26:28 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 14/22] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations Date: Fri, 21 Mar 2025 17:26:10 +0800 Message-ID: <20250321092623.2097234-15-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549479915019100 Content-Type: text/plain; charset="utf-8" The digest_addr is set to "src_addr + 0x1000000", where src_addr is the DRAM base address. However, the value 0x1000000 (16MB) is too large because the AST1030 does not support DRAM, and its SRAM size is only 768KB. A range size of 0x1000 (64KB) is sufficient for HACE test cases, as the test vector size does not exceed 64KB. Updates: 1. Direct Access Mode Update digest_addr to "src_addr + 0x1000" in the following functions: aspeed_test_md5 aspeed_test_sha256 aspeed_test_sha512 2. Scatter-Gather (SG) Mode Update source address for different SG buffer addresses in the following functions: src_addr1 =3D src_addr + 0x1000 src_addr2 =3D src_addr + 0x2000 src_addr3 =3D src_addr + 0x3000 digest_addr =3D src_addr + 0x4000 aspeed_test_sha256_sg aspeed_test_sha512_sg 3. ACC Mode Update Update the SG List start address: src_addr + 0x10000 Update the SG List buffer size to 0x3000 (192KB). buffer_addr =3D src_addr + 0x10000 digest_addr =3D src_addr + 0x40000 Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 8582847945..8fbbba49c1 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -132,7 +132,7 @@ void aspeed_test_md5(const char *machine, const uint32_= t base, { QTestState *s =3D qtest_init(machine); =20 - uint32_t digest_addr =3D src_addr + 0x01000000; + uint32_t digest_addr =3D src_addr + 0x010000; uint8_t digest[16] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -166,7 +166,7 @@ void aspeed_test_sha256(const char *machine, const uint= 32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x10000; uint8_t digest[32] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -200,7 +200,7 @@ void aspeed_test_sha512(const char *machine, const uint= 32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x1000000; + const uint32_t digest_addr =3D src_addr + 0x10000; uint8_t digest[64] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -234,10 +234,10 @@ void aspeed_test_sha256_sg(const char *machine, const= uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t src_addr_1 =3D src_addr + 0x10000; + const uint32_t src_addr_2 =3D src_addr + 0x20000; + const uint32_t src_addr_3 =3D src_addr + 0x30000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), @@ -285,10 +285,10 @@ void aspeed_test_sha512_sg(const char *machine, const= uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x1000000; - const uint32_t src_addr_2 =3D src_addr + 0x2000000; - const uint32_t src_addr_3 =3D src_addr + 0x3000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t src_addr_1 =3D src_addr + 0x10000; + const uint32_t src_addr_2 =3D src_addr + 0x20000; + const uint32_t src_addr_3 =3D src_addr + 0x30000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), @@ -336,8 +336,8 @@ void aspeed_test_sha256_accum(const char *machine, cons= t uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t buffer_addr =3D src_addr + 0x10000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), @@ -377,8 +377,8 @@ void aspeed_test_sha512_accum(const char *machine, cons= t uint32_t base, { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x1000000; - const uint32_t digest_addr =3D src_addr + 0x4000000; + const uint32_t buffer_addr =3D src_addr + 0x10000; + const uint32_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174254946661189.90118490440375; Fri, 21 Mar 2025 02:31:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tvYfT-0008J3-GI; Fri, 21 Mar 2025 05:27:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYf7-0007Hk-QV; Fri, 21 Mar 2025 05:27:35 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYf5-0005EC-OY; Fri, 21 Mar 2025 05:27:33 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:29 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:29 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 15/22] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model Date: Fri, 21 Mar 2025 17:26:11 +0800 Message-ID: <20250321092623.2097234-16-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549467833019000 Content-Type: text/plain; charset="utf-8" Introduced SHA-384 test functions to verify hashing operations. Extended support for scatter-gather (`_sg`) and accumulation (`_accum`) tes= ts. Updated test result vectors for SHA-384 validation. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 6 ++ tests/qtest/aspeed-hace-utils.c | 168 +++++++++++++++++++++++++++++++- 2 files changed, 171 insertions(+), 3 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index 598577c69b..f4440561de 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -54,14 +54,20 @@ void aspeed_test_md5(const char *machine, const uint32_= t base, const uint32_t src_addr); void aspeed_test_sha256(const char *machine, const uint32_t base, const uint32_t src_addr); +void aspeed_test_sha384(const char *machine, const uint32_t base, + const uint32_t src_addr); void aspeed_test_sha512(const char *machine, const uint32_t base, const uint32_t src_addr); void aspeed_test_sha256_sg(const char *machine, const uint32_t base, const uint32_t src_addr); +void aspeed_test_sha384_sg(const char *machine, const uint32_t base, + const uint32_t src_addr); void aspeed_test_sha512_sg(const char *machine, const uint32_t base, const uint32_t src_addr); void aspeed_test_sha256_accum(const char *machine, const uint32_t base, const uint32_t src_addr); +void aspeed_test_sha384_accum(const char *machine, const uint32_t base, + const uint32_t src_addr); void aspeed_test_sha512_accum(const char *machine, const uint32_t base, const uint32_t src_addr); void aspeed_test_addresses(const char *machine, const uint32_t base, diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 8fbbba49c1..d3146898c2 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -16,7 +16,7 @@ * Expected results were generated using command line utitiles: * * echo -n -e 'abc' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done + * for hash in sha512sum sha384sum sha256sum md5sum; do $hash /tmp/test; = done * */ static const uint8_t test_vector[] =3D {0x61, 0x62, 0x63}; @@ -29,6 +29,12 @@ static const uint8_t test_result_sha512[] =3D { 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f}; =20 +static const uint8_t test_result_sha384[] =3D { + 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, 0xb5, 0xa0, 0x3d, 0x69, + 0x9a, 0xc6, 0x50, 0x07, 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, + 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, 0x80, 0x86, 0x07, 0x2b, + 0xa1, 0xe7, 0xcc, 0x23, 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7= }; + static const uint8_t test_result_sha256[] =3D { 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, @@ -45,7 +51,7 @@ static const uint8_t test_result_md5[] =3D { * Expected results were generated using command line utitiles: * * echo -n -e 'abcdefghijkl' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum; do $hash /tmp/test; done + * for hash in sha512sum sha384sum sha256sum; do $hash /tmp/test; done * */ static const uint8_t test_vector_sg1[] =3D {0x61, 0x62, 0x63, 0x64, 0x65, = 0x66}; @@ -60,6 +66,12 @@ static const uint8_t test_result_sg_sha512[] =3D { 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, 0xf8, 0x6d, 0xda, 0x2e}; =20 +static const uint8_t test_result_sg_sha384[] =3D { + 0x10, 0x3c, 0xa9, 0x6c, 0x06, 0xa1, 0xce, 0x79, 0x8f, 0x08, 0xf8, 0xef, + 0xf0, 0xdf, 0xb0, 0xcc, 0xdb, 0x56, 0x7d, 0x48, 0xb2, 0x85, 0xb2, 0x3d, + 0x0c, 0xd7, 0x73, 0x45, 0x46, 0x67, 0xa3, 0xc2, 0xfa, 0x5f, 0x1b, 0x58, + 0xd9, 0xcd, 0xf2, 0x32, 0x9b, 0xd9, 0x97, 0x97, 0x30, 0xbf, 0xaa, 0xff= }; + static const uint8_t test_result_sg_sha256[] =3D { 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, @@ -74,7 +86,7 @@ static const uint8_t test_result_sg_sha256[] =3D { * Expected results were generated using command line utitiles: * * echo -n -e 'abc' | dd of=3D/tmp/test - * for hash in sha512sum sha256sum; do $hash /tmp/test; done + * for hash in sha512sum sha384sum sha256sum; do $hash /tmp/test; done */ static const uint8_t test_vector_accum_512[] =3D { 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, @@ -94,6 +106,24 @@ static const uint8_t test_vector_accum_512[] =3D { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; =20 +static const uint8_t test_vector_accum_384[] =3D { + 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; + static const uint8_t test_vector_accum_256[] =3D { 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -112,6 +142,12 @@ static const uint8_t test_result_accum_sha512[] =3D { 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f}; =20 +static const uint8_t test_result_accum_sha384[] =3D { + 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, 0xb5, 0xa0, 0x3d, 0x69, + 0x9a, 0xc6, 0x50, 0x07, 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, + 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, 0x80, 0x86, 0x07, 0x2b, + 0xa1, 0xe7, 0xcc, 0x23, 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7= }; + static const uint8_t test_result_accum_sha256[] =3D { 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, @@ -195,6 +231,40 @@ void aspeed_test_sha256(const char *machine, const uin= t32_t base, qtest_quit(s); } =20 +void aspeed_test_sha384(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t digest_addr =3D src_addr + 0x10000; + uint8_t digest[32] =3D {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, + HACE_ALGO_SHA384); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sha384, sizeof(digest)); + + qtest_quit(s); +} + void aspeed_test_sha512(const char *machine, const uint32_t base, const uint32_t src_addr) { @@ -280,6 +350,57 @@ void aspeed_test_sha256_sg(const char *machine, const = uint32_t base, qtest_quit(s); } =20 +void aspeed_test_sha384_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t src_addr_1 =3D src_addr + 0x10000; + const uint32_t src_addr_2 =3D src_addr + 0x20000; + const uint32_t src_addr_3 =3D src_addr + 0x30000; + const uint32_t digest_addr =3D src_addr + 0x40000; + uint8_t digest[64] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_sg1)), + cpu_to_le32(src_addr_1) }, + { cpu_to_le32(sizeof(test_vector_sg2)), + cpu_to_le32(src_addr_2) }, + { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), + cpu_to_le32(src_addr_3) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)= ); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)= ); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)= ); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA384 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha384, sizeof(digest)); + + qtest_quit(s); +} + void aspeed_test_sha512_sg(const char *machine, const uint32_t base, const uint32_t src_addr) { @@ -372,6 +493,47 @@ void aspeed_test_sha256_accum(const char *machine, con= st uint32_t base, qtest_quit(s); } =20 +void aspeed_test_sha384_accum(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s =3D qtest_init(machine); + + const uint32_t buffer_addr =3D src_addr + 0x10000; + const uint32_t digest_addr =3D src_addr + 0x40000; + uint8_t digest[64] =3D {0}; + struct AspeedSgList array[] =3D { + { cpu_to_le32(sizeof(test_vector_accum_384) | SG_LIST_LEN_LAST), + cpu_to_le32(buffer_addr) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, buffer_addr, test_vector_accum_384, + sizeof(test_vector_accum_384)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, sizeof(test_vector_accum_384), + digest_addr, HACE_ALGO_SHA384 | HACE_SG_EN | HACE_ACCUM_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), =3D=3D, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_accum_sha384, sizeof(digest)); + + qtest_quit(s); +} + void aspeed_test_sha512_accum(const char *machine, const uint32_t base, const uint32_t src_addr) { --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549461; cv=none; d=zohomail.com; s=zohoarc; b=ngeYAMhYX9FFDBc0S4rm8Lzgvh5SXKl/0kGkA8wNnaN/fDKMLKP+bxzfaYs6Le+ha6IGoDuiBo9Dq772PdL3PZQY7AvDP+yByHEr+CoMJxBGZB6pFumFf3jwnO7IVGqBA0KLX5+djdd59kjkKc7ZIAyXhf1+KNNKL1h9IueYD/8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549461; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 21 Mar 2025 05:27:35 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:29 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:29 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 16/22] test/qtest/hace: Add SHA-384 tests for AST2600 Date: Fri, 21 Mar 2025 17:26:12 +0800 Message-ID: <20250321092623.2097234-17-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549464062019000 Content-Type: text/plain; charset="utf-8" Introduced "test_sha384_ast2600" to validate SHA-384 hashing. Added "test_sha384_sg_ast2600" for scatter-gather SHA-384 verification. Implemented "test_sha384_accum_ast2600" to test SHA-384 accumulation. Registered new test cases in "main" to ensure execution. Signed-off-by: Jamin Lin --- tests/qtest/aspeed_hace-test.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index 42a306af2a..ab0c98330e 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -44,6 +44,16 @@ static void test_sha256_sg_ast2600(void) aspeed_test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); } =20 +static void test_sha384_ast2600(void) +{ + aspeed_test_sha384("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + +static void test_sha384_sg_ast2600(void) +{ + aspeed_test_sha384_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + static void test_sha512_ast2600(void) { aspeed_test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); @@ -59,6 +69,11 @@ static void test_sha256_accum_ast2600(void) aspeed_test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); } =20 +static void test_sha384_accum_ast2600(void) +{ + aspeed_test_sha384_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); +} + static void test_sha512_accum_ast2600(void) { aspeed_test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x8000000= 0); @@ -117,13 +132,16 @@ int main(int argc, char **argv) =20 qtest_add_func("ast2600/hace/addresses", test_addresses_ast2600); qtest_add_func("ast2600/hace/sha512", test_sha512_ast2600); + qtest_add_func("ast2600/hace/sha384", test_sha384_ast2600); qtest_add_func("ast2600/hace/sha256", test_sha256_ast2600); qtest_add_func("ast2600/hace/md5", test_md5_ast2600); =20 qtest_add_func("ast2600/hace/sha512_sg", test_sha512_sg_ast2600); + qtest_add_func("ast2600/hace/sha384_sg", test_sha384_sg_ast2600); qtest_add_func("ast2600/hace/sha256_sg", test_sha256_sg_ast2600); =20 qtest_add_func("ast2600/hace/sha512_accum", test_sha512_accum_ast2600); + qtest_add_func("ast2600/hace/sha384_accum", test_sha384_accum_ast2600); qtest_add_func("ast2600/hace/sha256_accum", test_sha256_accum_ast2600); =20 qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500); --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 21 Mar 2025 17:26:29 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:29 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 17/22] test/qtest/hace: Add tests for AST1030 Date: Fri, 21 Mar 2025 17:26:13 +0800 Message-ID: <20250321092623.2097234-18-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549321154019100 Content-Type: text/plain; charset="utf-8" The HACE model in AST2600 and AST1030 is identical. Referencing the AST2600 test cases, new tests have been created for AST1030. Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5. Added scatter-gather and accumulation test variants. For AST1030, the HACE controller base address starts at "0x7e6d0000", and t= he SDRAM start address is "0x0". Signed-off-by: Jamin Lin --- tests/qtest/aspeed_hace-test.c | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index ab0c98330e..31890d574e 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -10,6 +10,12 @@ #include "qemu/bitops.h" #include "aspeed-hace-utils.h" =20 +static const struct AspeedMasks ast1030_masks =3D { + .src =3D 0x7fffffff, + .dest =3D 0x7ffffff8, + .len =3D 0x0fffffff, +}; + static const struct AspeedMasks ast2600_masks =3D { .src =3D 0x7fffffff, .dest =3D 0x7ffffff8, @@ -28,6 +34,62 @@ static const struct AspeedMasks ast2400_masks =3D { .len =3D 0x0fffffff, }; =20 +/* ast1030 */ +static void test_md5_ast1030(void) +{ + aspeed_test_md5("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha256_ast1030(void) +{ + aspeed_test_sha256("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha256_sg_ast1030(void) +{ + aspeed_test_sha256_sg("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha384_ast1030(void) +{ + aspeed_test_sha384("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha384_sg_ast1030(void) +{ + aspeed_test_sha384_sg("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha512_ast1030(void) +{ + aspeed_test_sha512("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha512_sg_ast1030(void) +{ + aspeed_test_sha512_sg("-machine ast1030-evb", 0x7e6d0000, 0x00000000); +} + +static void test_sha256_accum_ast1030(void) +{ + aspeed_test_sha256_accum("-machine ast1030-evb", 0x7e6d0000, 0x0000000= 0); +} + +static void test_sha384_accum_ast1030(void) +{ + aspeed_test_sha384_accum("-machine ast1030-evb", 0x7e6d0000, 0x0000000= 0); +} + +static void test_sha512_accum_ast1030(void) +{ + aspeed_test_sha512_accum("-machine ast1030-evb", 0x7e6d0000, 0x0000000= 0); +} + +static void test_addresses_ast1030(void) +{ + aspeed_test_addresses("-machine ast1030-evb", 0x7e6d0000, &ast1030_mas= ks); +} + /* ast2600 */ static void test_md5_ast2600(void) { @@ -130,6 +192,20 @@ int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); =20 + qtest_add_func("ast1030/hace/addresses", test_addresses_ast1030); + qtest_add_func("ast1030/hace/sha512", test_sha512_ast1030); + qtest_add_func("ast1030/hace/sha384", test_sha384_ast1030); + qtest_add_func("ast1030/hace/sha256", test_sha256_ast1030); + qtest_add_func("ast1030/hace/md5", test_md5_ast1030); + + qtest_add_func("ast1030/hace/sha512_sg", test_sha512_sg_ast1030); + qtest_add_func("ast1030/hace/sha384_sg", test_sha384_sg_ast1030); + qtest_add_func("ast1030/hace/sha256_sg", test_sha256_sg_ast1030); + + qtest_add_func("ast1030/hace/sha512_accum", test_sha512_accum_ast1030); + qtest_add_func("ast1030/hace/sha384_accum", test_sha384_accum_ast1030); + qtest_add_func("ast1030/hace/sha256_accum", test_sha256_accum_ast1030); + qtest_add_func("ast2600/hace/addresses", test_addresses_ast2600); qtest_add_func("ast2600/hace/sha512", test_sha512_ast2600); qtest_add_func("ast2600/hace/sha384", test_sha384_ast2600); --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549463; cv=none; d=zohomail.com; s=zohoarc; b=EDjPdMwJr3if0nfZxUqWCKb68MdLS4/26ZAlxmY0NouDXD7yUbnOzWFB15pExPEe16Vlg76EOZjfyzaSllW2XXBhU0zDBpB4MRgF2ZFGnrhymDkV/FVT9Ru3TfSbqpDp4MxBBHgMQI04GEwX7WUHG0upofspKw5+/ko34u4o2Ps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549463; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ue5BEwpzBa6QOnWJbqXrv2dCki1jrKRmbOGKO/ey/2Y=; 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Fri, 21 Mar 2025 05:28:02 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:30 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:30 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 18/22] test/qtest/hace: Update source data and digest data type to 64-bit Date: Fri, 21 Mar 2025 17:26:14 +0800 Message-ID: <20250321092623.2097234-19-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549465862019100 Content-Type: text/plain; charset="utf-8" Currently, the hash data source and digest result buffer addresses are set = to 32-bit. However, the AST2700 CPU is a 64-bit Cortex-A35 architecture, and i= ts DRAM base address is also 64-bit. To support AST2700, update the hash data source address and digest result b= uffer address to use 64-bit addressing. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 20 +++---- tests/qtest/aspeed-hace-utils.c | 96 ++++++++++++++++----------------- 2 files changed, 58 insertions(+), 58 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index f4440561de..0382570fa2 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -51,25 +51,25 @@ struct AspeedMasks { }; =20 void aspeed_test_md5(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha256(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha384(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha512(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha256_sg(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha384_sg(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha512_sg(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha256_accum(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha384_accum(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_sha512_accum(const char *machine, const uint32_t base, - const uint32_t src_addr); + const uint64_t src_addr); void aspeed_test_addresses(const char *machine, const uint32_t base, const struct AspeedMasks *expected); =20 diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index d3146898c2..f39bb8ea48 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -153,22 +153,22 @@ static const uint8_t test_result_accum_sha256[] =3D { 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; =20 -static void write_regs(QTestState *s, uint32_t base, uint32_t src, - uint32_t length, uint32_t out, uint32_t method) +static void write_regs(QTestState *s, uint32_t base, uint64_t src, + uint32_t length, uint64_t out, uint32_t method) { - qtest_writel(s, base + HACE_HASH_SRC, src); - qtest_writel(s, base + HACE_HASH_DIGEST, out); + qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32)); + qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0, 32)); qtest_writel(s, base + HACE_HASH_DATA_LEN, length); qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); } =20 void aspeed_test_md5(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) =20 { QTestState *s =3D qtest_init(machine); =20 - uint32_t digest_addr =3D src_addr + 0x010000; + uint64_t digest_addr =3D src_addr + 0x010000; uint8_t digest[16] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -198,11 +198,11 @@ void aspeed_test_md5(const char *machine, const uint3= 2_t base, } =20 void aspeed_test_sha256(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x10000; uint8_t digest[32] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -232,11 +232,11 @@ void aspeed_test_sha256(const char *machine, const ui= nt32_t base, } =20 void aspeed_test_sha384(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x10000; uint8_t digest[32] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -266,11 +266,11 @@ void aspeed_test_sha384(const char *machine, const ui= nt32_t base, } =20 void aspeed_test_sha512(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t digest_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x10000; uint8_t digest[64] =3D {0}; =20 /* Check engine is idle, no busy or irq bits set */ @@ -300,22 +300,22 @@ void aspeed_test_sha512(const char *machine, const ui= nt32_t base, } =20 void aspeed_test_sha256_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x10000; - const uint32_t src_addr_2 =3D src_addr + 0x20000; - const uint32_t src_addr_3 =3D src_addr + 0x30000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t src_addr_1 =3D src_addr + 0x10000; + const uint64_t src_addr_2 =3D src_addr + 0x20000; + const uint64_t src_addr_3 =3D src_addr + 0x30000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, + cpu_to_le64(src_addr_1) }, { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, + cpu_to_le64(src_addr_2) }, { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, + cpu_to_le64(src_addr_3) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -351,22 +351,22 @@ void aspeed_test_sha256_sg(const char *machine, const= uint32_t base, } =20 void aspeed_test_sha384_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x10000; - const uint32_t src_addr_2 =3D src_addr + 0x20000; - const uint32_t src_addr_3 =3D src_addr + 0x30000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t src_addr_1 =3D src_addr + 0x10000; + const uint64_t src_addr_2 =3D src_addr + 0x20000; + const uint64_t src_addr_3 =3D src_addr + 0x30000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, + cpu_to_le64(src_addr_1) }, { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, + cpu_to_le64(src_addr_2) }, { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, + cpu_to_le64(src_addr_3) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -402,22 +402,22 @@ void aspeed_test_sha384_sg(const char *machine, const= uint32_t base, } =20 void aspeed_test_sha512_sg(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t src_addr_1 =3D src_addr + 0x10000; - const uint32_t src_addr_2 =3D src_addr + 0x20000; - const uint32_t src_addr_3 =3D src_addr + 0x30000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t src_addr_1 =3D src_addr + 0x10000; + const uint64_t src_addr_2 =3D src_addr + 0x20000; + const uint64_t src_addr_3 =3D src_addr + 0x30000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_sg1)), - cpu_to_le32(src_addr_1) }, + cpu_to_le64(src_addr_1) }, { cpu_to_le32(sizeof(test_vector_sg2)), - cpu_to_le32(src_addr_2) }, + cpu_to_le64(src_addr_2) }, { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), - cpu_to_le32(src_addr_3) }, + cpu_to_le64(src_addr_3) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -453,16 +453,16 @@ void aspeed_test_sha512_sg(const char *machine, const= uint32_t base, } =20 void aspeed_test_sha256_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x10000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t buffer_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[32] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, + cpu_to_le64(buffer_addr) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -494,16 +494,16 @@ void aspeed_test_sha256_accum(const char *machine, co= nst uint32_t base, } =20 void aspeed_test_sha384_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x10000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t buffer_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_384) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, + cpu_to_le64(buffer_addr) }, }; =20 /* Check engine is idle, no busy or irq bits set */ @@ -535,16 +535,16 @@ void aspeed_test_sha384_accum(const char *machine, co= nst uint32_t base, } =20 void aspeed_test_sha512_accum(const char *machine, const uint32_t base, - const uint32_t src_addr) + const uint64_t src_addr) { QTestState *s =3D qtest_init(machine); =20 - const uint32_t buffer_addr =3D src_addr + 0x10000; - const uint32_t digest_addr =3D src_addr + 0x40000; + const uint64_t buffer_addr =3D src_addr + 0x10000; + const uint64_t digest_addr =3D src_addr + 0x40000; uint8_t digest[64] =3D {0}; struct AspeedSgList array[] =3D { { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), - cpu_to_le32(buffer_addr) }, + cpu_to_le64(buffer_addr) }, }; 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Fri, 21 Mar 2025 05:28:06 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:30 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:30 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 19/22] test/qtest/hace: Support 64-bit source and digest addresses for AST2700 Date: Fri, 21 Mar 2025 17:26:15 +0800 Message-ID: <20250321092623.2097234-20-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549413664019000 Content-Type: text/plain; charset="utf-8" Added "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI", "HACE_HASH_KEY_BUFF_HI" registers to store upper 32 bits. Updated "write_regs" to handle 64-bit source and digest addresses. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 3 +++ tests/qtest/aspeed-hace-utils.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index 0382570fa2..d8684d3f83 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -36,6 +36,9 @@ #define HACE_HASH_KEY_BUFF 0x28 #define HACE_HASH_DATA_LEN 0x2c #define HACE_HASH_CMD 0x30 +#define HACE_HASH_SRC_HI 0x90 +#define HACE_HASH_DIGEST_HI 0x94 +#define HACE_HASH_KEY_BUFF_HI 0x98 =20 /* Scatter-Gather Hash */ #define SG_LIST_LEN_LAST BIT(31) diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index f39bb8ea48..8d9c464f72 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -157,7 +157,9 @@ static void write_regs(QTestState *s, uint32_t base, ui= nt64_t src, uint32_t length, uint64_t out, uint32_t method) { qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32)); + qtest_writel(s, base + HACE_HASH_SRC_HI, extract64(src, 32, 32)); qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0, 32)); + qtest_writel(s, base + HACE_HASH_DIGEST_HI, extract64(out, 32, 32)= ); qtest_writel(s, base + HACE_HASH_DATA_LEN, length); qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); } --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549478; cv=none; d=zohomail.com; s=zohoarc; b=D1fFgWnHiR8t+EzVg73PQ3HY4BPB+sIQebyX+iGEALXrn6kQE1joA/gQLTrg3/VUQJy7gnbYzT+W+lfKDdRPWRLj36/fWGw5NglExSqNscyaw72M4hJFytLKfz+0cvh8ABRW9CgkCMK+J7XHMWSK/NPBL6Dk6G0PWk8yAP8hx5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742549478; 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Fri, 21 Mar 2025 05:28:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYfk-0001M5-Nu; Fri, 21 Mar 2025 05:28:13 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tvYfh-0005jH-P2; Fri, 21 Mar 2025 05:28:12 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 21 Mar 2025 17:26:30 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 21 Mar 2025 17:26:30 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 20/22] test/qtest/hace: Support to test upper 32 bits of digest and source addresses Date: Fri, 21 Mar 2025 17:26:16 +0800 Message-ID: <20250321092623.2097234-21-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549480480019000 Content-Type: text/plain; charset="utf-8" Added "src_hi" and "dest_hi" fields to "AspeedMasks" for 64-bit addresses t= est. Updated "aspeed_test_addresses" to validate "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI". Ensured correct masking of 64-bit addresses by checking both lower and upper 32-bit registers. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 2 ++ tests/qtest/aspeed-hace-utils.c | 15 ++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index d8684d3f83..de8055a1db 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -51,6 +51,8 @@ struct AspeedMasks { uint32_t src; uint32_t dest; uint32_t len; + uint32_t src_hi; + uint32_t dest_hi; }; =20 void aspeed_test_md5(const char *machine, const uint32_t base, diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index 8d9c464f72..fc209353f3 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -588,30 +588,43 @@ void aspeed_test_addresses(const char *machine, const= uint32_t base, */ g_assert_cmphex(qtest_readl(s, base + HACE_CMD), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 - /* Check that the address masking is correct */ qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, expected= ->src); =20 + qtest_writel(s, base + HACE_HASH_SRC_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), + =3D=3D, expected->src_hi); + qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, expected->dest); =20 + qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, + expected->dest_hi); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, expected->len); =20 /* Reset to zero */ qtest_writel(s, base + HACE_HASH_SRC, 0); + qtest_writel(s, base + HACE_HASH_SRC_HI, 0); qtest_writel(s, base + HACE_HASH_DIGEST, 0); + qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0); qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); =20 /* Check that all bits are now zero */ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 qtest_quit(s); --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549318; cv=none; d=zohomail.com; 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Fri, 21 Mar 2025 17:26:31 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 21/22] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses Date: Fri, 21 Mar 2025 17:26:17 +0800 Message-ID: <20250321092623.2097234-22-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> References: <20250321092623.2097234-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549321163019100 Content-Type: text/plain; charset="utf-8" Added "key" and "key_hi" fields to "AspeedMasks" for 64-bit addresses test. Updated "aspeed_test_addresses" to validate "HACE_HASH_KEY_BUFF" and "HACE_HASH_KEY_BUFF_HI". Ensured correct masking of 64-bit addresses by checking both lower and upper 32-bit registers. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 2 ++ tests/qtest/aspeed-hace-utils.c | 14 ++++++++++++++ tests/qtest/aspeed_hace-test.c | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-util= s.h index de8055a1db..c8b2ec45af 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -50,9 +50,11 @@ struct AspeedSgList { struct AspeedMasks { uint32_t src; uint32_t dest; + uint32_t key; uint32_t len; uint32_t src_hi; uint32_t dest_hi; + uint32_t key_hi; }; =20 void aspeed_test_md5(const char *machine, const uint32_t base, diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-util= s.c index fc209353f3..a5ece614ed 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -591,6 +591,8 @@ void aspeed_test_addresses(const char *machine, const u= int32_t base, g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), =3D=3D, = 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 /* Check that the address masking is correct */ @@ -609,6 +611,14 @@ void aspeed_test_addresses(const char *machine, const = uint32_t base, g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, expected->dest_hi); =20 + qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), =3D=3D, + expected->key); + + qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), =3D=3D, + expected->key_hi); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, expected->len); @@ -618,6 +628,8 @@ void aspeed_test_addresses(const char *machine, const u= int32_t base, qtest_writel(s, base + HACE_HASH_SRC_HI, 0); qtest_writel(s, base + HACE_HASH_DIGEST, 0); qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0); + qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0); + qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0); qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); =20 /* Check that all bits are now zero */ @@ -625,6 +637,8 @@ void aspeed_test_addresses(const char *machine, const u= int32_t base, g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), =3D=3D, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), =3D=3D, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), =3D=3D, = 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), =3D=3D, 0); =20 qtest_quit(s); diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c index 31890d574e..38777020ca 100644 --- a/tests/qtest/aspeed_hace-test.c +++ b/tests/qtest/aspeed_hace-test.c @@ -13,24 +13,28 @@ static const struct AspeedMasks ast1030_masks =3D { .src =3D 0x7fffffff, .dest =3D 0x7ffffff8, + .key =3D 0x7ffffff8, .len =3D 0x0fffffff, }; =20 static const struct AspeedMasks ast2600_masks =3D { .src =3D 0x7fffffff, .dest =3D 0x7ffffff8, + .key =3D 0x7ffffff8, .len =3D 0x0fffffff, }; =20 static const struct AspeedMasks ast2500_masks =3D { .src =3D 0x3fffffff, .dest =3D 0x3ffffff8, + .key =3D 0x3fffffc0, .len =3D 0x0fffffff, }; =20 static const struct AspeedMasks ast2400_masks =3D { .src =3D 0x0fffffff, .dest =3D 0x0ffffff8, + .key =3D 0x0fffffc0, .len =3D 0x0fffffff, }; =20 --=20 2.43.0 From nobody Tue Apr 1 08:51:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1742549445; cv=none; d=zohomail.com; s=zohoarc; b=dPRwP2+yJoVA8bk47qSaAZaQhbwFgFszdiSgk1I5X6q75pF4oTvCt78xep+cYRcPBK7SylKSF3HWIuJmCtXlTFYr6IOZHSuwp+chGZ3lOZdHj8M2jw8NJIPW9fB+o4pMgW/p6CCMv+ftuaulJvDtpsIFbm1W1dIUc5afW0LCc5U= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742549448032019100 Content-Type: text/plain; charset="utf-8" The HACE models in AST2600 and AST2700 are nearly identical. Based on the AST2600 test cases, new tests have been added for AST2700. Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5. Added scatter-gather and accumulation test variants. For AST2700, the HACE controller base address starts at "0x12070000", and the DRAM start address is "0x4_00000000". Signed-off-by: Jamin Lin --- tests/qtest/ast2700-hace-test.c | 98 +++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 4 +- 2 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/ast2700-hace-test.c diff --git a/tests/qtest/ast2700-hace-test.c b/tests/qtest/ast2700-hace-tes= t.c new file mode 100644 index 0000000000..a400e2962b --- /dev/null +++ b/tests/qtest/ast2700-hace-test.c @@ -0,0 +1,98 @@ +/* + * QTest testcase for the ASPEED Hash and Crypto Engine + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2025 ASPEED Technology Inc. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "qemu/bitops.h" +#include "aspeed-hace-utils.h" + +static const struct AspeedMasks as2700_masks =3D { + .src =3D 0x7fffffff, + .dest =3D 0x7ffffff8, + .key =3D 0x7ffffff8, + .len =3D 0x0fffffff, + .src_hi =3D 0x00000003, + .dest_hi =3D 0x00000003, + .key_hi =3D 0x00000003, +}; + +/* ast2700 */ +static void test_md5_ast2700(void) +{ + aspeed_test_md5("-machine ast2700a1-evb", 0x12070000, 0x400000000); +} + +static void test_sha256_ast2700(void) +{ + aspeed_test_sha256("-machine ast2700a1-evb", 0x12070000, 0x400000000); +} + +static void test_sha256_sg_ast2700(void) +{ + aspeed_test_sha256_sg("-machine ast2700a1-evb", 0x12070000, 0x40000000= 0); +} + +static void test_sha384_ast2700(void) +{ + aspeed_test_sha384("-machine ast2700a1-evb", 0x12070000, 0x400000000); +} + +static void test_sha384_sg_ast2700(void) +{ + aspeed_test_sha384_sg("-machine ast2700a1-evb", 0x12070000, 0x40000000= 0); +} + +static void test_sha512_ast2700(void) +{ + aspeed_test_sha512("-machine ast2700a1-evb", 0x12070000, 0x400000000); +} + +static void test_sha512_sg_ast2700(void) +{ + aspeed_test_sha512_sg("-machine ast2700a1-evb", 0x12070000, 0x40000000= 0); +} + +static void test_sha256_accum_ast2700(void) +{ + aspeed_test_sha256_accum("-machine ast2700a1-evb", 0x12070000, 0x40000= 0000); +} + +static void test_sha384_accum_ast2700(void) +{ + aspeed_test_sha384_accum("-machine ast2700a1-evb", 0x12070000, 0x40000= 0000); +} + +static void test_sha512_accum_ast2700(void) +{ + aspeed_test_sha512_accum("-machine ast2700a1-evb", 0x12070000, 0x40000= 0000); +} + +static void test_addresses_ast2700(void) +{ + aspeed_test_addresses("-machine ast2700a1-evb", 0x12070000, &as2700_ma= sks); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("ast2700/hace/addresses", test_addresses_ast2700); + qtest_add_func("ast2700/hace/sha512", test_sha512_ast2700); + qtest_add_func("ast2700/hace/sha384", test_sha384_ast2700); + qtest_add_func("ast2700/hace/sha256", test_sha256_ast2700); + qtest_add_func("ast2700/hace/md5", test_md5_ast2700); + + qtest_add_func("ast2700/hace/sha512_sg", test_sha512_sg_ast2700); + qtest_add_func("ast2700/hace/sha384_sg", test_sha384_sg_ast2700); + qtest_add_func("ast2700/hace/sha256_sg", test_sha256_sg_ast2700); + + qtest_add_func("ast2700/hace/sha512_accum", test_sha512_accum_ast2700); + qtest_add_func("ast2700/hace/sha384_accum", test_sha384_accum_ast2700); + qtest_add_func("ast2700/hace/sha256_accum", test_sha256_accum_ast2700); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 62fc8f9868..253d37f7bd 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -218,7 +218,8 @@ qtests_aspeed =3D \ 'aspeed_gpio-test'] qtests_aspeed64 =3D \ ['ast2700-gpio-test', - 'ast2700-smc-test'] + 'ast2700-smc-test', + 'ast2700-hace-test'] =20 qtests_stm32l4x5 =3D \ ['stm32l4x5_exti-test', @@ -384,6 +385,7 @@ qtests =3D { 'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'), 'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'), 'aspeed_hace-test': files('aspeed-hace-utils.c', 'aspeed_hace-test.c'), + 'ast2700-hace-test': files('aspeed-hace-utils.c', 'ast2700-hace-test.c'), } =20 if vnc.found() --=20 2.43.0