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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: qemu-devel@nongnu.org
Cc: kvm@vger.kernel.org, qemu-arm@nongnu.org,
Peter Maydell <peter.maydell@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
Richard Henderson <richard.henderson@linaro.org>,
=?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org>,
Pierrick Bouvier <pierrick.bouvier@linaro.org>
Subject: [PATCH v2 23/30] target/arm/cpu: remove inline stubs for aarch32
emulation
Date: Thu, 20 Mar 2025 15:29:55 -0700
Message-Id: <20250320223002.2915728-24-pierrick.bouvier@linaro.org>
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Directly condition associated calls in target/arm/helper.c for now.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 8 --------
target/arm/helper.c | 6 ++++++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b1c3e463267..c1a0faed3ad 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1222,7 +1222,6 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f,=
CPUState *cs,
*/
void arm_emulate_firmware_reset(CPUState *cpustate, int target_el);
=20
-#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
@@ -1254,13 +1253,6 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, u=
int64_t *src, int nr)
#endif
}
=20
-#else
-static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
-static inline void aarch64_sve_change_el(CPUARMState *env, int o,
- int n, bool a)
-{ }
-#endif
-
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
=20
diff --git a/target/arm/helper.c b/target/arm/helper.c
index fa23e309040..73e98532c03 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6564,7 +6564,9 @@ static void zcr_write(CPUARMState *env, const ARMCPRe=
gInfo *ri,
*/
new_len =3D sve_vqm1_for_el(env, cur_el);
if (new_len < old_len) {
+#ifdef TARGET_AARCH64
aarch64_sve_narrow_vq(env, new_len + 1);
+#endif
}
}
=20
@@ -10648,7 +10650,9 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *=
cs)
* Note that new_el can never be 0. If cur_el is 0, then
* el0_a64 is is_a64(), else el0_a64 is ignored.
*/
+#ifdef TARGET_AARCH64
aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+#endif
}
=20
if (cur_el < new_el) {
@@ -11665,7 +11669,9 @@ void aarch64_sve_change_el(CPUARMState *env, int ol=
d_el,
=20
/* When changing vector length, clear inaccessible state. */
if (new_len < old_len) {
+#ifdef TARGET_AARCH64
aarch64_sve_narrow_vq(env, new_len + 1);
+#endif
}
}
#endif
--=20
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