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([38.39.164.180]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22780f4581csm3370145ad.59.2025.03.20.15.30.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Mar 2025 15:30:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742509834; x=1743114634; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9ozZ2STeyLcJfOi2HO38PmZ1SSe1ZJ6WASMV/GdeD4Q=; b=Exaa2x43Pt35lxK6xlGOomDqkBGws0dl0rqbXOOFoPdoP+9xTF6SxfK9jrplX1T/F6 Db3cTTF1JUlYJMY6NdsIkk8PV1t4E8WgZUr/+Ml+mvtu1DRgb/WrCR44w3q32AfuxPuh XEVV383VY4pBj0A4YHH933+iUFisCkRXN1yZm9pmfdzvoa0SlakEN2LVMAQKOb2UAy3Y ga02z+q/VqxVdmnWU/L07Gyw/ZevgOFr79Z5yIqhfqOm+WjkwSNKOArRH2RAwwglim8z 4la+NCIVquVNmS6eDJMSDdFXn9bAMl/bWBQPB4FCt/rRftguEvB9jgTxcroG8lS4x/uM mvFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742509834; x=1743114634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9ozZ2STeyLcJfOi2HO38PmZ1SSe1ZJ6WASMV/GdeD4Q=; b=YMgX768lD6O1ZE7swnFKFeVaexpf3uKtakjzDEJWJdMItXjtEv5yyAt3vPrHqXUEAe 1qKEHVkm3sPwtQrSERZ4lFhIBciU7eYTR2qIEx7E2iGWQ9EGu53gpx4Ga8Iht4vaDGXj RucKxDAjlWDuJhQ+y+7WF/+Bl1j5iBGylnj+PoLHYNdUGFaGddlXwAC6Sr0PHygF9KwU 9j5I3xrU6DVUSByWSkWxhWyJzQDXZvrxw4qAM4+Tznso2Wrn4U7zObjGL8Pwm0173zBq jf1PjjNgLQIFw9KHSIUU0aVMN6TzjhtpZkvTJ/ksOf2/8E2M6KI0TknoQiK0tdu8s4bZ JJig== X-Gm-Message-State: AOJu0YwmZ9rsEKSraFddZajuAh+gSJQeQ0stl54VOTK9/n+4GXHz70mw Jh/VkS0vgiuogtK3pNiZFSa2LZEoL5STYUr8zip0PwMdNlpz6DgFDODxHXp6Ay1nngsqS11gEY4 e X-Gm-Gg: ASbGnctVLryfdYOmUtraDJkOJFamYKnoO94G6PcYO7uJH7JvcUzg6/bOSjFQfk/5etG tWujMH0eHF3+Mwj9mm9wQr7kf3OjbZmBhXAvKh7W0h3Z+wiUdtvRLfR0/v2exHzr2zjgFbXmZ7E HyDDCLJtqNOX2iuwStDolzSbZxmVpGJ+tYhGBurB6QlODD5Nq+LDdLEegyZkyMlJfUJ0HzGMe9X mZ7V6k/4/hIPO3SLMc7LC3QSat9EoyKEKNAPYMkqsFyLJa3bVhy7yEd96mMJTNn+190VdxoR1Wz ayOPsl0+XDz8jkfqOomBS71+5x5Ah/9GoNfoKcE3pQl7 X-Google-Smtp-Source: AGHT+IHe6GBkn4KwpLvaTmmjJDIDMzLP05ORVKokysmKy53aE2ukm/kc/ZOTuWlwBaafsA2wQaDJ1Q== X-Received: by 2002:a17:902:ea04:b0:224:1294:1d26 with SMTP id d9443c01a7336-22780c7afa2mr10974305ad.13.1742509833662; Thu, 20 Mar 2025 15:30:33 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier Subject: [PATCH v2 22/30] target/arm/cpu: define same set of registers for aarch32 and aarch64 Date: Thu, 20 Mar 2025 15:29:54 -0700 Message-Id: <20250320223002.2915728-23-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250320223002.2915728-1-pierrick.bouvier@linaro.org> References: <20250320223002.2915728-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742510207046019100 Content-Type: text/plain; charset="utf-8" To eliminate TARGET_AARCH64, we need to make various definitions common between 32 and 64 bit Arm targets. Added registers are used only by aarch64 code, and the only impact is on the size of CPUARMState, and added zarray (ARMVectorReg zarray[ARM_MAX_VQ * 16]) member (+64KB) It could be eventually possible to allocate this array only for aarch64 emulation, but I'm not sure it's worth the hassle to save a few KB per vcpu. Running qemu-system takes already several hundreds of MB of (resident) memory, and qemu-user takes dozens of MB of (resident) memory anyway. As part of this, we define ARM_MAX_VQ once for aarch32 and aarch64, which will affect zregs field for aarch32. This field is used for MVE and SVE implementations. MVE implementation is clipping index value to 0 or 1 for zregs[*].d[], so we should not touch the rest of data in this case anyway. This change is safe regarding migration, because aarch64 registers still have the same size, and for aarch32, only zregs is modified. Migration code explicitly specify a size of 2 for env.vfp.zregs[0].d, VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2). So extending the storage size has no impact. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/cpu.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cc975175c61..b1c3e463267 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -169,17 +169,12 @@ typedef struct ARMGenericTimer { * Align the data for use with TCG host vector operations. */ =20 -#ifdef TARGET_AARCH64 -# define ARM_MAX_VQ 16 -#else -# define ARM_MAX_VQ 1 -#endif +#define ARM_MAX_VQ 16 =20 typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; =20 -#ifdef TARGET_AARCH64 /* In AArch32 mode, predicate registers do not exist at all. */ typedef struct ARMPredicateReg { uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); @@ -189,7 +184,6 @@ typedef struct ARMPredicateReg { typedef struct ARMPACKey { uint64_t lo, hi; } ARMPACKey; -#endif =20 /* See the commentary above the TBFLAG field definitions. */ typedef struct CPUARMTBFlags { @@ -660,13 +654,11 @@ typedef struct CPUArchState { struct { ARMVectorReg zregs[32]; =20 -#ifdef TARGET_AARCH64 /* Store FFR as pregs[16] to make it easier to treat as any other.= */ #define FFR_PRED_NUM 16 ARMPredicateReg pregs[17]; /* Scratch space for aa64 sve predicate temporary. */ ARMPredicateReg preg_tmp; -#endif =20 /* We store these fpcsr fields separately for convenience. */ uint32_t qc[4] QEMU_ALIGNED(16); @@ -711,7 +703,6 @@ typedef struct CPUArchState { uint32_t cregs[16]; } iwmmxt; =20 -#ifdef TARGET_AARCH64 struct { ARMPACKey apia; ARMPACKey apib; @@ -743,7 +734,6 @@ typedef struct CPUArchState { * to keep the offsets into the rest of the structure smaller. */ ARMVectorReg zarray[ARM_MAX_VQ * 16]; -#endif =20 struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; --=20 2.39.5