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Wed, 19 Mar 2025 11:22:56 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 01/10] include/gdbstub: fix include guard in commands.h Date: Wed, 19 Mar 2025 18:22:46 +0000 Message-Id: <20250319182255.3096731-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408752222019100 Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/gdbstub/commands.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/gdbstub/commands.h b/include/gdbstub/commands.h index 40f0514fe9..bff3674872 100644 --- a/include/gdbstub/commands.h +++ b/include/gdbstub/commands.h @@ -1,5 +1,5 @@ #ifndef GDBSTUB_COMMANDS_H -#define GDBSTUB +#define GDBSTUB_COMMANDS_H =20 typedef void (*GdbCmdHandler)(GArray *params, void *user_ctx); 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Wed, 19 Mar 2025 11:23:02 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 02/10] gdbstub: introduce target independent gdb register helper Date: Wed, 19 Mar 2025 18:22:47 +0000 Message-Id: <20250319182255.3096731-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408668164019000 The current helper.h functions rely on hard coded assumptions about target endianess to use the tswap macros. We also end up double swapping a bunch of values if the target can run in multiple endianess modes. Avoid this by getting the target to pass the endianess and size via a MemOp and fixing up appropriately. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Pierrick Bouvier --- include/gdbstub/registers.h | 30 ++++++++++++++++++++++++++++++ gdbstub/gdbstub.c | 22 ++++++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 include/gdbstub/registers.h diff --git a/include/gdbstub/registers.h b/include/gdbstub/registers.h new file mode 100644 index 0000000000..4abc7a6ae7 --- /dev/null +++ b/include/gdbstub/registers.h @@ -0,0 +1,30 @@ +/* + * GDB Common Register Helpers + * + * Copyright (c) 2025 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef GDB_REGISTERS_H +#define GDB_REGISTERS_H + +#include "exec/memop.h" + +/** + * gdb_get_register_value() - get register value for gdb + * mo: size and endian MemOp + * buf: GByteArray to store in target order + * val: pointer to value in host order + * + * This replaces the previous legacy read functions with a single + * function to handle all sizes. Passing @mo allows the target mode to + * be taken into account and avoids using hard coded tswap() macros. + * + * Returns the number of bytes written to the array. + */ +int gdb_get_register_value(MemOp op, GByteArray *buf, uint8_t *val); + +#endif /* GDB_REGISTERS_H */ + + diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 282e13e163..3d7b1028e4 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -32,6 +32,7 @@ #include "exec/gdbstub.h" #include "gdbstub/commands.h" #include "gdbstub/syscalls.h" +#include "gdbstub/registers.h" #ifdef CONFIG_USER_ONLY #include "accel/tcg/vcpu-state.h" #include "gdbstub/user.h" @@ -45,6 +46,7 @@ #include "system/runstate.h" #include "exec/replay-core.h" #include "exec/hwaddr.h" +#include "exec/memop.h" =20 #include "internals.h" =20 @@ -551,6 +553,26 @@ static int gdb_write_register(CPUState *cpu, uint8_t *= mem_buf, int reg) return 0; } =20 +/* + * Target helper function to read value into GByteArray, target + * supplies the size and target endianess via the MemOp. + */ +int gdb_get_register_value(MemOp op, GByteArray *buf, uint8_t *val) +{ + size_t bytes =3D memop_size(op); + + if (op & MO_BSWAP) { + for ( int i =3D bytes ; i > 0; i--) { + g_byte_array_append(buf, &val[i - 1], 1); + }; + } else { + g_byte_array_append(buf, val, bytes); + } + + return bytes; +} + + static void gdb_register_feature(CPUState *cpu, int base_reg, gdb_get_reg_cb get_reg, gdb_set_reg_cb se= t_reg, const GDBFeature *feature) --=20 2.39.5 From nobody Thu Apr 3 11:27:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742408659; cv=none; d=zohomail.com; s=zohoarc; b=W2CUOwfzsZg18lpJzeir9knV9+ydNcenhM2h/bikBIcZ2uYVQ0U7V7I6KxEJq4WS5T4KTutw0WZQBmJFUoMuBqYtF92kdfqEultYZwVG8R0oEyRceEOG8St0zQj2saOtNW1NqIzFEt2H+VTWWIe2q3K37POuZc6SrqD9pmIyyQQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Wed, 19 Mar 2025 11:22:57 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 03/10] target/arm: convert 32 bit gdbstub to new helper Date: Wed, 19 Mar 2025 18:22:48 +0000 Message-Id: <20250319182255.3096731-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408659952019000 For some of the helpers we need a temporary variable to copy from although we could add some helpers to return pointers into env in those cases if we wanted to. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Pierrick Bouvier --- target/arm/gdbstub.c | 57 ++++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 30068c2262..14d931b0bf 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/gdbstub.h" -#include "gdbstub/helpers.h" +#include "gdbstub/registers.h" #include "gdbstub/commands.h" #include "system/tcg.h" #include "internals.h" @@ -33,12 +33,16 @@ typedef struct RegisterSysregFeatureParam { int n; } RegisterSysregFeatureParam; =20 -/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect - whatever the target description contains. Due to a historical mishap - the FPA registers appear in between core integer regs and the CPSR. - We hack round this by giving the FPA regs zero size when talking to a - newer gdb. */ - +/* + * Old gdb always expect FPA registers. Newer (xml-aware) gdb only + * expect whatever the target description contains. Due to a + * historical mishap the FPA registers appear in between core integer + * regs and the CPSR. We hack round this by giving the FPA regs zero + * size when talking to a newer gdb. + * + * While gdb cares about the memory endianess of the target all + * registers are passed in little-endian mode. + */ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -46,15 +50,17 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) =20 if (n < 16) { /* Core integer register. */ - return gdb_get_reg32(mem_buf, env->regs[n]); + return gdb_get_register_value(MO_TEUL, mem_buf, (uint8_t *) &env->= regs[n]); } if (n =3D=3D 25) { /* CPSR, or XPSR for M-profile */ + uint32_t reg; if (arm_feature(env, ARM_FEATURE_M)) { - return gdb_get_reg32(mem_buf, xpsr_read(env)); + reg =3D xpsr_read(env); } else { - return gdb_get_reg32(mem_buf, cpsr_read(env)); + reg =3D cpsr_read(env); } + return gdb_get_register_value(MO_TEUL, mem_buf, (uint8_t *) ®); } /* Unknown register. */ return 0; @@ -115,19 +121,22 @@ static int vfp_gdb_get_reg(CPUState *cs, GByteArray *= buf, int reg) =20 /* VFP data registers are always little-endian. */ if (reg < nregs) { - return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); + return gdb_get_register_value(MO_TEUQ, buf, + (uint8_t *) aa32_vfp_dreg(env, reg)); } if (arm_feature(env, ARM_FEATURE_NEON)) { /* Aliases for Q regs. */ nregs +=3D 16; if (reg < nregs) { uint64_t *q =3D aa32_vfp_qreg(env, reg - 32); - return gdb_get_reg128(buf, q[0], q[1]); + return gdb_get_register_value(MO_TEUO, buf, (uint8_t *) q); } } switch (reg - nregs) { + uint32_t fpcr; case 0: - return gdb_get_reg32(buf, vfp_get_fpscr(env)); + fpcr =3D vfp_get_fpscr(env); + return gdb_get_register_value(MO_TEUL, buf, (uint8_t *) &fpcr); } return 0; } @@ -166,9 +175,11 @@ static int vfp_gdb_get_sysreg(CPUState *cs, GByteArray= *buf, int reg) =20 switch (reg) { case 0: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); + return gdb_get_register_value(MO_TEUL, buf, + (uint8_t *) &env->vfp.xregs[ARM_VFP_= FPSID]); case 1: - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); + return gdb_get_register_value(MO_TEUL, buf, + (uint8_t *) &env->vfp.xregs[ARM_VFP_= FPEXC]); } return 0; } @@ -196,7 +207,8 @@ static int mve_gdb_get_reg(CPUState *cs, GByteArray *bu= f, int reg) =20 switch (reg) { case 0: - return gdb_get_reg32(buf, env->v7m.vpr); + return gdb_get_register_value(MO_TEUL, buf, + (uint8_t *) &env->v7m.vpr); default: return 0; } @@ -236,9 +248,11 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArray= *buf, int reg) ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); if (ri) { if (cpreg_field_is_64bit(ri)) { - return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); + uint64_t cpreg =3D read_raw_cp_reg(env, ri); + return gdb_get_register_value(MO_TEUQ, buf, (uint8_t *) &cpreg= ); } else { - return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); + uint32_t cpreg =3D (uint32_t) read_raw_cp_reg(env, ri); + return gdb_get_register_value(MO_TEUL, buf, (uint8_t *) &cpreg= ); } } return 0; @@ -375,12 +389,12 @@ static uint32_t *m_sysreg_ptr(CPUARMState *env, MProf= ileSysreg reg, bool sec) static int m_sysreg_get(CPUARMState *env, GByteArray *buf, MProfileSysreg reg, bool secure) { - uint32_t *ptr =3D m_sysreg_ptr(env, reg, secure); + uint8_t *ptr =3D (uint8_t *) m_sysreg_ptr(env, reg, secure); =20 if (ptr =3D=3D NULL) { return 0; } - return gdb_get_reg32(buf, *ptr); + return gdb_get_register_value(MO_TEUL, buf, ptr); } =20 static int arm_gdb_get_m_systemreg(CPUState *cs, GByteArray *buf, int reg) @@ -393,7 +407,8 @@ static int arm_gdb_get_m_systemreg(CPUState *cs, GByteA= rray *buf, int reg) * banked and non-banked bits. */ if (reg =3D=3D M_SYSREG_CONTROL) { - return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure= )); + uint32_t reg32 =3D arm_v7m_mrs_control(env, env->v7m.secure); + return gdb_get_register_value(MO_TEUL, buf, (uint8_t *) ®32); } return m_sysreg_get(env, buf, reg, env->v7m.secure); } --=20 2.39.5 From nobody Thu Apr 3 11:27:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 19 Mar 2025 11:22:58 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 04/10] target/arm: convert 64 bit gdbstub to new helper Date: Wed, 19 Mar 2025 18:22:49 +0000 Message-Id: <20250319182255.3096731-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408664097019100 For some of the helpers we need a temporary variable to copy from although we could add some helpers to return pointers into env in those cases if we wanted to. Signed-off-by: Alex Benn=C3=A9e --- target/arm/gdbstub64.c | 53 ++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 20 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 1a4dbec567..793332af31 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -20,7 +20,7 @@ #include "qemu/log.h" #include "cpu.h" #include "internals.h" -#include "gdbstub/helpers.h" +#include "gdbstub/registers.h" #include "gdbstub/commands.h" #include "tcg/mte_helper.h" #if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX) @@ -35,15 +35,16 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteAr= ray *mem_buf, int n) =20 if (n < 31) { /* Core integer register. */ - return gdb_get_reg64(mem_buf, env->xregs[n]); + return gdb_get_register_value(MO_TEUO, mem_buf, (uint8_t *) &env->= xregs[n]); } switch (n) { case 31: - return gdb_get_reg64(mem_buf, env->xregs[31]); + return gdb_get_register_value(MO_TEUO, mem_buf, (uint8_t *) &env->= xregs[31]); case 32: - return gdb_get_reg64(mem_buf, env->pc); + return gdb_get_register_value(MO_TEUO, mem_buf, (uint8_t *) &env->= pc); case 33: - return gdb_get_reg32(mem_buf, pstate_read(env)); + uint32_t pstate =3D pstate_read(env); + return gdb_get_register_value(MO_TEUL, mem_buf, (uint8_t *) &pstat= e); } /* Unknown register. */ return 0; @@ -82,23 +83,27 @@ int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *b= uf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + uint32_t fpr; =20 switch (reg) { case 0 ... 31: { /* 128 bit FP register - quads are in LE order */ uint64_t *q =3D aa64_vfp_qreg(env, reg); - return gdb_get_reg128(buf, q[1], q[0]); + return gdb_get_register_value(MO_TEUO, buf, (uint8_t *) q); } case 32: /* FPSR */ - return gdb_get_reg32(buf, vfp_get_fpsr(env)); + fpr =3D vfp_get_fpsr(env); + break; case 33: /* FPCR */ - return gdb_get_reg32(buf, vfp_get_fpcr(env)); + fpr =3D vfp_get_fpcr(env); + break; default: return 0; } + return gdb_get_register_value(MO_TEUL, buf, (uint8_t *) &fpr); } =20 int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg) @@ -132,30 +137,37 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray = *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + uint32_t fpr; =20 switch (reg) { /* The first 32 registers are the zregs */ case 0 ... 31: { int vq, len =3D 0; + ARMVectorReg *zreg =3D &env->vfp.zregs[reg]; + for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { - len +=3D gdb_get_reg128(buf, - env->vfp.zregs[reg].d[vq * 2 + 1], - env->vfp.zregs[reg].d[vq * 2]); + len +=3D gdb_get_register_value(MO_TEUQ, buf, + (uint8_t *) &zreg->d[vq * 2 + 1]= ); + len +=3D gdb_get_register_value(MO_TEUQ, buf, + (uint8_t *) &zreg->d[vq * 2]); } return len; } case 32: - return gdb_get_reg32(buf, vfp_get_fpsr(env)); + fpr =3D vfp_get_fpsr(env); + return gdb_get_register_value(MO_TEUL, buf, (uint8_t *) &fpr); case 33: - return gdb_get_reg32(buf, vfp_get_fpcr(env)); + fpr =3D vfp_get_fpcr(env); + return gdb_get_register_value(MO_TEUL, buf, (uint8_t *) &fpr); /* then 16 predicates and the ffr */ case 34 ... 50: { int preg =3D reg - 34; int vq, len =3D 0; for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { - len +=3D gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); + len +=3D gdb_get_register_value(MO_TEUQ, buf, + (uint8_t *) &env->vfp.pregs[preg= ].p[vq / 4]); } return len; } @@ -165,8 +177,8 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *b= uf, int reg) * We report in Vector Granules (VG) which is 64bit in a Z reg * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ - int vq =3D sve_vqm1_for_el(env, arm_current_el(env)) + 1; - return gdb_get_reg64(buf, vq * 2); + uint64_t vq =3D (sve_vqm1_for_el(env, arm_current_el(env)) + 1) * = 2; + return gdb_get_register_value(MO_TEUL, buf, (uint8_t *) &vq); } default: /* gdbstub asked for something out our range */ @@ -248,10 +260,11 @@ int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArra= y *buf, int reg) bool is_data =3D !(reg & 1); bool is_high =3D reg & 2; ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); - ARMVAParameters param; + ARMVAParameters param =3D aa64_va_parameters(env, -is_high, mm= u_idx, + is_data, false); + uint64_t pauth_mask =3D pauth_ptr_mask(param); =20 - param =3D aa64_va_parameters(env, -is_high, mmu_idx, is_data, = false); - return gdb_get_reg64(buf, pauth_ptr_mask(param)); + return gdb_get_register_value(MO_TEUQ, buf, (uint8_t *) &pauth= _mask); } default: return 0; @@ -399,7 +412,7 @@ int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArra= y *buf, int reg) =20 tcf0 =3D extract64(env->cp15.sctlr_el[1], 38, 2); =20 - return gdb_get_reg64(buf, tcf0); + return gdb_get_register_value(MO_TEUQ, buf, (uint8_t *) &tcf0); } =20 int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg) --=20 2.39.5 From nobody Thu Apr 3 11:27:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742408752; cv=none; d=zohomail.com; s=zohoarc; b=bQAuD1SJpQlkIzJFXa2ORdJwmiQ31nuYSDoVhzpTVUXXKWLyjiNvKOxIftfGC09IyOFg9n9iZWuKPcLJZL4ByL2rmVmotbIoYlVAHmlDFNg2fldQIGcCSqP4CIC+8xovg2Pykkf3R5mND2NpgY1O+ym0zHurWMCQ0BWLSU2p+qI= ARC-Message-Signature: i=1; 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Wed, 19 Mar 2025 11:22:59 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 05/10] target/ppc: expand comment on FP/VMX/VSX access functions Date: Wed, 19 Mar 2025 18:22:50 +0000 Message-Id: <20250319182255.3096731-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408754341019000 Mainly as an aid to myself getting confused too many bswaps deep into the code. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Pierrick Bouvier --- target/ppc/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index efab54a068..1e833ade04 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2906,7 +2906,12 @@ static inline bool lsw_reg_in_range(int start, int n= regs, int rx) (start + nregs > 32 && (rx >=3D start || rx < start + nregs - 3= 2)); } =20 -/* Accessors for FP, VMX and VSX registers */ +/* + * Access functions for FP, VMX and VSX registers + * + * The register is stored as a 128 bit host endian value so we need to + * take that into account when accessing smaller parts of it. + */ #if HOST_BIG_ENDIAN #define VsrB(i) u8[i] #define VsrSB(i) s8[i] --=20 2.39.5 From nobody Thu Apr 3 11:27:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 19 Mar 2025 11:23:00 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 06/10] target/ppc: make ppc_maybe_bswap_register static Date: Wed, 19 Mar 2025 18:22:51 +0000 Message-Id: <20250319182255.3096731-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408660230019100 It's not used outside of the gdbstub code. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/ppc/cpu.h | 1 - target/ppc/gdbstub.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1e833ade04..950bb6e06c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -3016,7 +3016,6 @@ static inline bool ppc_interrupts_little_endian(Power= PCCPU *cpu, bool hv) =20 void dump_mmu(CPUPPCState *env); =20 -void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); void ppc_store_vscr(CPUPPCState *env, uint32_t vscr); uint32_t ppc_get_vscr(CPUPPCState *env); void ppc_set_cr(CPUPPCState *env, uint64_t cr); diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 3b28d4e21c..c09e93abaf 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -81,7 +81,7 @@ static int ppc_gdb_register_len(int n) * TARGET_BIG_ENDIAN is always set, and we must check the current * mode of the chip to see if we're running in little-endian. */ -void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) +static void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, i= nt len) { #ifndef CONFIG_USER_ONLY if (!FIELD_EX64(env->msr, MSR, LE)) { --=20 2.39.5 From nobody Thu Apr 3 11:27:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 19 Mar 2025 11:23:02 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 07/10] target/ppc: convert gdbstub to new helper (!hacky) Date: Wed, 19 Mar 2025 18:22:52 +0000 Message-Id: <20250319182255.3096731-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408752337019000 By passing the explicit state of LE/BE via the memop we can avoid the messing about we do with ppc_maybe_bswap_register() at least for supplying register values to gdbstub. The fact we still need the helper for setting the values probably indicates we could do with a reverse helper, possibly to setting env vars directly? This is complicated by aliasing though. Signed-off-by: Alex Benn=C3=A9e --- target/ppc/gdbstub.c | 192 ++++++++++++++++++++++++------------------- 1 file changed, 108 insertions(+), 84 deletions(-) diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index c09e93abaf..663a97d986 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/gdbstub.h" -#include "gdbstub/helpers.h" +#include "gdbstub/registers.h" #include "internal.h" =20 static int ppc_gdb_register_len_apple(int n) @@ -74,12 +74,12 @@ static int ppc_gdb_register_len(int n) } =20 /* - * We need to present the registers to gdb in the "current" memory - * ordering. For user-only mode we get this for free; - * TARGET_BIG_ENDIAN is set to the proper ordering for the - * binary, and cannot be changed. For system mode, - * TARGET_BIG_ENDIAN is always set, and we must check the current - * mode of the chip to see if we're running in little-endian. + * We need to map the target endian registers from gdb in the + * "current" memory ordering. For user-only mode we get this for free; + * TARGET_BIG_ENDIAN is set to the proper ordering for the binary, and + * cannot be changed. For system mode, TARGET_BIG_ENDIAN is always + * set, and we must check the current mode of the chip to see if we're + * running in little-endian. */ static void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, i= nt len) { @@ -98,6 +98,38 @@ static void ppc_maybe_bswap_register(CPUPPCState *env, u= int8_t *mem_buf, int len #endif } =20 +/* + * We need to present the registers to gdb in the "current" memory + * ordering. For user-only mode this is hardwired by TARGET_BIG_ENDIAN + * and cannot be changed. For system mode we must check the current + * mode of the chip to see if we're running in little-endian. + */ +static MemOp ppc_gdb_memop(CPUPPCState *env, int len) +{ +#ifndef CONFIG_USER_ONLY + MemOp end =3D FIELD_EX64(env->msr, MSR, LE) ? MO_LE : MO_BE; +#else + #ifdef TARGET_BIG_ENDIAN + MemOp end =3D MO_BE; + #else + MemOp end =3D MO_LE; + #endif +#endif + + return size_memop(len) | end; +} + +/* + * Helpers copied from helpers.h just for loading target_ulong values + * from gdbstub's GByteArray + */ + +#if TARGET_LONG_BITS =3D=3D 64 +#define ldtul_p(addr) ldq_p(addr) +#else +#define ldtul_p(addr) ldl_p(addr) +#endif + /* * Old gdb always expects FP registers. Newer (xml-aware) gdb only * expects whatever the target description contains. Due to a @@ -109,51 +141,50 @@ static void ppc_maybe_bswap_register(CPUPPCState *env= , uint8_t *mem_buf, int len int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) { CPUPPCState *env =3D cpu_env(cs); - uint8_t *mem_buf; int r =3D ppc_gdb_register_len(n); + MemOp mo; =20 if (!r) { return r; } =20 + mo =3D ppc_gdb_memop(env, r); + if (n < 32) { /* gprs */ - gdb_get_regl(buf, env->gpr[n]); + return gdb_get_register_value(mo, buf, (uint8_t *) &env->gpr[n]); } else { switch (n) { case 64: - gdb_get_regl(buf, env->nip); - break; + return gdb_get_register_value(mo, buf, (uint8_t *) &env->nip); case 65: - gdb_get_regl(buf, env->msr); - break; + return gdb_get_register_value(mo, buf, (uint8_t *) &env->msr); case 66: { uint32_t cr =3D ppc_get_cr(env); - gdb_get_reg32(buf, cr); - break; + return gdb_get_register_value(ppc_gdb_memop(env, 4), buf, = (uint8_t *) &cr); } case 67: - gdb_get_regl(buf, env->lr); + return gdb_get_register_value(mo, buf, (uint8_t *) &env->lr); break; case 68: - gdb_get_regl(buf, env->ctr); + return gdb_get_register_value(mo, buf, (uint8_t *) &env->ctr); break; case 69: - gdb_get_reg32(buf, cpu_read_xer(env)); - break; + uint32_t val =3D cpu_read_xer(env); + return gdb_get_register_value(ppc_gdb_memop(env, 4), buf, (uin= t8_t *) &val); } } - mem_buf =3D buf->data + buf->len - r; - ppc_maybe_bswap_register(env, mem_buf, r); - return r; + + return 0; } =20 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) { CPUPPCState *env =3D cpu_env(cs); - uint8_t *mem_buf; int r =3D ppc_gdb_register_len_apple(n); + MemOp mo =3D ppc_gdb_memop(env, r); + int actual =3D 0; =20 if (!r) { return r; @@ -161,44 +192,48 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, GBy= teArray *buf, int n) =20 if (n < 32) { /* gprs */ - gdb_get_reg64(buf, env->gpr[n]); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &env->gpr[n= ]); } else if (n < 64) { /* fprs */ - gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32)); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) cpu_fpr_ptr= (env, n - 32)); } else if (n < 96) { - /* Altivec */ - gdb_get_reg64(buf, n - 64); - gdb_get_reg64(buf, 0); + /* Altivec - where are they? ppc_vsr_t vsr[64]? */ + uint64_t empty =3D 0; + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &empty); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &empty); } else { switch (n) { case 64 + 32: - gdb_get_reg64(buf, env->nip); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &env->n= ip); break; case 65 + 32: - gdb_get_reg64(buf, env->msr); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &env->m= sr); break; case 66 + 32: - { - uint32_t cr =3D ppc_get_cr(env); - gdb_get_reg32(buf, cr); - break; - } + { + uint32_t cr =3D ppc_get_cr(env); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &cr); + break; + } case 67 + 32: - gdb_get_reg64(buf, env->lr); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &env->l= r); break; case 68 + 32: - gdb_get_reg64(buf, env->ctr); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &env->c= tr); break; case 69 + 32: - gdb_get_reg32(buf, cpu_read_xer(env)); + { + uint32_t xer =3D cpu_read_xer(env); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &xer); break; + } case 70 + 32: - gdb_get_reg64(buf, env->fpscr); + actual =3D gdb_get_register_value(mo, buf, (uint8_t *) &env->f= pscr); break; } } - mem_buf =3D buf->data + buf->len - r; - ppc_maybe_bswap_register(env, mem_buf, r); + + g_assert(r =3D=3D actual); return r; } =20 @@ -210,6 +245,9 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) if (!r) { return r; } + + g_assert(r =3D=3D n); + =20 ppc_maybe_bswap_register(env, mem_buf, r); if (n < 32) { /* gprs */ @@ -367,18 +405,16 @@ static int gdb_get_spr_reg(CPUState *cs, GByteArray *= buf, int n) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; + MemOp mo =3D ppc_gdb_memop(env, TARGET_LONG_SIZE); + target_ulong val; int reg; - int len; =20 reg =3D gdb_find_spr_idx(env, n); if (reg < 0) { return 0; } =20 - len =3D TARGET_LONG_SIZE; - /* Handle those SPRs that are not part of the env->spr[] array */ - target_ulong val; switch (reg) { #if defined(TARGET_PPC64) case SPR_CFAR: @@ -400,10 +436,7 @@ static int gdb_get_spr_reg(CPUState *cs, GByteArray *b= uf, int n) default: val =3D env->spr[reg]; } - gdb_get_regl(buf, val); - - ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len); - return len; + return gdb_get_register_value(mo, buf, (uint8_t *) &val); } =20 static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n) @@ -441,18 +474,14 @@ static int gdb_get_float_reg(CPUState *cs, GByteArray= *buf, int n) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; - uint8_t *mem_buf; + MemOp mo; if (n < 32) { - gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); - mem_buf =3D gdb_get_reg_ptr(buf, 8); - ppc_maybe_bswap_register(env, mem_buf, 8); - return 8; + mo =3D ppc_gdb_memop(env, 8); + return gdb_get_register_value(mo, buf, (uint8_t *)cpu_fpr_ptr(env,= n)); } if (n =3D=3D 32) { - gdb_get_reg32(buf, env->fpscr); - mem_buf =3D gdb_get_reg_ptr(buf, 4); - ppc_maybe_bswap_register(env, mem_buf, 4); - return 4; + mo =3D ppc_gdb_memop(env, 4); + return gdb_get_register_value(mo, buf, (uint8_t *) &env->fpscr); } return 0; } @@ -479,26 +508,21 @@ static int gdb_get_avr_reg(CPUState *cs, GByteArray *= buf, int n) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; - uint8_t *mem_buf; + MemOp mo; =20 if (n < 32) { ppc_avr_t *avr =3D cpu_avr_ptr(env, n); - gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1)); - mem_buf =3D gdb_get_reg_ptr(buf, 16); - ppc_maybe_bswap_register(env, mem_buf, 16); - return 16; + mo =3D ppc_gdb_memop(env, 16); + return gdb_get_register_value(mo, buf, (uint8_t *) avr); } if (n =3D=3D 32) { - gdb_get_reg32(buf, ppc_get_vscr(env)); - mem_buf =3D gdb_get_reg_ptr(buf, 4); - ppc_maybe_bswap_register(env, mem_buf, 4); - return 4; + uint32_t vscr =3D ppc_get_vscr(env); + mo =3D ppc_gdb_memop(env, 4); + return gdb_get_register_value(mo, buf, (uint8_t *) &vscr); } if (n =3D=3D 33) { - gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); - mem_buf =3D gdb_get_reg_ptr(buf, 4); - ppc_maybe_bswap_register(env, mem_buf, 4); - return 4; + mo =3D ppc_gdb_memop(env, 4); + return gdb_get_register_value(mo, buf, (uint8_t *) &env->spr[SPR_V= RSAVE]); } return 0; } @@ -532,25 +556,25 @@ static int gdb_get_spe_reg(CPUState *cs, GByteArray *= buf, int n) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; + MemOp mo; =20 if (n < 32) { #if defined(TARGET_PPC64) - gdb_get_reg32(buf, env->gpr[n] >> 32); - ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); + uint32_t low =3D env->gpr[n] >> 32; + mo =3D ppc_gdb_memop(env, 4); + return gdb_get_register_value(mo, buf, (uint8_t *) &low); #else - gdb_get_reg32(buf, env->gprh[n]); + mo =3D ppc_gdb_memop(env, 4); + return gdb_get_register_value(mo, buf, (uint8_t *) &env->gprh[n]); #endif - return 4; } if (n =3D=3D 32) { - gdb_get_reg64(buf, env->spe_acc); - ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); - return 8; + mo =3D ppc_gdb_memop(env, 8); + return gdb_get_register_value(mo, buf, (uint8_t *) &env->spe_acc); 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Wed, 19 Mar 2025 11:22:59 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 08/10] gdbstub: assert earlier in handle_read_all_regs Date: Wed, 19 Mar 2025 18:22:53 +0000 Message-Id: <20250319182255.3096731-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408645995019000 When things go wrong we want to assert on the register that failed to be able to figure out what went wrong. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- gdbstub/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 3d7b1028e4..8561d9d527 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -1350,8 +1350,8 @@ static void handle_read_all_regs(GArray *params, void= *user_ctx) len +=3D gdb_read_register(gdbserver_state.g_cpu, gdbserver_state.mem_buf, reg_id); + g_assert(len =3D=3D gdbserver_state.mem_buf->len); } - g_assert(len =3D=3D gdbserver_state.mem_buf->len); =20 gdb_memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, l= en); gdb_put_strbuf(); --=20 2.39.5 From nobody Thu Apr 3 11:27:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 19 Mar 2025 11:23:00 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 09/10] include/exec: fix assert in size_memop Date: Wed, 19 Mar 2025 18:22:54 +0000 Message-Id: <20250319182255.3096731-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408673022019100 We can handle larger sized memops now, expand the range of the assert. Fixes: 4b473e0c60 (tcg: Expand MO_SIZE to 3 bits) Signed-off-by: Alex Benn=C3=A9e --- include/exec/memop.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 407a47d82c..faed3ff902 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -162,8 +162,8 @@ static inline unsigned memop_size(MemOp op) static inline MemOp size_memop(unsigned size) { #ifdef CONFIG_DEBUG_TCG - /* Power of 2 up to 8. */ - assert((size & (size - 1)) =3D=3D 0 && size >=3D 1 && size <=3D 8); + /* Power of 2 up to 128. */ + assert((size & (size - 1)) =3D=3D 0 && size >=3D 1 && size <=3D 128); #endif return (MemOp)ctz32(size); } --=20 2.39.5 From nobody Thu Apr 3 11:27:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Wed, 19 Mar 2025 11:23:01 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Juan Quintela , Ilya Leoshkevich , Thomas Huth , Akihiko Odaki , qemu-ppc@nongnu.org, David Gibson , qemu-s390x@nongnu.org, Wainer dos Santos Moschetta , Peter Xu , Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Hildenbrand , Yonggang Luo , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Beraldo Leal , qemu-arm@nongnu.org, Greg Kurz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Paolo Bonzini , "Edgar E. Iglesias" Subject: [PATCH 10/10] target/microblaze: convert gdbstub to new helper Date: Wed, 19 Mar 2025 18:22:55 +0000 Message-Id: <20250319182255.3096731-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250319182255.3096731-1-alex.bennee@linaro.org> References: <20250319182255.3096731-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742408687998019000 This is a pretty simple conversion which will be trivial to update once TARGET_BIGENDIAN is replaced with a helper function. Signed-off-by: Alex Benn=C3=A9e --- target/microblaze/gdbstub.c | 44 ++++++++++++++----------------------- 1 file changed, 17 insertions(+), 27 deletions(-) diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index d493681d38..106d6efbab 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "gdbstub/helpers.h" +#include "gdbstub/registers.h" =20 /* * GDB expects SREGs in the following order: @@ -50,62 +50,52 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *= mem_buf, int n) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; - uint32_t val; + MemOp mo =3D TARGET_BIG_ENDIAN ? MO_BEUL : MO_LEUL; =20 switch (n) { case 1 ... 31: - val =3D env->regs[n]; - break; + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &env->regs[= n]); case GDB_PC: - val =3D env->pc; - break; + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &env->pc); case GDB_MSR: - val =3D mb_cpu_read_msr(env); - break; + uint32_t msr =3D mb_cpu_read_msr(env); + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &msr); case GDB_EAR: - val =3D env->ear; - break; + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &env->ear); case GDB_ESR: - val =3D env->esr; - break; + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &env->esr); case GDB_FSR: - val =3D env->fsr; - break; + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &env->fsr); case GDB_BTR: - val =3D env->btr; - break; + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &env->btr); case GDB_PVR0 ... GDB_PVR11: /* PVR12 is intentionally skipped */ - val =3D cpu->cfg.pvr_regs[n - GDB_PVR0]; - break; + return gdb_get_register_value(mo, mem_buf, + (uint8_t *) &cpu->cfg.pvr_regs[n - G= DB_PVR0]); case GDB_EDR: - val =3D env->edr; - break; + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &env->edr); default: /* Other SRegs aren't modeled, so report a value of 0 */ - val =3D 0; - break; + return 0; } - return gdb_get_reg32(mem_buf, val); } =20 int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; - uint32_t val; + MemOp mo =3D TARGET_BIG_ENDIAN ? MO_BEUL : MO_LEUL; =20 switch (n) { case GDB_SP_SHL: - val =3D env->slr; + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &env->slr); break; case GDB_SP_SHR: - val =3D env->shr; + return gdb_get_register_value(mo, mem_buf, (uint8_t *) &env->shr); break; default: return 0; } - return gdb_get_reg32(mem_buf, val); } =20 int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) --=20 2.39.5