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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu-param.h | 14 ++++++++++++++ target/arm/cpu.h | 14 -------------- target/hppa/cpu-param.h | 2 ++ target/hppa/cpu.h | 2 -- target/i386/cpu-param.h | 2 ++ target/i386/cpu.h | 2 -- target/m68k/cpu-param.h | 2 ++ target/m68k/cpu.h | 2 -- target/microblaze/cpu-param.h | 2 ++ target/microblaze/cpu.h | 2 -- target/mips/cpu-param.h | 2 ++ target/mips/cpu.h | 2 -- target/openrisc/cpu-param.h | 2 ++ target/openrisc/cpu.h | 2 -- target/riscv/cpu-param.h | 8 ++++++++ target/riscv/cpu.h | 6 ------ target/s390x/cpu-param.h | 2 ++ target/s390x/cpu.h | 2 -- target/sh4/cpu-param.h | 2 ++ target/sh4/cpu.h | 2 -- target/sparc/cpu-param.h | 2 ++ target/sparc/cpu.h | 1 - 22 files changed, 40 insertions(+), 37 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 896b35bd6d5..ed1f0b16e51 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -38,6 +38,20 @@ # define TARGET_PAGE_BITS_MIN 10 #endif /* !CONFIG_USER_ONLY */ =20 +/* ARM-specific extra insn start words: + * 1: Conditional execution bits + * 2: Partial exception syndrome for data aborts + */ +#define TARGET_INSN_START_EXTRA_WORDS 2 + +/* The 2nd extra word holding syndrome info for data aborts does not use + * the upper 6 bits nor the lower 13 bits. We mask and shift it down to + * help the sleb128 encoder do a better job. + * When restoring the CPU state, we shift it back up. + */ +#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) +#define ARM_INSN_START_WORD2_SHIFT 13 + /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a8177c6c2e8..537359ff30b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -100,20 +100,6 @@ #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif =20 -/* ARM-specific extra insn start words: - * 1: Conditional execution bits - * 2: Partial exception syndrome for data aborts - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - -/* The 2nd extra word holding syndrome info for data aborts does not use - * the upper 6 bits nor the lower 13 bits. We mask and shift it down to - * help the sleb128 encoder do a better job. - * When restoring the CPU state, we shift it back up. - */ -#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) -#define ARM_INSN_START_WORD2_SHIFT 13 - /* We currently assume float and double are IEEE single and double precision respectively. Doing runtime conversions is tricky because VFP registers may contain diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 7ed6b5741e7..68ed84e84af 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -19,6 +19,8 @@ =20 #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* PA-RISC 1.x processors have a strong memory model. */ /* * ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7be4a1d3800..f289843c299 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -45,8 +45,6 @@ #define PRIV_KERNEL 0 #define PRIV_USER 3 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - /* No need to flush MMU_ABS*_IDX */ #define HPPA_MMU_FLUSH_MASK \ (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \ diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index b0e884c5d70..0c8efce8619 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -22,6 +22,8 @@ #endif #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + /* The x86 has a strong memory model with some store-after-load re-orderin= g */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 76f24446a55..f2cae1b066e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1610,8 +1610,6 @@ typedef struct { #define MAX_FIXED_COUNTERS 3 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #define NB_OPMASK_REGS 8 =20 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 7afbf6d302d..256a2b5f8b2 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -17,4 +17,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + #endif diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index ddb0f29f4a3..b6cc38f700e 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -76,8 +76,6 @@ #define M68K_MAX_TTR 2 #define TTR(type, index) ttr[((type & ACCESS_CODE) =3D=3D ACCESS_CODE) * 2= + index] =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - typedef CPU_LDoubleU FPReg; =20 typedef struct CPUArchState { diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index c866ec6c149..5d55e0e3c4a 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -27,6 +27,8 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + /* MicroBlaze is always in-order. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e44ddd53078..552e9646e95 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -231,8 +231,6 @@ typedef struct CPUArchState CPUMBState; #define STREAM_CONTROL (1 << 3) #define STREAM_NONBLOCK (1 << 4) =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - /* use-non-secure property masks */ #define USE_NON_SECURE_M_AXI_DP_MASK 0x1 #define USE_NON_SECURE_M_AXI_IP_MASK 0x2 diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 11b3ac0ac63..b953f993b25 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -25,6 +25,8 @@ #define TARGET_PAGE_BITS_MIN 12 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 2 + #define TCG_GUEST_DEFAULT_MO (0) =20 #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f6877ece8b4..6545f0b4cd4 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -98,8 +98,6 @@ struct CPUMIPSFPUContext { #define FP_UNIMPLEMENTED 32 }; =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { int32_t CP0_MVPControl; diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 37627f2c394..7ea0ecb55a6 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -12,6 +12,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + #define TCG_GUEST_DEFAULT_MO (0) =20 #endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b97d2ffdd26..ae6d6a77910 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -38,8 +38,6 @@ struct OpenRISCCPUClass { ResettablePhases parent_phases; }; =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - enum { MMU_NOMMU_IDX =3D 0, MMU_SUPERVISOR_IDX =3D 1, diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index fba30e966a8..ff4ba81965a 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -16,6 +16,14 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ + +/* + * RISC-V-specific extra insn start words: + * 1: Original instruction opcode + * 2: more information about instruction + */ +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* * The current MMU Modes are: * - U mode 0b000 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7de19b41836..b432e31fb6d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -43,12 +43,6 @@ typedef struct CPUArchState CPURISCVState; # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif =20 -/* - * RISC-V-specific extra insn start words: - * 1: Original instruction opcode - * 2: more information about instruction - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 /* * b0: Whether a instruction always raise a store AMO or not. */ diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index 5c331ec424c..a8a4377f4ff 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -12,6 +12,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 =20 +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 5b7992deda6..057c33e0225 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -35,8 +35,6 @@ =20 #define TARGET_HAS_PRECISE_SMC =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #define MMU_USER_IDX 0 =20 #define S390_MAX_CPUS 248 diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index 2b6e11dd0ac..f328715ee86 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -16,4 +16,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index d536d5d7154..3ece180ff63 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -125,8 +125,6 @@ typedef struct tlb_t { #define UTLB_SIZE 64 #define ITLB_SIZE 4 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - enum sh_features { SH_FEATURE_SH4A =3D 1, SH_FEATURE_BCR3_AND_BCR4 =3D 2, diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 6952ee2b826..62d47b804bb 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -21,6 +21,8 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + /* * From Oracle SPARC Architecture 2015: * diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 462bcb6c0e6..d5e8378e6c0 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -221,7 +221,6 @@ typedef struct trap_state { uint32_t tt; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/tcg/insn-start-words.h | 4 ---- include/tcg/tcg-op.h | 2 +- target/alpha/cpu-param.h | 2 ++ target/avr/cpu-param.h | 2 ++ target/hexagon/cpu-param.h | 2 ++ target/loongarch/cpu-param.h | 2 ++ target/ppc/cpu-param.h | 2 ++ target/rx/cpu-param.h | 2 ++ target/tricore/cpu-param.h | 2 ++ target/xtensa/cpu-param.h | 2 ++ 10 files changed, 17 insertions(+), 5 deletions(-) diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h index 50c18bd326d..394c191da8d 100644 --- a/include/tcg/insn-start-words.h +++ b/include/tcg/insn-start-words.h @@ -8,10 +8,6 @@ =20 #include "cpu.h" =20 -#ifndef TARGET_INSN_START_EXTRA_WORDS -# define TARGET_INSN_START_WORDS 1 -#else # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) -#endif =20 #endif /* TARGET_INSN_START_WORDS */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index a02850583bd..5dfddf995d6 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -22,7 +22,7 @@ # error #endif =20 -#ifndef TARGET_INSN_START_EXTRA_WORDS +#if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 static inline void tcg_gen_insn_start(target_ulong pc) { TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BIT= S); diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index ff06e41497a..c89d3ad52b6 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -25,6 +25,8 @@ # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 81f3f49ee1f..0417f8dcccb 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -31,6 +31,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO 0 =20 #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 45ee7b46409..635d509e743 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -23,4 +23,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 52437946e56..dbe414bb35a 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -13,6 +13,8 @@ =20 #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO (0) =20 #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 6c4525fdf3c..9cb26cefd5d 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -38,6 +38,8 @@ # define TARGET_PAGE_BITS 12 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO 0 =20 #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index ef1970a09e9..84934f3bcaf 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -24,4 +24,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 790242ef3d2..eb33a67c419 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -12,4 +12,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 5e4848ad059..e7cb747aaae 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -16,6 +16,8 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 --=20 2.47.1 From nobody Thu Apr 3 11:52:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Use the same type signature for tcg_gen_insn_start(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-op.h | 7 +++---- accel/tcg/translate-all.c | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 5dfddf995d6..8938f386599 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -23,21 +23,20 @@ #endif =20 #if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 -static inline void tcg_gen_insn_start(target_ulong pc) +static inline void tcg_gen_insn_start(uint64_t pc) { TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BIT= S); tcg_set_insn_start_param(op, 0, pc); } #elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) +static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1) { TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG= _BITS); tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); } #elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 2 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, - target_ulong a2) +static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a= 2) { TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG= _BITS); tcg_set_insn_start_param(op, 0, pc); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 82bc16bd535..a857aefd756 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -117,7 +117,7 @@ static int64_t decode_sleb128(const uint8_t **pp) /* Encode the data collected about the instructions while compiling TB. Place the data at BLOCK, and return the number of bytes consumed. =20 - The logical table consists of TARGET_INSN_START_WORDS target_ulong's, + The logical table consists of TARGET_INSN_START_WORDS uint64_t's, which come from the target's insn_start data, followed by a uintptr_t which comes from the host pc of the end of the code implementing the in= sn. =20 --=20 2.47.1 From nobody Thu Apr 3 11:52:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742391988; cv=none; d=zohomail.com; s=zohoarc; b=cuzZm/2I/Nm6YNKfpjwuO9+lfa6I7hT+Me6eMgldP8rD3mgSxNPFZICUVA8FmP/PEclKz7/iN9eQaYeaf4mmr4HJCrHRGD7tS7qrFzrpj8TbThRHWfX3RWzOTaDGioTz+Bp9sN4MmC/9jUOdMlGW6XVy0xQ+AuqJYpHFlpdqfXw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742391988; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4Lkvodc73kqPvvWCS6V/G40kuyzwCLOWEJP7L4a0kMI=; b=PLyXC0e5dfmgDOZeS7JfOIAE3NSXQW/fs534FysoxojO4QOIsMlgJK2e71C7sGhDHhV/Bhh+TPz7nUZqpFV5xxjmYm0ZCi5aj4m/bNv5EZgkJqXc+0Vh6Nnc/4mdB/Z3s8JcahczzQGcMTpTeXErd7dCJ7wAQCboz8yC1U49yoc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742391988516903.2701157874942; Wed, 19 Mar 2025 06:46:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tutjl-0002wt-LT; Wed, 19 Mar 2025 09:45:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tutji-0002tX-US for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:34 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tutjh-00042v-4a for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:34 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-43cf034d4abso48330345e9.3 for ; Wed, 19 Mar 2025 06:45:32 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-op.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 8938f386599..e0038e70a8d 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -25,20 +25,29 @@ #if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 static inline void tcg_gen_insn_start(uint64_t pc) { - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BIT= S); + unsigned insn_start_words =3D 1; + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, + insn_start_words * 64 / TCG_TARGET_REG_BITS); + tcg_set_insn_start_param(op, 0, pc); } #elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1) { - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG= _BITS); + unsigned insn_start_words =3D 1 + TARGET_INSN_START_EXTRA_WORDS; + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, + insn_start_words * 64 / TCG_TARGET_REG_BITS); + tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); } #elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 2 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a= 2) { - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG= _BITS); + unsigned insn_start_words =3D 1 + TARGET_INSN_START_EXTRA_WORDS; + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, + insn_start_words * 64 / TCG_TARGET_REG_BITS); + tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); tcg_set_insn_start_param(op, 2, a2); --=20 2.47.1 From nobody Thu Apr 3 11:52:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742391997; cv=none; d=zohomail.com; s=zohoarc; b=FvGcMAz5qwih4dN4BWPbz3sBvCJ8yWElLvX0qG5otTORJvCL5VKYqK3P6frQZ4l9PCHKI6VVujWc/lU8KvaUvrJCvQgpZVDsUQ3cv75gx3Ar3tPLpSCTG3mfgElsuO+SCwl2wOY4c+8cRxAJ4f7h6LlRJqFw05amcqyQ+ii97qs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742391997; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=E7leHVcf9fCZ+ZDskvBL1qGPxfR0Xmsc8quxcgvFRhU=; b=AtLqqYq5Ou893phWcG3iTeCThVbMCBEHOhKvwEO9Exl68yvybtlJeIcrBSHFkxfegOoej8+QhuVtSohzhnelNxkUF2/uGPA3sOai9MuyEdoGuLg5i8QGCo+wwyt2T+HyVYoh/sU5RHtQAYVEn85sXKQzlRU16cGp5tp2yZeA1ik= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742391997166386.8386979996719; Wed, 19 Mar 2025 06:46:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tutjq-00036p-Bh; Wed, 19 Mar 2025 09:45:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tutjm-00031X-Kb for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:39 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tutjk-00043G-RI for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:38 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-43bb6b0b898so45642785e9.1 for ; Wed, 19 Mar 2025 06:45:36 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-op.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index e0038e70a8d..1f0d3b95304 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -25,7 +25,7 @@ #if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 static inline void tcg_gen_insn_start(uint64_t pc) { - unsigned insn_start_words =3D 1; + unsigned insn_start_words =3D tcg_ctx->insn_start_words; TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, insn_start_words * 64 / TCG_TARGET_REG_BITS); =20 @@ -34,7 +34,7 @@ static inline void tcg_gen_insn_start(uint64_t pc) #elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1) { - unsigned insn_start_words =3D 1 + TARGET_INSN_START_EXTRA_WORDS; + unsigned insn_start_words =3D tcg_ctx->insn_start_words; TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, insn_start_words * 64 / TCG_TARGET_REG_BITS); =20 @@ -44,7 +44,7 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64= _t a1) #elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 2 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a= 2) { - unsigned insn_start_words =3D 1 + TARGET_INSN_START_EXTRA_WORDS; + unsigned insn_start_words =3D tcg_ctx->insn_start_words; TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, insn_start_words * 64 / TCG_TARGET_REG_BITS); =20 --=20 2.47.1 From nobody Thu Apr 3 11:52:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742392014; cv=none; d=zohomail.com; s=zohoarc; b=cmd0bYqRH4DGHAeA8j1vWFKJHtiOeG7DLV3QRBTVtKUI8cTwAKq82WKhcTeBOAppLbrrYJ8d/03IbP/0sT7e7w0zGasyM9IzULzo6/a7Fv0RAeflytW5mLnz2FXoeutU84QQUyPrzLuaBibmnwqBLeoccZfSrWnmEUzccm7sZG8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742392014; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pD8YI+wp8fAxGYCXUbWnDA857RwLaG+OiY+C78OOnko=; b=HzmAxy1LKI1ZKP716qp7MQ1wbS0lfnZRYH9jtacn59pcNusF22jovgt/6lSqO3EKWbcPePBiZrgJ5IkG7vzDcyX25yrStxCZevFCAB+A3TfUCJmNjkS5WHs+64zE1pZKNYto0fGbDIkCTqjokduuGDnAprDYTPIpL/iu5hWKYko= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742392014474349.59772430253906; Wed, 19 Mar 2025 06:46:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tutju-0003JM-RI; Wed, 19 Mar 2025 09:45:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tutjr-0003BY-J3 for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:43 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tutjp-00043r-EJ for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:43 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-43d04dc73b7so46008515e9.3 for ; Wed, 19 Mar 2025 06:45:40 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/translate-all.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a857aefd756..54bba995a04 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -131,19 +131,20 @@ static int encode_search(TranslationBlock *tb, uint8_= t *block) uint8_t *highwater =3D tcg_ctx->code_gen_highwater; uint64_t *insn_data =3D tcg_ctx->gen_insn_data; uint16_t *insn_end_off =3D tcg_ctx->gen_insn_end_off; + unsigned insn_start_words =3D tcg_ctx->insn_start_words; uint8_t *p =3D block; int i, j, n; =20 for (i =3D 0, n =3D tb->icount; i < n; ++i) { uint64_t prev, curr; =20 - for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { + for (j =3D 0; j < insn_start_words; ++j) { if (i =3D=3D 0) { prev =3D (!(tb_cflags(tb) & CF_PCREL) && j =3D=3D 0 ? tb->= pc : 0); } else { - prev =3D insn_data[(i - 1) * TARGET_INSN_START_WORDS + j]; + prev =3D insn_data[(i - 1) * insn_start_words + j]; } - curr =3D insn_data[i * TARGET_INSN_START_WORDS + j]; + curr =3D insn_data[i * insn_start_words + j]; p =3D encode_sleb128(p, curr - prev); } prev =3D (i =3D=3D 0 ? 0 : insn_end_off[i - 1]); @@ -167,6 +168,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, { uintptr_t iter_pc =3D (uintptr_t)tb->tc.ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; + unsigned insn_start_words =3D tcg_ctx->insn_start_words; int i, j, num_insns =3D tb->icount; =20 host_pc -=3D GETPC_ADJ; @@ -175,7 +177,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, return -1; } =20 - memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS); + memset(data, 0, sizeof(uint64_t) * insn_start_words); if (!(tb_cflags(tb) & CF_PCREL)) { data[0] =3D tb->pc; } @@ -185,7 +187,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, * at which the end of the insn exceeds host_pc. */ for (i =3D 0; i < num_insns; ++i) { - for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { + for (j =3D 0; j < insn_start_words; ++j) { data[j] +=3D decode_sleb128(&p); } iter_pc +=3D decode_sleb128(&p); @@ -443,6 +445,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (logfile) { int code_size, data_size; const tcg_target_ulong *rx_data_gen_ptr; + unsigned insn_start_words =3D tcg_ctx->insn_start_words; size_t chunk_start; int insn =3D 0; =20 @@ -460,7 +463,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, fprintf(logfile, "OUT: [size=3D%d]\n", gen_code_size); fprintf(logfile, " -- guest addr 0x%016" PRIx64 " + tb prologue\n", - tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]= ); + tcg_ctx->gen_insn_data[insn * insn_start_words]); chunk_start =3D tcg_ctx->gen_insn_end_off[insn]; disas(logfile, tb->tc.ptr, chunk_start); =20 @@ -473,7 +476,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, size_t chunk_end =3D tcg_ctx->gen_insn_end_off[insn]; if (chunk_end > chunk_start) { fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n", - tcg_ctx->gen_insn_data[insn * TARGET_INSN_STAR= T_WORDS]); + tcg_ctx->gen_insn_data[insn * insn_start_words= ]); disas(logfile, tb->tc.ptr + chunk_start, chunk_end - chunk_start); chunk_start =3D chunk_end; --=20 2.47.1 From nobody Thu Apr 3 11:52:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742392014; cv=none; d=zohomail.com; s=zohoarc; b=DuJEju5SVcFti4dhtJd3vgpxO/Ea6To5EeoHwW5klKciW0RRUpLuWlYq14Dy+p2bmi8EUKlf2F96ll4GBfbzgwSwZ5R86dRANUPBCFmsIZIuouJ2lYRJIeByXrNj2H46qyLv8VXPFaV81Kx9AEaiWw5kQgcQ+3/C9HysVlb7RSU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742392014; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7+uCNdGR7Q/g7PWEHJ64I2sH/b8RzXSLv7jzZO24+jg=; b=lUSpkxJYHrS//5YbUFXZMb1gMSF2CdRP6pZlWe+BjD2gs3aT+5WAfLtCDgU9yht543bWjlDGMqRj3ikebmksCz8KrKLzrFv5v6iOCw4RrdxfXUlJaNFT66tUDcz+q8VRhYPv97VMX2SvmPWBUf3LUzOYKlK91sro0Jh/RMwpGlk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742392013994563.9503527001825; Wed, 19 Mar 2025 06:46:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tutk6-0003Uo-Ss; Wed, 19 Mar 2025 09:45:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tutjw-0003LU-8z for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:50 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tutjt-000448-VN for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:47 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-43cfecdd8b2so33504605e9.2 for ; Wed, 19 Mar 2025 06:45:45 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-op.h | 4 +--- include/tcg/tcg.h | 2 ++ accel/tcg/translate-all.c | 2 ++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 1f0d3b95304..0915043adf8 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -41,7 +41,7 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64= _t a1) tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); } -#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 2 +#elif TARGET_INSN_START_EXTRA_WORDS >=3D 2 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a= 2) { unsigned insn_start_words =3D tcg_ctx->insn_start_words; @@ -52,8 +52,6 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64= _t a1, uint64_t a2) tcg_set_insn_start_param(op, 1, a1); tcg_set_insn_start_param(op, 2, a2); } -#else -#error Unhandled TARGET_INSN_START_EXTRA_WORDS value #endif =20 #if TARGET_LONG_BITS =3D=3D 32 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 84d99508b65..92a23e10218 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -577,6 +577,8 @@ static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) return (TCGv_vec)temp_tcgv_i32(t); } =20 +#define TARGET_INSN_START_WORDS_MAX 3 + static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) { return op->args[arg]; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 54bba995a04..5e2a89dc474 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -66,6 +66,7 @@ #include "internal-target.h" #include "tcg/perf.h" #include "tcg/insn-start-words.h" +#include "tcg/tcg-op.h" =20 TBContext tb_ctx; =20 @@ -351,6 +352,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; + tcg_debug_assert(tcg_ctx->insn_start_words <=3D TARGET_INSN_START_WORD= S_MAX); #ifdef TCG_GUEST_DEFAULT_MO tcg_ctx->guest_mo =3D TCG_GUEST_DEFAULT_MO; #else --=20 2.47.1 From nobody Thu Apr 3 11:52:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742392030; cv=none; d=zohomail.com; s=zohoarc; b=gQDWBI6hmfOz1f0eYoJowGaJQuJ/AH51kTDHW1Hwk7fqQrOHVSm8gV7kJpE3AFq1i9PXmzQAClPnKzrgCo4RqkS2p6S877N47echUpxIjxf/g9/tG9vVGr7QcQAAKTvPpsRjG7f5Sclyz388c12KQxc1im3PHHVIkLm4iN/ax7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742392030; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SPrx/qQq0qEoYxnErEWIYikr7yzsC+mHkGeoZcaDE8c=; b=aw7AFG6w5Zj6PU05Puf+QVBIOQE0Ua5tjI5GvO7yn9O7AWsc3uoYVL7caxDrFFYjZD8C1sEWE4fvuJzsGBJmup9Uv1gs2aC1IF+VCMmvr9hw84Tk+f/2lF0/2uh1WHvxOqgpio0K6B7TKVJ0yLN8cPzLChi2Or3McxJN96wHTbI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742392030275547.3147168249704; Wed, 19 Mar 2025 06:47:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tutkz-0004EB-7z; Wed, 19 Mar 2025 09:46:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tutk0-0003N3-Pm for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:54 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tutjy-00044L-T9 for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:52 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-43cf034d4abso48336815e9.3 for ; Wed, 19 Mar 2025 06:45:50 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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The former is guaranty to hold the latter. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/translate-all.c | 2 +- target/i386/helper.c | 3 ++- target/openrisc/sys_helper.c | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5e2a89dc474..2f8cf6db144 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -206,7 +206,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb= , uintptr_t host_pc, void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc) { - uint64_t data[TARGET_INSN_START_WORDS]; + uint64_t data[TARGET_INSN_START_WORDS_MAX]; int insns_left =3D cpu_unwind_data_from_tb(tb, host_pc, data); =20 if (insns_left < 0) { diff --git a/target/i386/helper.c b/target/i386/helper.c index c07b1b16ea1..90e113c8b5a 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -31,6 +31,7 @@ #include "qemu/log.h" #ifdef CONFIG_TCG #include "tcg/insn-start-words.h" +#include "tcg/tcg.h" #endif =20 void cpu_sync_avx_hflag(CPUX86State *env) @@ -524,7 +525,7 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int = bank, static inline target_ulong get_memio_eip(CPUX86State *env) { #ifdef CONFIG_TCG - uint64_t data[TARGET_INSN_START_WORDS]; + uint64_t data[TARGET_INSN_START_WORDS_MAX]; CPUState *cs =3D env_cpu(env); =20 if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) { diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 21bc137ccca..cf521461954 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -28,6 +28,7 @@ #include "hw/boards.h" #endif #include "tcg/insn-start-words.h" +#include "tcg/tcg.h" =20 #define TO_SPR(group, number) (((group) << 11) + (number)) =20 @@ -218,7 +219,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, targe= t_ulong rd, { OpenRISCCPU *cpu =3D env_archcpu(env); #ifndef CONFIG_USER_ONLY - uint64_t data[TARGET_INSN_START_WORDS]; + uint64_t data[TARGET_INSN_START_WORDS_MAX]; MachineState *ms =3D MACHINE(qdev_get_machine()); CPUState *cs =3D env_cpu(env); int idx; --=20 2.47.1 From nobody Thu Apr 3 11:52:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742392218; cv=none; d=zohomail.com; s=zohoarc; b=ANTU7noDGFU3BycSendydxgQzu8sSaD6NHPaXvD4ePHqIfLHMFaRak5+Ehj+T/hukpqRGvLoLTmN6VAgWe7YfJQyx/J6XhSJvSgNl7S4guWYpayusTRxEgVFnuLRSjP4TbiaJ38JAgphHnEIlJrvOwedyxOvjCP4i3Ij03om3Eo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742392218; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0iduta05yw16WNoxlZ2Qk6hI45690lcV/AnGwn0ABIE=; b=K1bpimdCIex98sKZA9DnUCYsrepWxBcCU89dPxgIecgxOLR7niky4+GrmlmsahmH+Qlebeu4HURsTVlmz76v6F2hU6x4k0u3OUsyI+B5KbutQLqYTD2H/29UCJU3x1aY/UM/4egrjcNGf+H7afEh3tAESAR2LuAPzOMx0Rty08o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742392218753478.75797500287797; Wed, 19 Mar 2025 06:50:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tutl4-0004cU-Gr; Wed, 19 Mar 2025 09:46:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tutk7-0003ZO-Fb for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:46:02 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tutk3-00044x-Bj for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:45:57 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-43cf58eea0fso24294485e9.0 for ; Wed, 19 Mar 2025 06:45:54 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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"tcg/insn-start-words.h" header being now empty, remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/insn-start-words.h | 13 ------------- accel/tcg/translate-all.c | 3 ++- target/i386/helper.c | 1 - target/openrisc/sys_helper.c | 1 - 4 files changed, 2 insertions(+), 16 deletions(-) delete mode 100644 include/tcg/insn-start-words.h diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h deleted file mode 100644 index 394c191da8d..00000000000 --- a/include/tcg/insn-start-words.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Define TARGET_INSN_START_WORDS - * Copyright (c) 2008 Fabrice Bellard - */ - -#ifndef TARGET_INSN_START_WORDS - -#include "cpu.h" - -# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) - -#endif /* TARGET_INSN_START_WORDS */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 2f8cf6db144..fc55a75a3cf 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,11 +65,12 @@ #include "internal-common.h" #include "internal-target.h" #include "tcg/perf.h" -#include "tcg/insn-start-words.h" #include "tcg/tcg-op.h" =20 TBContext tb_ctx; =20 +#define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) + /* * Encode VAL as a signed leb128 sequence at P. * Return P incremented past the encoded value. diff --git a/target/i386/helper.c b/target/i386/helper.c index 90e113c8b5a..1f819fbff65 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -30,7 +30,6 @@ #endif #include "qemu/log.h" #ifdef CONFIG_TCG -#include "tcg/insn-start-words.h" #include "tcg/tcg.h" #endif =20 diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index cf521461954..9da2bebbd5b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -27,7 +27,6 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #endif -#include "tcg/insn-start-words.h" #include "tcg/tcg.h" =20 #define TO_SPR(group, number) (((group) << 11) + (number)) --=20 2.47.1 From nobody Thu Apr 3 11:52:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742392073; cv=none; d=zohomail.com; s=zohoarc; b=kk7Wmm+sNwrTYqtEv54gYtZorhqF7MK89uB4hgQ7PSSbSyDDNDo4E6kZxkrMqODLBtmk2Qmssy36j4hK07OELjrAeUMee29YD9ly8sNTiDPwXBlUC7CTqWbznNJfabrRbp9CsE5jJ2788g55R6AabypmZ3sBPL31a2I2oVcnYLs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742392073; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=adKcjdToncFNSb7FtMey2mB2jyzU5Dr+yeVuZvMoV7M=; b=kClrBgOJcIWHtgnT0jWRdczO8GwjQPhwtgScNS6LzfiIjATPPb2YeWaETnlOjEFTnvoTBTRZ+8MY+Q2iaMhZQlrUXmSQ3jDWgUWJctZE6w5ysVNVLTxyYvwYLyNJSZNzAT6NfAgtzsjrTxdQ/qyv9LTiKNuoyo4N7OORnJvw8kc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742392073114855.4029493768498; Wed, 19 Mar 2025 06:47:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tutl0-0004IO-Jl; Wed, 19 Mar 2025 09:46:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tutkD-0003lX-LK for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:46:07 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tutkB-00047b-NX for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:46:05 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3914a5def6bso3815947f8f.1 for ; Wed, 19 Mar 2025 06:46:03 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-op.h | 16 ++++------------ target/i386/tcg/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/sh4/translate.c | 2 +- target/sparc/translate.c | 2 +- 7 files changed, 10 insertions(+), 18 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 0915043adf8..df234d4e1e0 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -31,17 +31,7 @@ static inline void tcg_gen_insn_start(uint64_t pc) =20 tcg_set_insn_start_param(op, 0, pc); } -#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 -static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1) -{ - unsigned insn_start_words =3D tcg_ctx->insn_start_words; - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, - insn_start_words * 64 / TCG_TARGET_REG_BITS); - - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, a1); -} -#elif TARGET_INSN_START_EXTRA_WORDS >=3D 2 +#elif TARGET_INSN_START_EXTRA_WORDS >=3D 1 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a= 2) { unsigned insn_start_words =3D tcg_ctx->insn_start_words; @@ -50,7 +40,9 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64= _t a1, uint64_t a2) =20 tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); - tcg_set_insn_start_param(op, 2, a2); + if (insn_start_words > 2) { + tcg_set_insn_start_param(op, 2, a2); + } } #endif =20 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a8935f487aa..0f1e72b1bc0 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3766,7 +3766,7 @@ static void i386_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) if (tb_cflags(dcbase->tb) & CF_PCREL) { pc_arg &=3D ~TARGET_PAGE_MASK; } - tcg_gen_insn_start(pc_arg, dc->cc_op); + tcg_gen_insn_start(pc_arg, dc->cc_op, 0); } =20 static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index dec2967fce4..9f7052aa6b5 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6037,7 +6037,7 @@ static void m68k_tr_tb_start(DisasContextBase *dcbase= , CPUState *cpu) static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); } =20 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b54e5ac4b2f..d256b317cfb 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1631,7 +1631,7 @@ static void mb_tr_insn_start(DisasContextBase *dcb, C= PUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); =20 - tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK, 0); } =20 static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7a6af183ae2..ff720e7fb6b 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1558,7 +1558,7 @@ static void openrisc_tr_insn_start(DisasContextBase *= dcbase, CPUState *cs) DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) - | (dc->base.num_insns > 1 ? 2 : 0)); + | (dc->base.num_insns > 1 ? 2 : 0), 0); } =20 static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index bcdd5588183..f140080c08c 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2248,7 +2248,7 @@ static void sh4_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); + tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags, 0); } =20 static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bfe63649db2..a775f425658 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5725,7 +5725,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) g_assert_not_reached(); } } - tcg_gen_insn_start(dc->pc, npc); + tcg_gen_insn_start(dc->pc, npc, 0); } =20 static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) --=20 2.47.1 From nobody Thu Apr 3 11:52:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1742392189; cv=none; d=zohomail.com; s=zohoarc; b=MJQ/lPnsKSvzjRNQJS/5IPBmqq0y+KFpNyE44afljjiwdlSGVLJ2ZTOwCD9evSRCes+P/fMH1wk/C4rbNNBeMheuet8vFwl034kCzY6ZBhEw9mIHwhzJTG4W68w9l6uZUYXRjLSNTtNM9Qz8wMcIoriQNTNh73DqHr0mXSRD+bs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1742392189; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=giq5jVWaUOn7Cy+Hw51AnglHBMySE1InchxU7/kS33s=; b=BJ/YAU090imF68vTYOmw/DAxrDHr0lR6N8CaGm0gaJbmj899lLdZrdeh05J32rPsT4Ryh0R69U2r4I4toGSSdulgz0EP3qoJDxPplWuQ8Jbogp8m1vrDC2G11ubh+p5nRACcpwt7DDe3sEWXHtr+yvqOW43GkF3UjgrdXPXHDmc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742392189872371.20852931142224; Wed, 19 Mar 2025 06:49:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tutl4-0004df-Vm; Wed, 19 Mar 2025 09:46:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tutkI-0003n9-F2 for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:46:13 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tutkG-00048f-9n for qemu-devel@nongnu.org; Wed, 19 Mar 2025 09:46:10 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3913fdd003bso414940f8f.1 for ; Wed, 19 Mar 2025 06:46:07 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-op.h | 15 +++------------ target/alpha/translate.c | 4 ++-- target/avr/translate.c | 2 +- target/loongarch/tcg/translate.c | 2 +- target/ppc/translate.c | 2 +- target/rx/translate.c | 2 +- target/tricore/translate.c | 2 +- target/xtensa/translate.c | 2 +- 8 files changed, 11 insertions(+), 20 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index df234d4e1e0..cf177a1fd3b 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -22,16 +22,6 @@ # error #endif =20 -#if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 -static inline void tcg_gen_insn_start(uint64_t pc) -{ - unsigned insn_start_words =3D tcg_ctx->insn_start_words; - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, - insn_start_words * 64 / TCG_TARGET_REG_BITS); - - tcg_set_insn_start_param(op, 0, pc); -} -#elif TARGET_INSN_START_EXTRA_WORDS >=3D 1 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a= 2) { unsigned insn_start_words =3D tcg_ctx->insn_start_words; @@ -39,12 +29,13 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint= 64_t a1, uint64_t a2) insn_start_words * 64 / TCG_TARGET_REG_BITS); =20 tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, a1); + if (insn_start_words > 1) { + tcg_set_insn_start_param(op, 1, a1); + } if (insn_start_words > 2) { tcg_set_insn_start_param(op, 2, a2); } } -#endif =20 #if TARGET_LONG_BITS =3D=3D 32 typedef TCGv_i32 TCGv; diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 2156c022146..6586ad0a69a 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2905,9 +2905,9 @@ static void alpha_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 if (ctx->pcrel) { - tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK); + tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK, 0, 0); } else { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } } =20 diff --git a/target/avr/translate.c b/target/avr/translate.c index 4ab71d8138b..c4f1a446467 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2686,7 +2686,7 @@ static void avr_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->npc); + tcg_gen_insn_start(ctx->npc, 0, 0); } =20 static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index e59e4ed25b1..ee359e804af 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -158,7 +158,7 @@ static void loongarch_tr_insn_start(DisasContextBase *d= cbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 /* diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a52cbc869ae..70458526282 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6558,7 +6558,7 @@ static void ppc_tr_tb_start(DisasContextBase *db, CPU= State *cs) =20 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } =20 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) diff --git a/target/rx/translate.c b/target/rx/translate.c index bbda703be86..16a865bd40f 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2210,7 +2210,7 @@ static void rx_tr_insn_start(DisasContextBase *dcbase= , CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 6819b776686..636137a5f73 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8376,7 +8376,7 @@ static void tricore_tr_insn_start(DisasContextBase *d= cbase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 4f02cefde34..888752f2279 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1159,7 +1159,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcba= se, CPUState *cpu) =20 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { - tcg_gen_insn_start(dcbase->pc_next); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d4863b4a7sm3162555e9.8.2025.03.19.06.46.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 19 Mar 2025 06:46:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742391971; x=1742996771; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=32mireliZ/dTP04oYHZ+DYdxeMqjsmJC3DhlT1EPop4=; b=D5uOYWQbgSLrxu6lXueZbRnA646xpJtAWS6eWmrEG54ZyC/SvkQ03o6gpD/kWFIYD9 IwX8Dq7ZD5NQHmY0Q2uLVyqPEuJ/JWPIFRifhQiMeQZSb4+Zqp7M8ZjekyXW1umoGL4G cVKgSIj6ZRRnBvYXp7fAy2dNuOoZtaGeDlC9+4PqpH/6Ssdwh7ualAQPGaTxLw939jKM z3lnzapAsVHxp3KHQQaCXhIfZIpmh2NWvYvSrpikBB/++ytS0QoxYjTBeJ4PBNPlyYge ZCrAxnG6ho2IDB0lTzHq2EsUdxaHIz7uGQ2O9oerTav57m+ZM1JDoVdMBTX4NZos8EbR JqZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742391971; x=1742996771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=32mireliZ/dTP04oYHZ+DYdxeMqjsmJC3DhlT1EPop4=; b=xB+ADuw92M4sTCCUHhGkWoKeCS9WbrFXoJkGWT1ZCkQ5b6zMeVr4bgFw5SAS5DM4BH 9wXzBt7kSc9KfoA+XvvG05IXnGada9xkcg0FQFhyTd+dfv3Sok8HPXXxYajr6YFOxHac tYkpK7Pz37JOXcr+sOQ2YRJtWcN2qfZ3X5buBIw1S68RB7oDlwN4ubjh9Bch+1/3jsoE 9ybM1dqsu/C+r5ds7VaaoyFkRl8GZVdM4uuGbSlyrvqDQsb8a6H0cKFNASsibu8nIGkX /UFF6Et49CQ2Jj5WGcsbVxB7zy62UZ3zPboUGebKezJZDDBTpf+dueHcPqcGJoAwFimm WY2A== X-Gm-Message-State: AOJu0Yxj+pzsuZoJ8JCGInKNf9TK3VLi3PrOrpI55s9NmiWmU5LOXwyb mFz240Z16bP+M9Gb46sKdUX6kjv05ljdQF3uA8DNJKyVWUDNrTHw5teOIPxaPC710XLs5r8JoQB f X-Gm-Gg: ASbGncvSuo5XixZ6F8v2mCCVdCg9Wb90DicBpf6G/ciAlruzfXXSv3bMRiZyubX7h9d KphVQJqscYZIG9bG4fly04iAtDcfVSNgl9OfgYHdkV4KaWeNhk2AlA0vZEC/xy3q6WzkAKgNyNa QJ67W3k0Tk2eiUF5CpLqTljBZaZhER+WD4+ceq9OsbI3NnLqIADDYGYfo2rJ0iWM2RAnXIEQ7Ui CIoBmVJAQYQOAlQQs+d/T64aYRRf/ShBl/rbIvz005rE2GWLXsk3voFGaTX/Lqi98RNGRpRnHWY 8ENkq9XEfprH8u+ZAcfeM+PHfVPK02pEBD0g7P4PccUXFDie1+LHt2SJg5D+oBYFaRkwyggHpcN thSCKRPUBuP+/7yYmtK8= X-Google-Smtp-Source: AGHT+IFzEqWCZZWPfFgIotp1OH3ucYkN3WVuP9zfofN+Mllp38MhkvTyRe8Phny4sWd19e4RX8yNbA== X-Received: by 2002:a05:600c:3594:b0:43c:fb36:d296 with SMTP id 5b1f17b1804b1-43d4383d0e7mr20984915e9.25.1742391971041; Wed, 19 Mar 2025 06:46:11 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , Peter Maydell , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 12/12] tcg: Uninline tcg_gen_insn_start() Date: Wed, 19 Mar 2025 14:45:06 +0100 Message-ID: <20250319134507.45045-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250319134507.45045-1-philmd@linaro.org> References: <20250319134507.45045-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742392058910019000 tcg_gen_insn_start() is now common to all TCG frontends. We don't need to keep it inlined, move it to tcg.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- include/tcg/tcg-op.h | 15 --------------- include/tcg/tcg.h | 2 ++ tcg/tcg.c | 15 +++++++++++++++ 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index cf177a1fd3b..470cb46225e 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -22,21 +22,6 @@ # error #endif =20 -static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a= 2) -{ - unsigned insn_start_words =3D tcg_ctx->insn_start_words; - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, - insn_start_words * 64 / TCG_TARGET_REG_BITS); - - tcg_set_insn_start_param(op, 0, pc); - if (insn_start_words > 1) { - tcg_set_insn_start_param(op, 1, a1); - } - if (insn_start_words > 2) { - tcg_set_insn_start_param(op, 2, a2); - } -} - #if TARGET_LONG_BITS =3D=3D 32 typedef TCGv_i32 TCGv; #define tcg_temp_new() tcg_temp_new_i32() diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 92a23e10218..d87d900bf81 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -609,6 +609,8 @@ static inline void tcg_set_insn_start_param(TCGOp *op, = int arg, uint64_t v) } } =20 +void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2); + /* The last op that was emitted. */ static inline TCGOp *tcg_last_op(void) { diff --git a/tcg/tcg.c b/tcg/tcg.c index e8950df2ad3..904f858e4dc 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3468,6 +3468,21 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old= _op, return new_op; } =20 +void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2) +{ + unsigned insn_start_words =3D tcg_ctx->insn_start_words; + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, + insn_start_words * 64 / TCG_TARGET_REG_BITS); + + tcg_set_insn_start_param(op, 0, pc); + if (insn_start_words > 1) { + tcg_set_insn_start_param(op, 1, a1); + } + if (insn_start_words > 2) { + tcg_set_insn_start_param(op, 2, a2); + } +} + static void move_label_uses(TCGLabel *to, TCGLabel *from) { TCGLabelUse *u; --=20 2.47.1