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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-225c6ba6c8dsm107725255ad.156.2025.03.19.01.03.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Mar 2025 01:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1742371424; x=1742976224; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nk46gytbFxIUMtZF+osZ4hsSwJ+YwCe1y9MoyWvsXsY=; b=NerZnh3mV/Z/U43RFw2wHFushHzTUlbGoqnpm/4fGDVkzpS6LfLqs0lXzMZZVGi1Jy ZWakA5sMZH5Q3IpQEsWneBNrc5u0mIFjkxgtkLyR8nEoyP87nnuI00xVcuVObrwFNqJ5 n0bk36sDBOL1ZKF4EV7/CEyKufJhQ5kkZIywkwFO+SUx0qWWkhCwvOIxmNwturH5xykq UvkubGEeR5Sx5xDBhjAUCI/JfVnM0oJxsPS/V49gB+UaxrW+V/ijGUgJ9zRYqIrLnXba hrGeknjzhoUaXC9svtLOqndCTzYcly2AV+M9NTFJqqJW1bkF3QFR8a15XPhZAh3qJ1kd PL/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742371424; x=1742976224; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nk46gytbFxIUMtZF+osZ4hsSwJ+YwCe1y9MoyWvsXsY=; b=vzDuUxOmZKXdj3mEIH81RblYwlFoNzy61Z5DfLmdy4pq0lsYH/gq9WBeglE9Hc65nT TPpE6XpckgwmocI12TBDyCrDio7QM9I1Khmos7di67dMgIFuFBZYDHdFZKa4I1fu7qAA W3F8KL9QYzgbrPX7VvHnc2mk7fTygng3+H8pqTHZQZTDoYuC1YzvGz5w2JKv1hvXLaA5 jGLoCHkAgQ2+M1X8rheghSwqzpe26cO8/r1pVS8EYe9ec9b5P5Sarkh76aCJ5ZDk4bQo pg7AOlYhwASgHUVrMOceNahTvO9O/FLuAsRpB+3OjpZLBabgsy7bk15KPWt4IP8f0c7Q IwMw== X-Gm-Message-State: AOJu0YxeUWGxWrNxJN4MY9xYfNOApVPvw2kYujuqYGPAsQglznT8FKkG qKJjs+E9+u/suE+t3f2gtsnNN5oUtnkfi4uWxV+6SddVh1m2nqzIhFbeOQ== X-Gm-Gg: ASbGncud+g0veMbuuM3oGoekhZW7ZEnYXr7N70lZ0PNnqp5y2IsUeK+i0InvZIZWmfj zEcHEf3WugtGjQXEayH9dl9mZmZoXIePF/dHLLhKFKHqqH8p08SSWrHgDguJcfMUU3FF5mUCS1M LKcp/iE36BApplglDb7VgKY3L+CEvbZ4OaXxnMZoPCvY1FMbWh8Cr1qCrzv2Mto6m6GY7P8hML4 HfzX16AkQfdleQBChOFVdEKdw+kYZrGCCGnx99uabPluFoKRN8/QmoFC2R84f/WLjAceFnLmEee jqNDL1Ulv8qWVmQVq3i1NaUTVaocb6MCDEdi18cHdtotNToPwekca8x1SjYMszoQuYw+1XKDer9 ydwjp7Ivx1eWJYloZH0XuGkVp7jaJTLST/E4yK3CJV2V3uTTE X-Google-Smtp-Source: AGHT+IETKGTgtWdhTLBzOTanlaXh5w0XH2wuhyZWxVLUWU0IC/C5DShjOUG/xjq8UfhxQ2/Pu7jjRQ== X-Received: by 2002:a17:903:2341:b0:223:7006:4db2 with SMTP id d9443c01a7336-226499399fbmr29298995ad.31.1742371423956; Wed, 19 Mar 2025 01:03:43 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Chao Liu , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 08/10] target/riscv: fix handling of nop for vstart >= vl in some vector instruction Date: Wed, 19 Mar 2025 18:03:06 +1000 Message-ID: <20250319080308.609520-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250319080308.609520-1-alistair.francis@wdc.com> References: <20250319080308.609520-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1742371525972019100 Content-Type: text/plain; charset="utf-8" From: Chao Liu Recently, when I was writing a RISCV test, I found that when VL is set to 0= , the instruction should be nop, but when I tested it, I found that QEMU will tre= at all elements as tail elements, and in the case of VTA=3D1, write all elemen= ts to 1. After troubleshooting, it was found that the vext_vx_rm_1 function was call= ed in the vext_vx_rm_2, and then the vext_set_elems_1s function was called to pro= cess the tail element, but only VSTART >=3D vl was checked in the vext_vx_rm_1 function, which caused the tail element to still be processed even if it was returned in advance. So I've made the following change: Put VSTART_CHECK_EARLY_EXIT(env) at the beginning of the vext_vx_rm_2 funct= ion, so that the VSTART register is checked correctly. Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when vstart >=3D vl") Signed-off-by: Chao Liu Reviewed-by: Daniel Henrique Barboza Message-ID: Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 217d2f60a5..67b3bafebb 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2175,8 +2175,6 @@ vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, uint32_t vl, uint32_t vm, int vxrm, opivv2_rm_fn *fn, uint32_t vma, uint32_t esz) { - VSTART_CHECK_EARLY_EXIT(env, vl); - for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ @@ -2200,6 +2198,8 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, uint32_t vta =3D vext_vta(desc); uint32_t vma =3D vext_vma(desc); =20 + VSTART_CHECK_EARLY_EXIT(env, vl); + switch (env->vxrm) { case 0: /* rnu */ vext_vv_rm_1(vd, v0, vs1, vs2, @@ -2302,8 +2302,6 @@ vext_vx_rm_1(void *vd, void *v0, target_long s1, void= *vs2, uint32_t vl, uint32_t vm, int vxrm, opivx2_rm_fn *fn, uint32_t vma, uint32_t esz) { - VSTART_CHECK_EARLY_EXIT(env, vl); - for (uint32_t i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ @@ -2327,6 +2325,8 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void= *vs2, uint32_t vta =3D vext_vta(desc); uint32_t vma =3D vext_vma(desc); =20 + VSTART_CHECK_EARLY_EXIT(env, vl); + switch (env->vxrm) { case 0: /* rnu */ vext_vx_rm_1(vd, v0, s1, vs2, @@ -4662,6 +4662,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t i; \ TD s1 =3D *((TD *)vs1 + HD(0)); \ \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ for (i =3D env->vstart; i < vl; i++) { \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -4750,6 +4752,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t i; \ TD s1 =3D *((TD *)vs1 + HD(0)); \ \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ for (i =3D env->vstart; i < vl; i++) { \ TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -4914,6 +4918,8 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPU= RISCVState *env, int i; bool first_mask_bit =3D false; =20 + VSTART_CHECK_EARLY_EXIT(env, vl); + for (i =3D env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { /* set masked-off elements to 1s */ @@ -4986,6 +4992,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPUR= ISCVState *env, \ uint32_t sum =3D 0; = \ int i; \ \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vm && !vext_elem_mask(v0, i)) { \ /* set masked-off elements to 1s */ \ @@ -5344,6 +5352,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vta =3D vext_vta(desc); = \ uint32_t num =3D 0, i; = \ \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ for (i =3D env->vstart; i < vl; i++) { = \ if (!vext_elem_mask(vs1, i)) { \ continue; \ --=20 2.48.1