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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250319-gpiodev-v1-7-76da4e5800a1@yadro.com> References: <20250319-gpiodev-v1-0-76da4e5800a1@yadro.com> In-Reply-To: <20250319-gpiodev-v1-0-76da4e5800a1@yadro.com> To: qemu-devel@nongnu.org Cc: Linus Walleij , Bartosz Golaszewski , "Enrico Weigelt, metux IT consult" , Viresh Kumar , Eric Blake , Markus Armbruster , Michael Roth , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Eduardo Habkost , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , qemu-arm@nongnu.org, Nikita Shubin , Nikita Shubin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1742371072; l=25956; i=n.shubin@yadro.com; s=20230718; h=from:subject:message-id; bh=cNBgCGBMLxXgwvJD8kFv/hNFULw4AM2bNKWA3qo9Ik0=; b=da/v3MMHqbf3iyZmB9TJpfufqJeB1STsA8hGs9bqbbyHrwgvkALZVqcpMMVYp6kDLHyQHhCSG c/2q74IEYPjBQwh+RLjfAOQccPcADl9KIqXQlBPDccX4ULYyCqoqzg4 X-Developer-Key: i=n.shubin@yadro.com; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for n.shubin@yadro.com/20230718 with auth_id=161 X-Original-From: Nikita Shubin Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2600:3c04:e001:324:0:1991:8:25; envelope-from=devnull+n.shubin.yadro.com@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.332, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 19 Mar 2025 08:49:31 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: n.shubin@yadro.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1742388663372019000 From: Nikita Shubin Add GUSE (FUSE based kernel module similiar to CUSE) based backend. This allows transparent usage of Linux GPIO UAPI based tools like in kernel tools/gpio or libgpiod. libgpiod requires some modification to allow "/sys/class/guse" in gpiod_check_gpiochip_device(). It requires guse module to be loaded and providing DEVICE()->id for GPIO module, for example: ``` DEVICE(&s->gpio)->id =3D g_strdup("aspeed-gpio0"); ``` The id should be provided to gpiodev with any `devname` that doesn't exists in /dev: ``` -gpiodev guse,id=3Daspeed-gpio0,devname=3Dgpiochip10 ``` That /dev/gpiochip10 can be used in the same way we usually operate with gpiochip's. Link: http://git.maquefel.me/?p=3Dqemu-gpiodev/libgpiod.git;a=3Dshortlog;h= =3Drefs/heads/nshubin/guse-fix Link: http://git.maquefel.me/?p=3Dqemu-gpiodev/guse.git;a=3Dsummary Link: http://git.maquefel.me/?p=3Dqemu-gpiodev/libfuse.git;a=3Dshortlog;h= =3Drefs/heads/nshubin/guse Signed-off-by: Nikita Shubin --- gpiodev/gpio-guse.c | 747 +++++++++++++++++++++++++++++++++++++++++++++= ++++ gpiodev/meson.build | 1 + include/gpiodev/gpio.h | 1 + qapi/gpio.json | 31 +- 4 files changed, 777 insertions(+), 3 deletions(-) diff --git a/gpiodev/gpio-guse.c b/gpiodev/gpio-guse.c new file mode 100644 index 0000000000000000000000000000000000000000..7e94c825653d42aae6e273acb79= d5e9f8eec293c --- /dev/null +++ b/gpiodev/gpio-guse.c @@ -0,0 +1,747 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * QEMU GPIO GUSE based backend. + * + * Author: 2025 Nikita Shubin + * + */ +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "qemu/option.h" +#include "qemu/log.h" +#include "qemu/lockable.h" +#include "qapi/error.h" +#include "gpiodev/gpio.h" +#include "chardev/char.h" +#include "chardev/char-fe.h" + +#define FUSE_USE_VERSION 31 +#include +#include +#include +#undef FUSE_USE_VERSION + +#include +#include + +#define GUSE_DEVICE_INODE_FLAG BIT_ULL(63) +#define GUSE_MAX_WATCH 64 +#define GUSE_MAX_EVENTS 64 + +typedef struct GusedevLineWatch { + uint64_t i_node; + struct fuse_pollhandle *ph; + + /* since we can have multiply requests per device we need own masks */ + struct { + unsigned long risen; + unsigned long fallen; + + /* special for GPIO_V2_LINE_FLAG_OUTPUT */ + unsigned long mask; + } mask; + + /* required to match mask with actual offsets */ + uint32_t num_lines; + uint32_t offsets[GPIO_V2_LINES_MAX]; + + QemuMutex event_lock; + uint32_t num_events; + struct gpio_v2_line_event events[GUSE_MAX_EVENTS]; + + QSIMPLEQ_ENTRY(GusedevLineWatch) next; +} GusedevLineWatch; + +typedef struct GusedevConfigWatch { + uint64_t i_node; + struct fuse_pollhandle *ph; + + unsigned long *mask; + + uint32_t num_events; + struct gpio_v2_line_info_changed events[GUSE_MAX_EVENTS]; + QSIMPLEQ_ENTRY(GusedevConfigWatch) next; +} GusedevConfigWatch; + +typedef struct GusedevGpiodev { + Gpiodev parent; + + char *devname; + struct fuse_session *fuse_session; + struct fuse_buf fuse_buf; + + QemuMutex linereq_lock; + QSIMPLEQ_HEAD(, GusedevLineWatch) linereq; + + QemuMutex configreq_lock; + QSIMPLEQ_HEAD(, GusedevConfigWatch) configreq; +} GusedevGpiodev; + +DECLARE_INSTANCE_CHECKER(GusedevGpiodev, GPIODEV_GUSEDEV, + TYPE_GPIODEV_GUSEDEV) + +static GusedevLineWatch *gpio_gusedev_find_linereq(GusedevGpiodev *d, uint= 64_t i_node) +{ + GusedevLineWatch *e; + + QSIMPLEQ_FOREACH(e, &d->linereq, next) { + if (e->i_node =3D=3D i_node) { + return e; + } + } + + return NULL; +} + +static GusedevLineWatch *gpio_gusedev_allocate_linereq(GusedevGpiodev *d, = uint64_t i_node) +{ + GusedevLineWatch *e =3D g_new0(GusedevLineWatch, 1); + + e->i_node =3D i_node; + + QSIMPLEQ_INSERT_TAIL(&d->linereq, e, next); + + return e; +} + +static void gpio_gusedev_free_linereq(GusedevGpiodev *d, GusedevLineWatch = *w) +{ + GusedevLineWatch *entry, *next; + + QSIMPLEQ_FOREACH_SAFE(entry, &d->linereq, next, next) { + if (entry->i_node =3D=3D w->i_node) { + QSIMPLEQ_REMOVE(&d->linereq, entry, GusedevLineWatch, next); + if (entry->ph) { + fuse_pollhandle_destroy(entry->ph); + } + g_free(entry); + } + } +} + +static GusedevConfigWatch *gpio_gusedev_find_configreq(GusedevGpiodev *d, = uint64_t i_node) +{ + GusedevConfigWatch *e; + + QSIMPLEQ_FOREACH(e, &d->configreq, next) { + if (e->i_node =3D=3D i_node) { + return e; + } + } + + return NULL; +} + +static GusedevConfigWatch *gpio_gusedev_allocate_configreq(GusedevGpiodev = *d, + uint64_t i_node) +{ + GusedevConfigWatch *e =3D g_new0(GusedevConfigWatch, 1); + + e->i_node =3D i_node; + e->mask =3D bitmap_new(d->parent.lines); + + QSIMPLEQ_INSERT_TAIL(&d->configreq, e, next); + + return e; +} + +static void gpio_gusedev_free_configreq(GusedevGpiodev *d, + GusedevConfigWatch *w) +{ + GusedevConfigWatch *entry, *next; + + QSIMPLEQ_FOREACH_SAFE(entry, &d->configreq, next, next) { + if (entry->i_node =3D=3D w->i_node) { + QSIMPLEQ_REMOVE(&d->configreq, entry, GusedevConfigWatch, next= ); + if (entry->ph) { + fuse_pollhandle_destroy(entry->ph); + } + g_free(entry->mask); + g_free(entry); + } + } +} + +static inline uint64_t timespec_to_ns(struct timespec ts) +{ + return (uint64_t)ts.tv_nsec + 1000000000ULL * (uint64_t)ts.tv_sec; +} + +static void gpio_gusedev_push_config(GusedevGpiodev *d, uint32_t offset, + enum gpio_v2_line_changed_type event) +{ + GusedevConfigWatch *e; + struct timespec ts; + uint64_t ts_ns; + + timespec_get(&ts, TIME_UTC); + ts_ns =3D timespec_to_ns(ts); + + QEMU_LOCK_GUARD(&d->configreq_lock); + QSIMPLEQ_FOREACH(e, &d->configreq, next) { + if (test_bit(offset, e->mask)) { + struct gpio_v2_line_info_changed *changed; + uint32_t num_events =3D e->num_events; + if (++num_events > GUSE_MAX_EVENTS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: max config events numb= er exeeded\n", + __func__); + continue; + } + + changed =3D &e->events[e->num_events]; + changed->timestamp_ns =3D ts_ns; + changed->event_type =3D event; + changed->info.offset =3D offset; + + e->num_events =3D num_events; + + if (e->ph) { + fuse_notify_poll(e->ph); + fuse_pollhandle_destroy(e->ph); + e->ph =3D NULL; + } + } + } +} + +static void gpio_gusedev_push_event(GusedevGpiodev *d, uint32_t offset, + enum gpio_v2_line_event_id event) +{ + GusedevLineWatch *e; + struct timespec ts; + uint64_t ts_ns; + + timespec_get(&ts, TIME_UTC); + ts_ns =3D timespec_to_ns(ts); + + QEMU_LOCK_GUARD(&d->linereq_lock); + QSIMPLEQ_FOREACH(e, &d->linereq, next) { + bool notify =3D false; + if ((event & GPIO_V2_LINE_EVENT_RISING_EDGE) + && test_bit(offset, &e->mask.risen)) { + notify =3D true; + } + + if ((event & GPIO_V2_LINE_EVENT_FALLING_EDGE) + && test_bit(offset, &e->mask.fallen)) { + notify =3D true; + } + + if (notify) { + struct gpio_v2_line_event *info; + uint32_t num_events =3D e->num_events; + if (++num_events > GUSE_MAX_EVENTS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: max config events numb= er exeeded\n", + __func__); + continue; + } + + info =3D &e->events[e->num_events]; + info->timestamp_ns =3D ts_ns; + info->id =3D event; + info->offset =3D offset; + + e->num_events =3D num_events; + + if (e->ph) { + fuse_notify_poll(e->ph); + fuse_pollhandle_destroy(e->ph); + e->ph =3D NULL; + } + } + } +} + +static void gpio_gusedev_line_event(Gpiodev *g, uint32_t offset, + QEMUGpioLineEvent event) +{ + GusedevGpiodev *d =3D GPIODEV_GUSEDEV(g); + + gpio_gusedev_push_event(d, offset, (enum gpio_v2_line_event_id)event); +} + +static void gpio_gusedev_config_event(Gpiodev *g, uint32_t offset, + QEMUGpioConfigEvent event) +{ + GusedevGpiodev *d =3D GPIODEV_GUSEDEV(g); + + gpio_gusedev_push_config(d, offset, (enum gpio_v2_line_changed_type)ev= ent); +} + +static void gusedev_init(void *userdata, struct fuse_conn_info *conn) +{ + (void)userdata; + + /* Disable the receiving and processing of FUSE_INTERRUPT requests */ + conn->no_interrupt =3D 1; +} + +static void gusedev_destroy(void *private_data) +{ + (void)private_data; +} + +static void gusedev_open(fuse_req_t req, fuse_ino_t ino, + struct fuse_file_info *fi) +{ + fuse_reply_open(req, fi); +} + +static void gusedev_release(fuse_req_t req, fuse_ino_t ino, + struct fuse_file_info *fi) +{ + GusedevGpiodev *d =3D fuse_req_userdata(req); + + if (ino & GUSE_DEVICE_INODE_FLAG) { + GusedevConfigWatch *e; + + e =3D gpio_gusedev_find_configreq(d, ino); + if (e) { + gpio_gusedev_free_configreq(d, e); + } + } else { + GusedevLineWatch *e; + + e =3D gpio_gusedev_find_linereq(d, ino); + if (e) { + gpio_gusedev_free_linereq(d, e); + } + } + + fuse_reply_err(req, 0); +} + +static void gusedev_read(fuse_req_t req, fuse_ino_t ino, size_t size, off_= t off, + struct fuse_file_info *fi) +{ + GusedevGpiodev *d =3D fuse_req_userdata(req); + + if (ino & GUSE_DEVICE_INODE_FLAG) { + GusedevConfigWatch *e; + + e =3D gpio_gusedev_find_configreq(d, ino); + if (e && e->num_events) { + fuse_reply_buf(req, (char *)&e->events, sizeof(e->events[0]) *= e->num_events); + e->num_events =3D 0; + return; + } + } else { + GusedevLineWatch *e; + + e =3D gpio_gusedev_find_linereq(d, ino); + if (e && e->num_events) { + fuse_reply_buf(req, (char *)&e->events, sizeof(e->events[0]) *= e->num_events); + e->num_events =3D 0; + return; + } + } + + fuse_reply_buf(req, NULL, 0); +} + +static void gusedev_poll_config(fuse_req_t req, fuse_ino_t ino, struct fus= e_file_info *fi, + struct fuse_pollhandle *ph) +{ + GusedevGpiodev *d =3D fuse_req_userdata(req); + GusedevConfigWatch *e; + + QEMU_LOCK_GUARD(&d->configreq_lock); + e =3D gpio_gusedev_find_configreq(d, ino); + if (!e) { + fuse_reply_poll(req, POLLERR); + return; + } + + if (ph) { + if (e->ph) { + fuse_pollhandle_destroy(e->ph); + } + + e->ph =3D ph; + } + + if (e->num_events) { + fuse_reply_poll(req, POLLIN); + } else { + fuse_reply_poll(req, 0); + } +} + +static void gusedev_poll_line(fuse_req_t req, fuse_ino_t ino, struct fuse_= file_info *fi, + struct fuse_pollhandle *ph) +{ + GusedevGpiodev *d =3D fuse_req_userdata(req); + GusedevLineWatch *e; + + QEMU_LOCK_GUARD(&d->linereq_lock); + e =3D gpio_gusedev_find_linereq(d, ino); + if (!e) { + fuse_reply_poll(req, POLLERR); + return; + } + + if (ph) { + if (e->ph) { + fuse_pollhandle_destroy(e->ph); + } + + e->ph =3D ph; + } + + if (e->num_events) { + fuse_reply_poll(req, POLLIN); + } else { + fuse_reply_poll(req, 0); + } +} + +static void gusedev_poll(fuse_req_t req, fuse_ino_t ino, struct fuse_file_= info *fi, + struct fuse_pollhandle *ph) +{ + if (ino & GUSE_DEVICE_INODE_FLAG) { + gusedev_poll_config(req, ino, fi, ph); + } else { + gusedev_poll_line(req, ino, fi, ph); + } +} + +static int gusedev_chipinfo(fuse_req_t req) +{ + GusedevGpiodev *d =3D fuse_req_userdata(req); + struct gpiochip_info info =3D { 0 }; + + qemu_gpio_chip_info(&d->parent, &info.lines, info.name, info.label); + + return fuse_reply_ioctl(req, 0, &info, sizeof(info)); +} + +static int gusedev_lineinfo(fuse_req_t req, const void *in_buf) +{ + struct gpio_v2_line_info *in =3D (struct gpio_v2_line_info *)in_buf; + GusedevGpiodev *d =3D fuse_req_userdata(req); + struct gpio_v2_line_info reply =3D { 0 }; + uint32_t offset =3D in->offset; + gpio_line_info info =3D { 0 }; + + if (offset > d->parent.lines) { + return fuse_reply_err(req, EINVAL); + } + + info.offset =3D offset; + qemu_gpio_line_info(&d->parent, &info); + g_strlcpy(reply.name, info.name, GPIO_MAX_NAME_SIZE); + reply.flags =3D info.flags; + + return fuse_reply_ioctl(req, 0, &reply, sizeof(reply)); +} + +static int gusedev_linerequest(fuse_req_t req, fuse_ino_t ino, + const void *in_buf) +{ + struct gpio_v2_line_request *in =3D (struct gpio_v2_line_request *)in_= buf; + GusedevGpiodev *d =3D fuse_req_userdata(req); + struct gpio_v2_line_request reply; + GusedevLineWatch *watch; + int i; + + /* line request not available for device inode */ + if (ino & GUSE_DEVICE_INODE_FLAG) { + return fuse_reply_err(req, EINVAL); + } + + watch =3D gpio_gusedev_allocate_linereq(d, ino); + if (!watch) { + return fuse_reply_err(req, ENOMEM); + } + + for (i =3D 0; i < in->num_lines; i++) { + bool notify =3D false; + + if (in->config.flags & GPIO_V2_LINE_FLAG_INPUT) { + if (in->config.flags & GPIO_V2_LINE_FLAG_EDGE_RISING) { + watch->mask.risen |=3D BIT_ULL(in->offsets[i]); + qemu_gpio_add_event_watch(&d->parent, in->offsets[i], + GPIO_EVENT_RISING_EDGE); + notify =3D true; + } + + if (in->config.flags & GPIO_V2_LINE_FLAG_EDGE_FALLING) { + watch->mask.fallen |=3D BIT_ULL(in->offsets[i]); + qemu_gpio_add_event_watch(&d->parent, in->offsets[i], + GPIO_EVENT_FALLING_EDGE); + notify =3D true; + } + /* TODO: check if lines are input and don't allow to change direct= ion */ + } else if (in->config.flags & GPIO_V2_LINE_FLAG_OUTPUT) { + watch->mask.mask |=3D BIT_ULL(in->offsets[i]); + } + + /* dispatch config change event */ + if (notify) { + gpio_gusedev_push_config(d, in->offsets[i], + GPIO_V2_LINE_CHANGED_REQUESTED); + } + } + + memcpy(&reply, in_buf, sizeof(reply)); + + return fuse_reply_ioctl(req, 0, &reply, sizeof(reply)); +} + +static int gusedev_get_line_values(fuse_req_t req, fuse_ino_t ino, + const void *in_buf) +{ + struct gpio_v2_line_values *values =3D (struct gpio_v2_line_values *)i= n_buf; + GusedevGpiodev *d =3D fuse_req_userdata(req); + struct gpio_v2_line_values reply =3D { 0 }; + GusedevLineWatch *e; + int idx; + + e =3D gpio_gusedev_find_linereq(d, ino); + if (!e) { + return fuse_reply_err(req, EINVAL); + } + + idx =3D find_first_bit((unsigned long *)values->mask, e->num_lines); + while (idx < e->num_lines) { + reply.bits |=3D qemu_gpio_get_line_value(&d->parent, e->offsets[id= x]); + idx =3D find_next_bit((unsigned long *)values->mask, e->num_lines,= idx + 1); + } + + reply.mask =3D values->mask; + + return fuse_reply_ioctl(req, 0, &reply, sizeof(reply)); +} + +/* TODO: merge with gusedev_set_line_values() */ +static int gusedev_set_line_values(fuse_req_t req, fuse_ino_t ino, + const void *in_buf) +{ + struct gpio_v2_line_values *values =3D (struct gpio_v2_line_values *)i= n_buf; + GusedevGpiodev *d =3D fuse_req_userdata(req); + struct gpio_v2_line_values reply =3D { 0 }; + GusedevLineWatch *e; + int idx; + + e =3D gpio_gusedev_find_linereq(d, ino); + if (!e) { + return fuse_reply_err(req, EINVAL); + } + + idx =3D find_first_bit((unsigned long *)&values->mask, e->num_lines); + while (idx < e->num_lines) { + uint8_t bit =3D test_bit(idx, (unsigned long *)&values->bits); + qemu_gpio_set_line_value(&d->parent, e->offsets[idx], bit); + idx =3D find_next_bit((unsigned long *)&values->mask, e->num_lines= , idx + 1); + } + + reply.bits =3D values->bits; + reply.mask =3D values->mask; + + return fuse_reply_ioctl(req, 0, &reply, sizeof(reply)); +} + +static int gusedev_set_line_watch(fuse_req_t req, fuse_ino_t ino, + const void *in_buf, bool watch) +{ + struct gpio_v2_line_info *info =3D (struct gpio_v2_line_info *)in_buf; + GusedevGpiodev *d =3D fuse_req_userdata(req); + struct gpio_v2_line_info reply =3D { 0 }; + GusedevConfigWatch *e; + + e =3D gpio_gusedev_find_configreq(d, ino); + + /* + * If not found allocate it, because unlike linereq configreq is added= separately + * per each line. + */ + if (!e) { + e =3D gpio_gusedev_allocate_configreq(d, ino); + } + + if (watch) { + qemu_gpio_add_config_watch(&d->parent, info->offset); + set_bit(info->offset, e->mask); + } else { + qemu_gpio_clear_config_watch(&d->parent, info->offset); + clear_bit(info->offset, e->mask); + } + + memcpy(&reply, info, sizeof(reply)); + + return fuse_reply_ioctl(req, 0, &reply, sizeof(reply)); +} + +static void gusedev_ioctl(fuse_req_t req, fuse_ino_t ino, unsigned int cmd, + void *arg, struct fuse_file_info *fi, unsigned f= lags, + const void *in_buf, size_t in_bufsz, size_t out_= bufsz) +{ + bool add_watch =3D false; + int ret; + + if (flags & FUSE_IOCTL_COMPAT) { + fuse_reply_err(req, ENOSYS); + return; + } + + switch (cmd) { + case GPIO_GET_CHIPINFO_IOCTL: + ret =3D gusedev_chipinfo(req); + break; + case GPIO_V2_GET_LINEINFO_IOCTL: + ret =3D gusedev_lineinfo(req, in_buf); + break; + /* GPIO_V2_GET_LINE_IOCTL is also processed by guse module. */ + case GPIO_V2_GET_LINE_IOCTL: + ret =3D gusedev_linerequest(req, ino, in_buf); + break; + case GPIO_V2_LINE_GET_VALUES_IOCTL: + ret =3D gusedev_get_line_values(req, ino, in_buf); + break; + case GPIO_V2_LINE_SET_VALUES_IOCTL: + ret =3D gusedev_set_line_values(req, ino, in_buf); + break; + case GPIO_V2_GET_LINEINFO_WATCH_IOCTL: + add_watch =3D true; + /* fallthrough */ + case GPIO_GET_LINEINFO_UNWATCH_IOCTL: + ret =3D gusedev_set_line_watch(req, ino, in_buf, add_watch); + break; + case GPIO_V2_LINE_SET_CONFIG_IOCTL: + default: + ret =3D fuse_reply_err(req, EINVAL); + } + + if (ret) { + qemu_log_mask(LOG_GUEST_ERROR, "gusedev_ioctl() failed with %d\n", + ret); + } +} + +static const struct guse_cdev_lowlevel_ops gusedev_glop =3D { + .init =3D gusedev_init, + .destroy =3D gusedev_destroy, + .open =3D gusedev_open, + .release =3D gusedev_release, + .read =3D gusedev_read, + .poll =3D gusedev_poll, + .ioctl =3D gusedev_ioctl, +}; + +static void read_from_fuse_export(void *opaque) +{ + GusedevGpiodev *guse =3D opaque; + int ret; + + do { + ret =3D fuse_session_receive_buf(guse->fuse_session, &guse->fuse_b= uf); + } while (ret =3D=3D -EINTR); + + if (ret < 0) { + return; + } + + fuse_session_process_buf(guse->fuse_session, &guse->fuse_buf); +} + +static int setup_guse_export(GusedevGpiodev *guse, Error **errp) +{ + char dev_name[128] =3D "DEVNAME=3D"; + const char *dev_info_argv[] =3D { dev_name }; + char *curdir =3D get_current_dir_name(); + struct fuse_session *session =3D NULL; + const char *argv[3]; + struct guse_info ci; + int multithreaded; + AioContext *ctx; + + strncat(dev_name, guse->devname, sizeof(dev_name) - sizeof("DEVNAME=3D= ")); + + argv[0] =3D ""; /* Dummy program name */ + argv[1] =3D "-d"; + argv[2] =3D NULL; + + ci.dev_major =3D 0; + ci.dev_minor =3D 0; + ci.dev_info_argc =3D 1; + ci.dev_info_argv =3D dev_info_argv; + + session =3D guse_lowlevel_setup(ARRAY_SIZE(argv) - 1, (char **)argv, &= ci, &gusedev_glop, + &multithreaded, guse); + if (session =3D=3D NULL) { + error_setg(errp, "guse_lowlevel_setup failed"); + errno =3D EINVAL; + return -1; + } + + /* FIXME: fuse_daemonize() calls chdir("/") */ + chdir(curdir); + g_free(curdir); + + ctx =3D iohandler_get_aio_context(); + + aio_set_fd_handler(ctx, fuse_session_fd(session), + read_from_fuse_export, NULL, + NULL, NULL, guse); + + guse->fuse_session =3D session; + + return 0; +} + +static void gpio_gusedev_open(Gpiodev *gpio, GpiodevBackend *backend, + Error **errp) +{ + GpiodevGusedev *opts =3D backend->u.gusedev.data; + GusedevGpiodev *d =3D GPIODEV_GUSEDEV(gpio); + + d->devname =3D g_strdup(opts->devname); + + QSIMPLEQ_INIT(&d->linereq); + QSIMPLEQ_INIT(&d->configreq); + + qemu_mutex_init(&d->linereq_lock); + qemu_mutex_init(&d->configreq_lock); + + setup_guse_export(d, errp); +} + +static void gpio_gusedev_parse(QemuOpts *opts, GpiodevBackend *backend, + Error **errp) +{ + const char *devname =3D qemu_opt_get(opts, "devname"); + /* TODO: add bool debug for fuse debug */ + GpiodevGusedev *ggusedev; + + if (devname =3D=3D NULL) { + error_setg(errp, "gpiodev: gusedev: no devname given"); + return; + } + + backend->type =3D GPIODEV_BACKEND_KIND_GUSEDEV; + ggusedev =3D backend->u.gusedev.data =3D g_new0(GpiodevGusedev, 1); + ggusedev->devname =3D g_strdup(devname); +} + +static void gpio_gusedev_class_init(ObjectClass *oc, void *data) +{ + GpiodevClass *cc =3D GPIODEV_CLASS(oc); + + cc->parse =3D &gpio_gusedev_parse; + cc->open =3D &gpio_gusedev_open; + cc->line_event =3D &gpio_gusedev_line_event; + cc->config_event =3D &gpio_gusedev_config_event; +} + +static const TypeInfo gpio_gusedev_type_info[] =3D { + { + .name =3D TYPE_GPIODEV_GUSEDEV, + .parent =3D TYPE_GPIODEV, + .class_init =3D gpio_gusedev_class_init, + .instance_size =3D sizeof(GusedevGpiodev), + /* .instance_finalize =3D gpio_gusedev_finalize, */ + }, +}; + +DEFINE_TYPES(gpio_gusedev_type_info); + diff --git a/gpiodev/meson.build b/gpiodev/meson.build index 64d3abb4e3d72cba0c26b665515a0f97e82fb5d9..32eae1c3f8bc856e8b7f4a4bb49= d796147f59da7 100644 --- a/gpiodev/meson.build +++ b/gpiodev/meson.build @@ -4,4 +4,5 @@ gpiodev_ss.add(files( 'gpio.c', )) =20 +gpiodev_ss.add(when: fuse, if_true: files('gpio-guse.c')) gpiodev_ss =3D gpiodev_ss.apply({}) diff --git a/include/gpiodev/gpio.h b/include/gpiodev/gpio.h index a34d805ccc0bf5a25986b118dcc0b2cc0a55572c..d3b95410d3a570480d187354ad3= 84f9a23b102e6 100644 --- a/include/gpiodev/gpio.h +++ b/include/gpiodev/gpio.h @@ -56,6 +56,7 @@ struct Gpiodev { OBJECT_DECLARE_TYPE(Gpiodev, GpiodevClass, GPIODEV) =20 #define TYPE_GPIODEV_CHARDEV "gpiodev-chardev" +#define TYPE_GPIODEV_GUSEDEV "gpiodev-guse" =20 struct GpiodevClass { ObjectClass parent_class; diff --git a/qapi/gpio.json b/qapi/gpio.json index 1c2b7af36813ff52cbb3a44e64a2e5a5d8658d62..e3cdca793260212622a30947eae= a61bd523e98fb 100644 --- a/qapi/gpio.json +++ b/qapi/gpio.json @@ -21,12 +21,36 @@ ## # @GpiodevBackendKind: # -# @chardev: chardevs +# @chardev: Gpio dev over chardev backend +# @gusedev: Gpio dev over GUSE FUSE module # # Since: 9.2 ## { 'enum': 'GpiodevBackendKind', - 'data': [ 'chardev' ] } + 'data': [ 'chardev', + { 'name': 'gusedev', 'if': 'CONFIG_LINUX' } ] } + +## +# @GpiodevGusedev: +# +# Configuration info for guse gpiodevs. +# +# @devname: Name of device created in /dev +# +# Since: 9.2 +## + { 'struct': 'GpiodevGusedev', + 'data': { 'devname': 'str' } } + +## +# @GpiodevGusedevWrapper: +# +# @data: Configuration info for chardev gpiodevs +# +# Since: 9.2 +## +{ 'struct': 'GpiodevGusedevWrapper', + 'data': { 'data': 'GpiodevGusedev' } } =20 ## # @GpiodevChardev: @@ -65,4 +89,5 @@ { 'union': 'GpiodevBackend', 'base': { 'type': 'GpiodevBackendKind' }, 'discriminator': 'type', - 'data': { 'chardev': 'GpiodevChardevWrapper' } } \ No newline at end of file + 'data': { 'chardev': 'GpiodevChardevWrapper', + 'gusedev': { 'type': 'GpiodevGusedevWrapper', 'if': 'CONFIG_LI= NUX' } } } \ No newline at end of file --=20 2.45.2