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Iglesias" , Peter Maydell , Alistair Francis , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , YannickV Subject: [PATCH 05/21] hw/dma/zynq: Notify devcfg on FPGA reset via SLCR control Date: Tue, 18 Mar 2025 14:07:56 +0100 Message-ID: <20250318130817.119636-6-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250318130817.119636-1-corvin.koehne@gmail.com> References: <20250318130817.119636-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1742303660496019000 From: YannickV When the FPGA_RST_CTRL register in the SLCR (System Level Control Register) is written to, the devcfg (Device Configuration) should indicate the finished reset. Problems occure when Loaders trigger a reset via SLCR and poll for the done flag in devcfg. Since the flag will never be set, this can result in an endless loop. A callback function `slcr_reset_handler` is added to the `XlnxZynqDevcfg` structure. The `slcr_reset` function sets the `PCFG_DONE` flag when triggered by an FPGA reset in the SLCR. The SLCR write handler calls the `slcr_reset` function when the FPGA reset control register (`R_FPGA_RST_CTRL`) is written with the reset value. Signed-off-by: Yannick Vo=C3=9Fen --- hw/dma/xlnx-zynq-devcfg.c | 7 +++++++ hw/misc/zynq_slcr.c | 16 ++++++++++++++++ include/hw/dma/xlnx-zynq-devcfg.h | 1 + 3 files changed, 24 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 03b5280228..611a57b4d4 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -138,6 +138,11 @@ static void xlnx_zynq_devcfg_update_ixr(XlnxZynqDevcfg= *s) qemu_set_irq(s->irq, ~s->regs[R_INT_MASK] & s->regs[R_INT_STS]); } =20 +static void slcr_reset (DeviceState *dev) { + XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(dev); + s->regs[R_INT_STS] |=3D R_INT_STS_PCFG_DONE_MASK; +} + static void xlnx_zynq_devcfg_reset(DeviceState *dev) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(dev); @@ -374,6 +379,8 @@ static void xlnx_zynq_devcfg_init(Object *obj) XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(obj); RegisterInfoArray *reg_array; =20 + s->slcr_reset_handler =3D slcr_reset; + sysbus_init_irq(sbd, &s->irq); =20 memory_region_init(&s->iomem, obj, "devcfg", XLNX_ZYNQ_DEVCFG_R_MAX * = 4); diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index a766bab182..9b3220f354 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -26,6 +26,7 @@ #include "qom/object.h" #include "hw/qdev-properties.h" #include "qapi/error.h" +#include "hw/dma/xlnx-zynq-devcfg.h" =20 #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -576,6 +577,21 @@ static void zynq_slcr_write(void *opaque, hwaddr offse= t, zynq_slcr_compute_clocks(s); zynq_slcr_propagate_clocks(s); break; + case R_FPGA_RST_CTRL: + if (val =3D=3D 0) { + Object *devcfgObject =3D + object_resolve_type_unambiguous("xlnx.ps7-dev-cfg", NU= LL); + if (!devcfgObject) { + break; + } + DeviceState *devcfg =3D OBJECT_CHECK(DeviceState, devcfgObject, + "xlnx.ps7-dev-cfg"); + XlnxZynqDevcfg *zynqdevcfg =3D XLNX_ZYNQ_DEVCFG(devcfg); + if (zynqdevcfg) { + zynqdevcfg->slcr_reset_handler(devcfg); + } + } + break; } } =20 diff --git a/include/hw/dma/xlnx-zynq-devcfg.h b/include/hw/dma/xlnx-zynq-d= evcfg.h index 2ab054e598..f48a630c5a 100644 --- a/include/hw/dma/xlnx-zynq-devcfg.h +++ b/include/hw/dma/xlnx-zynq-devcfg.h @@ -56,6 +56,7 @@ struct XlnxZynqDevcfg { uint8_t dma_cmd_fifo_num; =20 bool is_initialized; + void (*slcr_reset_handler) (DeviceState *dev); =20 uint32_t regs[XLNX_ZYNQ_DEVCFG_R_MAX]; RegisterInfo regs_info[XLNX_ZYNQ_DEVCFG_R_MAX]; --=20 2.49.0