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([38.39.164.180]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73711694b2csm8519195b3a.129.2025.03.17.21.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 21:51:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1742273502; x=1742878302; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wWxuqDn4s8YGDZbkaUM66zf0LxM3gMsyBA+i/Ql3r9I=; b=AHwWMggX6uoudT6S9mSuOirqQ990MnsvlxNyZ1ZljMmsEjPAYPB/5aRyYJlCWhZv7B koEJTLj9+hqsjuUJtu0+WJwLtZTDG37BxhxIzQZjYN6QKe4rTZ7mB6hNDTC/zY/AZrBF t6+4XXKIydJVOUwZT8y0caveWBsLsX1+eZrzO6PgJUOEZTU7nZTKRY4vk1Kcsq2nCLRR Pep/6P4NAOWz+rlwn5/elrtto/jzmUwE6FbH0B93G4Zr6xW8RxWQsgAIMXXvxP1TzAYD Xzedb09L5AP6vX3TkvzJfc7dU81m7tGNgmu7P4n/d9LF/pIZD/6X9P7qPZENvcgVzXGX v+0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742273502; x=1742878302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wWxuqDn4s8YGDZbkaUM66zf0LxM3gMsyBA+i/Ql3r9I=; b=Kqdyt2X3Nu3J9GBr19Nx0grWbzZHLbhSGZlFF12kII2YpfUcQM5mQQ4jsmi4079Ls6 ePBkoWk4Knw+eJWnPVYfwQsirMRQklr4T2PkmjATU8ZLuRi+bxsZPPuV2O/2XHCJKFL1 +r0Hk23nEAopDBqTWXBdRUu3i4Mcbo8yGa7m4g6rvTo3SMLotVJ0/O1Nqd2Ze7S36bAO RHICCL3jjqhpTWZZSrBIHRonodzkOsPZbAcsZI7AwkYsf1TEJnW1rCVfl8nPvguTnU0h x8PtzXI5VtT20t6ZCgzjRIXYv7LBWzXsDYu08KwzSgBa4t48trf+I2FYoBw3+SWKUn0Q KGsw== X-Gm-Message-State: AOJu0YyhBMhtR4oO2tlQ4M5DOGrKVTEHn4LNt1eBjborNaVfMr8wnK7p a5IA6l4n4HDeKQMA1Z6gta0ApbKDoQwiAOTp+QMZLRrR29NFebOZ0T7ztHpG6gzxZ6boKPscX2w / X-Gm-Gg: ASbGncsfuINsTBSnxf+THEacqb/XUy/F0K7HFc+gO8+b6NVj5kKTQsRGz3RaRlP1Yyu Kcv2hXijalyiCCN2MkTr+i/OvQvdXYeeiL8zfvb3F+d8T+LQIE7ZQVEcv3kNelic+n4ETfcC7lj g89dOTfCKI3e3QpNCLgvOHHctAdd/6PbWmkxAm4x0FEJmyrZOGPYmK++XoT9UHcqxxc8RzoAgce IFtJSEADe0DOKb7Trzly2SRy+xIqIhAIRqabH/gdoWtYV/b3l38irW4rqwXlovA+fp/2TbsFYlq qvmMC8FPeKhOHo7Mk9iqWVoX+aRbIuJcd4Hp/wUb1ZCu X-Google-Smtp-Source: AGHT+IFe64voSZsfhB6tCQvZ6JsS5YIy++Gra9YOoX3NHYIjPdoV//u+oQg4+pI0ZxYcfpZboB2sWw== X-Received: by 2002:a05:6a20:9c92:b0:1f5:6680:82b6 with SMTP id adf61e73a8af0-1fa461552c5mr3160029637.38.1742273502551; Mon, 17 Mar 2025 21:51:42 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , qemu-arm@nongnu.org, alex.bennee@linaro.org, Peter Maydell , kvm@vger.kernel.org, Paolo Bonzini , Richard Henderson , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 10/13] target/arm/cpu: define same set of registers for aarch32 and aarch64 Date: Mon, 17 Mar 2025 21:51:22 -0700 Message-Id: <20250318045125.759259-11-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250318045125.759259-1-pierrick.bouvier@linaro.org> References: <20250318045125.759259-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1742273681633019000 Content-Type: text/plain; charset="utf-8" To eliminate TARGET_AARCH64, we need to make various definitions common between 32 and 64 bit Arm targets. Added registers are used only by aarch64 code, and the only impact is on the size of CPUARMState, and added zarray (ARMVectorReg zarray[ARM_MAX_VQ * 16]) member (+64KB) It could be eventually possible to allocate this array only for aarch64 emulation, but I'm not sure it's worth the hassle to save a few KB per vcpu. Running qemu-system takes already several hundreds of MB of (resident) memory, and qemu-user takes dozens of MB of (resident) memory anyway. Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/arm/cpu.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 00f78d64bd8..51b6428cfec 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -175,7 +175,6 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; =20 -#ifdef TARGET_AARCH64 /* In AArch32 mode, predicate registers do not exist at all. */ typedef struct ARMPredicateReg { uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); @@ -185,7 +184,6 @@ typedef struct ARMPredicateReg { typedef struct ARMPACKey { uint64_t lo, hi; } ARMPACKey; -#endif =20 /* See the commentary above the TBFLAG field definitions. */ typedef struct CPUARMTBFlags { @@ -656,13 +654,11 @@ typedef struct CPUArchState { struct { ARMVectorReg zregs[32]; =20 -#ifdef TARGET_AARCH64 /* Store FFR as pregs[16] to make it easier to treat as any other.= */ #define FFR_PRED_NUM 16 ARMPredicateReg pregs[17]; /* Scratch space for aa64 sve predicate temporary. */ ARMPredicateReg preg_tmp; -#endif =20 /* We store these fpcsr fields separately for convenience. */ uint32_t qc[4] QEMU_ALIGNED(16); @@ -707,7 +703,6 @@ typedef struct CPUArchState { uint32_t cregs[16]; } iwmmxt; =20 -#ifdef TARGET_AARCH64 struct { ARMPACKey apia; ARMPACKey apib; @@ -739,7 +734,6 @@ typedef struct CPUArchState { * to keep the offsets into the rest of the structure smaller. */ ARMVectorReg zarray[ARM_MAX_VQ * 16]; -#endif =20 struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; --=20 2.39.5