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Mon, 17 Mar 2025 09:44:08 -0700 (PDT) From: anisa.su887@gmail.com To: qemu-devel@nongnu.org Cc: jonathan.cameron@huawei.com, nifan.cxl@gmail.com, dave@stgolabs.net, linux-cxl@vger.kernel.org, Anisa Su Subject: [PATCH 8/9] cxl-mailbox-utils: 0x5604 - FMAPI Initiate DC Add Date: Mon, 17 Mar 2025 16:31:35 +0000 Message-ID: <20250317164204.2299371-9-anisa.su887@gmail.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317164204.2299371-1-anisa.su887@gmail.com> References: <20250317164204.2299371-1-anisa.su887@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=anisa.su887@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 17 Mar 2025 15:48:34 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1742241016097019100 Content-Type: text/plain; charset="utf-8" From: Anisa Su FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section 7.6.= 7.6.5 Signed-off-by: Anisa Su --- hw/cxl/cxl-mailbox-utils.c | 173 ++++++++++++++++++++++++++++++++++++ hw/mem/cxl_type3.c | 8 +- include/hw/cxl/cxl_device.h | 4 + 3 files changed, 181 insertions(+), 4 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 77cf0fdb15..5bcbd434b7 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -127,6 +127,8 @@ enum { #define GET_HOST_DC_REGION_CONFIG 0x1 #define SET_DC_REGION_CONFIG 0x2 #define GET_DC_REGION_EXTENT_LIST 0x3 + #define INITIATE_DC_ADD 0x4 + }; =20 /* CCI Message Format CXL r3.1 Figure 7-19 */ @@ -3669,6 +3671,170 @@ static CXLRetCode cmd_fm_get_dc_region_extent_list(= const struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 +static CXLRetCode cxl_mbox_dc_prescriptive_sanity_check(CXLType3Dev *dcd, + uint16_t host_id, + uint32_t ext_count, + CXLDCExtentRaw ext= ents[], + CXLDCEventType typ= e) +{ + CXLDCExtentRaw ext; + CXLDCRegion *reg =3D NULL; + int i, j; + + if (dcd->dc.num_regions =3D=3D 0) { + qemu_log_mask(LOG_UNIMP, + "No dynamic capacity support from the device.\n"); + return CXL_MBOX_UNSUPPORTED; + } + + /* TODO: host id check will be added later, currently host id must be = 0. */ + if (host_id !=3D 0) { + return CXL_MBOX_INVALID_INPUT; + } + + for (i =3D 0; i < ext_count; i++) { + ext =3D extents[i]; + + if (ext.len =3D=3D 0) { + return CXL_MBOX_INVALID_EXTENT_LIST; + } + + reg =3D cxl_find_dc_region(dcd, ext.start_dpa, ext.len); + if (!reg) { + return CXL_MBOX_INVALID_EXTENT_LIST; + } + + if (ext.len % reg->block_size || ext.start_dpa % reg->block_size) { + return CXL_MBOX_INVALID_EXTENT_LIST; + } + + /* Check requested extents do not overlap with each other. */ + for (j =3D i + 1; j < ext_count; j++) { + if (ranges_overlap(ext.start_dpa, ext.len, extents[j].start_dp= a, + extents[j].len)) { + return CXL_MBOX_INVALID_EXTENT_LIST; + } + } + + if (type =3D=3D DC_EVENT_ADD_CAPACITY) { + /* Check requested extents do not overlap with existing extent= s. */ + if (cxl_extents_overlaps_dpa_range(&dcd->dc.extents, + ext.start_dpa, ext.len)) { + return CXL_MBOX_INVALID_EXTENT_LIST; + } + } + } + + return CXL_MBOX_SUCCESS; +} + +/* + * CXL r3.2 Section 7.6.7.6.5 Initiate Dynamic Capacity Add (Opcode 5604h) + */ +static CXLRetCode cmd_fm_initiate_dc_add(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + struct { + uint16_t host_id; + uint8_t selection_policy; + uint8_t reg_num; + uint64_t length; + uint8_t tag[0x10]; + uint32_t ext_count; + CXLDCExtentRaw extents[]; + } QEMU_PACKED *in =3D (void *)payload_in; + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); + g_autofree CXLDCExtentRaw *event_rec_exts =3D NULL; + CXLEventDynamicCapacity event_rec =3D {}; + CXLDCExtentGroup *group =3D NULL; + CXLDCExtentRaw ext; + int rc, i; + + switch (in->selection_policy) { + case CXL_EXTENT_SELECTION_POLICY_PRESCRIPTIVE: + /* Adding extents causes exceeding device's extent tracking abilit= y. */ + if (in->ext_count + ct3d->dc.total_extent_count > + CXL_NUM_EXTENTS_SUPPORTED) { + return CXL_MBOX_RESOURCES_EXHAUSTED; + } + rc =3D cxl_mbox_dc_prescriptive_sanity_check(ct3d, + in->host_id, + in->ext_count, + in->extents, + DC_EVENT_ADD_CAPACITY); + if (rc) { + return rc; + } + + /* Prepare extents for Event Record */ + event_rec_exts =3D g_new0(CXLDCExtentRaw, in->ext_count); + for (i =3D 0; i < in->ext_count; i++) { + ext =3D in->extents[i]; + event_rec_exts[i].start_dpa =3D ext.start_dpa; + event_rec_exts[i].len =3D ext.len; + memset(event_rec_exts[i].tag, 0, 0x10); + event_rec_exts[i].shared_seq =3D 0; + + /* Check requested extents do not overlap with pending extents= . */ + if (cxl_extent_groups_overlaps_dpa_range(&ct3d->dc.extents_pen= ding, + ext.start_dpa, ext.le= n)) { + return CXL_MBOX_INVALID_EXTENT_LIST; + } + + /* Create extent group to add to pending list. */ + group =3D cxl_insert_extent_to_extent_group(group, + event_rec_exts[i].st= art_dpa, + event_rec_exts[i].le= n, + event_rec_exts[i].ta= g, + event_rec_exts[i].sh= ared_seq); + } + + /* Add requested extents to pending list. */ + if (group) { + cxl_extent_group_list_insert_tail(&ct3d->dc.extents_pending, g= roup); + } + + /* Create event record and insert to event log */ + cxl_mbox_dc_event_create_record_hdr(ct3d, &event_rec.hdr); + event_rec.type =3D DC_EVENT_ADD_CAPACITY; + /* FIXME: for now, validity flag is cleared */ + event_rec.validity_flags =3D 0; + /* FIXME: Currently only support 1 host */ + event_rec.host_id =3D 0; + /* updated_region_id only valid for DC_EVENT_REGION_CONFIG_UPDATED= */ + event_rec.updated_region_id =3D 0; + for (i =3D 0; i < in->ext_count; i++) { + memcpy(&event_rec.dynamic_capacity_extent, + &event_rec_exts[i], + sizeof(CXLDCExtentRaw)); + + event_rec.flags =3D 0; + if (i < in->ext_count - 1) { + /* Set "More" flag */ + event_rec.flags |=3D BIT(0); + } + + if (cxl_event_insert(&ct3d->cxl_dstate, + CXL_EVENT_TYPE_DYNAMIC_CAP, + (CXLEventRecordRaw *)&event_rec)) { + cxl_event_irq_assert(ct3d); + } + } + + return CXL_MBOX_SUCCESS; + default: + qemu_log_mask(LOG_UNIMP, + "CXL extent selection policy not supported.\n"); + return CXL_MBOX_INVALID_INPUT; + } + + return CXL_MBOX_SUCCESS; +} + static const struct cxl_cmd cxl_cmd_set[256][256] =3D { [INFOSTAT][BACKGROUND_OPERATION_ABORT] =3D { "BACKGROUND_OPERATION_ABO= RT", cmd_infostat_bg_op_abort, 0, 0 }, @@ -3804,6 +3970,13 @@ static const struct cxl_cmd cxl_cmd_set_fm_dcd[256][= 256] =3D { CXL_MBOX_IMMEDIATE_DATA_CHANGE)}, [FMAPI_DCD_MGMT][GET_DC_REGION_EXTENT_LIST] =3D { "GET_DC_REGION_EXTEN= T_LIST", cmd_fm_get_dc_region_extent_list, 12, 0}, + [FMAPI_DCD_MGMT][INITIATE_DC_ADD] =3D { "INIT_DC_ADD", + cmd_fm_initiate_dc_add, ~0, + (CXL_MBOX_CONFIG_CHANGE_COLD_RESET | + CXL_MBOX_CONFIG_CHANGE_CONV_RESET | + CXL_MBOX_CONFIG_CHANGE_CXL_RESET | + CXL_MBOX_IMMEDIATE_CONFIG_CHANGE | + CXL_MBOX_IMMEDIATE_DATA_CHANGE)}, }; =20 /* diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index b742b2bb8d..ccc619fe10 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1982,8 +1982,8 @@ void qmp_cxl_inject_memory_module_event(const char *p= ath, CxlEventLog log, * the list. * Return value: return true if has overlaps; otherwise, return false */ -static bool cxl_extents_overlaps_dpa_range(CXLDCExtentList *list, - uint64_t dpa, uint64_t len) +bool cxl_extents_overlaps_dpa_range(CXLDCExtentList *list, + uint64_t dpa, uint64_t len) { CXLDCExtent *ent; Range range1, range2; @@ -2028,8 +2028,8 @@ bool cxl_extents_contains_dpa_range(CXLDCExtentList *= list, return false; } =20 -static bool cxl_extent_groups_overlaps_dpa_range(CXLDCExtentGroupList *lis= t, - uint64_t dpa, uint64_t le= n) +bool cxl_extent_groups_overlaps_dpa_range(CXLDCExtentGroupList *list, + uint64_t dpa, uint64_t len) { CXLDCExtentGroup *group; =20 diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 217003a29d..1d5831a0b6 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -809,4 +809,8 @@ bool ct3_test_region_block_backed(CXLType3Dev *ct3d, ui= nt64_t dpa, void cxl_assign_event_header(CXLEventRecordHdr *hdr, const QemuUUID *uuid, uint32_t flags, uint8_t length, uint64_t timestamp); +bool cxl_extents_overlaps_dpa_range(CXLDCExtentList *list, + uint64_t dpa, uint64_t len); +bool cxl_extent_groups_overlaps_dpa_range(CXLDCExtentGroupList *list, + uint64_t dpa, uint64_t len); #endif --=20 2.47.2