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Mon, 17 Mar 2025 09:44:02 -0700 (PDT) From: anisa.su887@gmail.com To: qemu-devel@nongnu.org Cc: jonathan.cameron@huawei.com, nifan.cxl@gmail.com, dave@stgolabs.net, linux-cxl@vger.kernel.org, Anisa Su Subject: [PATCH 6/9] cxl-mailbox-utils: 0x5602 - FMAPI Set DC Region Config Date: Mon, 17 Mar 2025 16:31:33 +0000 Message-ID: <20250317164204.2299371-7-anisa.su887@gmail.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317164204.2299371-1-anisa.su887@gmail.com> References: <20250317164204.2299371-1-anisa.su887@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=anisa.su887@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 17 Mar 2025 15:48:39 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1742241043647019100 Content-Type: text/plain; charset="utf-8" From: Anisa Su FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.= 7.6.3 Signed-off-by: Anisa Su --- hw/cxl/cxl-mailbox-utils.c | 100 +++++++++++++++++++++++++++++++++++ hw/mem/cxl_type3.c | 2 +- include/hw/cxl/cxl_device.h | 3 ++ include/hw/cxl/cxl_mailbox.h | 6 +++ 4 files changed, 110 insertions(+), 1 deletion(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 4bb51bf3e8..51ead2b152 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -125,6 +125,7 @@ enum { FMAPI_DCD_MGMT =3D 0x56, #define GET_DCD_INFO 0x0 #define GET_HOST_DC_REGION_CONFIG 0x1 + #define SET_DC_REGION_CONFIG 0x2 }; =20 /* CCI Message Format CXL r3.1 Figure 7-19 */ @@ -3494,6 +3495,98 @@ static CXLRetCode cmd_fm_get_host_dc_region_config(c= onst struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 +static void cxl_mbox_dc_event_create_record_hdr(CXLType3Dev *ct3d, + CXLEventRecordHdr *hdr) +{ + /* + * CXL r3.1 section 8.2.9.2.1.6: Dynamic Capacity Event Record + * + * All Dynamic Capacity event records shall set the Event Record Sever= ity + * field in the Common Event Record Format to Informational Event. All + * Dynamic Capacity related events shall be logged in the Dynamic Capa= city + * Event Log. + */ + uint8_t flags =3D 1 << CXL_EVENT_TYPE_INFO; + + st24_le_p(&hdr->flags, flags); + hdr->length =3D sizeof(struct CXLEventDynamicCapacity); + memcpy(&hdr->id, &dynamic_capacity_uuid, sizeof(hdr->id)); + stq_le_p(&hdr->timestamp, cxl_device_get_timestamp(&ct3d->cxl_dstate)); +} + +/* + * CXL r3.2 section 7.6.7.6.3: Set Host DC Region Configuration (Opcode 56= 02) + */ +static CXLRetCode cmd_fm_set_dc_region_config(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + struct { + uint8_t reg_id; + uint8_t rsvd[3]; + uint64_t block_sz; + uint8_t flags; + uint8_t rsvd2[3]; + } QEMU_PACKED *in; + CXLType3Dev *ct3d =3D CXL_TYPE3(cci->d); + CXLEventDynamicCapacity dcEvent =3D {}; + CXLDCRegion *region; + + if (ct3d->dc.num_regions =3D=3D 0) { + return CXL_MBOX_UNSUPPORTED; + } + + /* + * TODO: Fail with CXL_MBOX_INVALID_SECURITY_STATE if + * device has been locked + */ + + in =3D (void *)payload_in; + region =3D &ct3d->dc.regions[in->reg_id]; + + /* + * TODO: Fail if sanitize bit doesn't match current config and "the de= vice + * does not support reconfiguration of the Sanitize on Release setting= ." + * Currently not reconfigurable, so always fail if sanitize bit + * doesn't match. + */ + if ((in->flags & 1) !=3D (region->flags & 1)) { + return CXL_MBOX_UNSUPPORTED; + } + + if (in->reg_id >=3D DCD_MAX_NUM_REGION) { + return CXL_MBOX_UNSUPPORTED; + } + + /* Check that no extents are in the region being reconfigured */ + if (!bitmap_empty(region->blk_bitmap, region->len / region->block_size= )) { + return CXL_MBOX_UNSUPPORTED; + } + + /* Free bitmap and create new one for new block size. */ + g_free(region->blk_bitmap); + region->blk_bitmap =3D bitmap_new(region->len / in->block_sz); + + /* Create event record and insert into event log */ + cxl_mbox_dc_event_create_record_hdr(ct3d, &dcEvent.hdr); + dcEvent.type =3D DC_EVENT_REGION_CONFIG_UPDATED; + /* FIXME: for now, validity flag is cleared */ + dcEvent.validity_flags =3D 0; + /* FIXME: Currently only support 1 host */ + dcEvent.host_id =3D 0; + dcEvent.updated_region_id =3D in->reg_id; + + if (cxl_event_insert(&ct3d->cxl_dstate, + CXL_EVENT_TYPE_DYNAMIC_CAP, + (CXLEventRecordRaw *)&dcEvent)) { + cxl_event_irq_assert(ct3d); + } + return CXL_MBOX_SUCCESS; +} + static const struct cxl_cmd cxl_cmd_set[256][256] =3D { [INFOSTAT][BACKGROUND_OPERATION_ABORT] =3D { "BACKGROUND_OPERATION_ABO= RT", cmd_infostat_bg_op_abort, 0, 0 }, @@ -3620,6 +3713,13 @@ static const struct cxl_cmd cxl_cmd_set_fm_dcd[256][= 256] =3D { cmd_fm_get_dcd_info, 0, 0}, [FMAPI_DCD_MGMT][GET_HOST_DC_REGION_CONFIG] =3D { "GET_HOST_DC_REGION_= CONFIG", cmd_fm_get_host_dc_region_config, 4, 0}, + [FMAPI_DCD_MGMT][SET_DC_REGION_CONFIG] =3D { "SET_DC_REGION_CONFIG", + cmd_fm_set_dc_region_config, 16, + (CXL_MBOX_CONFIG_CHANGE_COLD_RESET | + CXL_MBOX_CONFIG_CHANGE_CONV_RESET | + CXL_MBOX_CONFIG_CHANGE_CXL_RESET | + CXL_MBOX_IMMEDIATE_CONFIG_CHANGE | + CXL_MBOX_IMMEDIATE_DATA_CHANGE)}, }; =20 /* diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index ac74e62875..b742b2bb8d 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1686,7 +1686,7 @@ void qmp_cxl_inject_correctable_error(const char *pat= h, CxlCorErrorType type, pcie_aer_inject_error(PCI_DEVICE(obj), &err); } =20 -static void cxl_assign_event_header(CXLEventRecordHdr *hdr, +void cxl_assign_event_header(CXLEventRecordHdr *hdr, const QemuUUID *uuid, uint32_t flags, uint8_t length, uint64_t timestamp) { diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 81b826f570..217003a29d 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -806,4 +806,7 @@ void ct3_clear_region_block_backed(CXLType3Dev *ct3d, u= int64_t dpa, uint64_t len); bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len); +void cxl_assign_event_header(CXLEventRecordHdr *hdr, + const QemuUUID *uuid, uint32_t flags, + uint8_t length, uint64_t timestamp); #endif diff --git a/include/hw/cxl/cxl_mailbox.h b/include/hw/cxl/cxl_mailbox.h index 8e1c7c5f15..820c411cbb 100644 --- a/include/hw/cxl/cxl_mailbox.h +++ b/include/hw/cxl/cxl_mailbox.h @@ -8,6 +8,7 @@ #ifndef CXL_MAILBOX_H #define CXL_MAILBOX_H =20 +#define CXL_MBOX_CONFIG_CHANGE_COLD_RESET (1) #define CXL_MBOX_IMMEDIATE_CONFIG_CHANGE (1 << 1) #define CXL_MBOX_IMMEDIATE_DATA_CHANGE (1 << 2) #define CXL_MBOX_IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -15,6 +16,11 @@ #define CXL_MBOX_SECURITY_STATE_CHANGE (1 << 5) #define CXL_MBOX_BACKGROUND_OPERATION (1 << 6) #define CXL_MBOX_BACKGROUND_OPERATION_ABORT (1 << 7) +#define CXL_MBOX_SECONDARY_MBOX_SUPPORTED (1 << 8) +#define CXL_MBOX_REQUEST_ABORT_BACKGROUND_OP_SUPPORTED (1 << 9) +#define CXL_MBOX_CEL_10_TO_11_VALID (1 << 10) +#define CXL_MBOX_CONFIG_CHANGE_CONV_RESET (1 << 11) +#define CXL_MBOX_CONFIG_CHANGE_CXL_RESET (1 << 12) =20 #define CXL_LOG_CAP_CLEAR_SUPPORTED (1 << 0) #define CXL_LOG_CAP_POPULATE_SUPPORTED (1 << 1) --=20 2.47.2