From nobody Wed Dec 17 15:38:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742204701881986.2461394223037; Mon, 17 Mar 2025 02:45:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tu70y-00041y-4g; Mon, 17 Mar 2025 05:44:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tu70v-00040h-Jq for qemu-devel@nongnu.org; Mon, 17 Mar 2025 05:44:05 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tu70q-0006zM-5S for qemu-devel@nongnu.org; Mon, 17 Mar 2025 05:44:05 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxDGvb7tdn+MyZAA--.63667S3; Mon, 17 Mar 2025 17:43:55 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBxb8fa7tdnP3tPAA--.30227S3; Mon, 17 Mar 2025 17:43:54 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 1/4] hw/intc/loongarch_pch: Use default path when access some registers Date: Mon, 17 Mar 2025 17:43:51 +0800 Message-Id: <20250317094354.1028221-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250317094354.1028221-1-maobibo@loongson.cn> References: <20250317094354.1028221-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBxb8fa7tdnP3tPAA--.30227S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742204703368019000 Content-Type: text/plain; charset="utf-8" For some registers such as PCH_PIC_AUTO_CTRL0_LO etc which are not emulated, emulation driver does nothing. It is the same with default handling, here remove these registers and use the default path for simplification. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index acd75ccb0c..3fc4227159 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -108,11 +108,6 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaq= ue, hwaddr addr, case PCH_PIC_HTMSI_EN_HI: val =3D s->htmsi_en >> 32; break; - case PCH_PIC_AUTO_CTRL0_LO: - case PCH_PIC_AUTO_CTRL0_HI: - case PCH_PIC_AUTO_CTRL1_LO: - case PCH_PIC_AUTO_CTRL1_HI: - break; default: break; } @@ -191,11 +186,6 @@ static void loongarch_pch_pic_low_writew(void *opaque,= hwaddr addr, case PCH_PIC_HTMSI_EN_HI: s->htmsi_en =3D get_writew_val(s->htmsi_en, data, 1); break; - case PCH_PIC_AUTO_CTRL0_LO: - case PCH_PIC_AUTO_CTRL0_HI: - case PCH_PIC_AUTO_CTRL1_LO: - case PCH_PIC_AUTO_CTRL1_HI: - break; default: break; } --=20 2.39.3 From nobody Wed Dec 17 15:38:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742204713959841.8909392330108; Mon, 17 Mar 2025 02:45:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tu70x-00041Q-BP; Mon, 17 Mar 2025 05:44:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tu70v-00040i-Lt for qemu-devel@nongnu.org; Mon, 17 Mar 2025 05:44:05 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tu70q-0006zQ-2V for qemu-devel@nongnu.org; Mon, 17 Mar 2025 05:44:05 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bxjazc7tdn_cyZAA--.31062S3; Mon, 17 Mar 2025 17:43:56 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBxb8fa7tdnP3tPAA--.30227S4; Mon, 17 Mar 2025 17:43:55 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 2/4] hw/intc/loongarch_pch: Rename register name Date: Mon, 17 Mar 2025 17:43:52 +0800 Message-Id: <20250317094354.1028221-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250317094354.1028221-1-maobibo@loongson.cn> References: <20250317094354.1028221-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBxb8fa7tdnP3tPAA--.30227S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742204715731019000 Content-Type: text/plain; charset="utf-8" For some registers with width 8 bytes, its name is something like PCH_PIC_INT_ID_LO and PCH_PIC_INT_ID_HI. From hardware manual, register name is PCH_PIC_INT_ID instead. Here name PCH_PIC_INT_ID is used, and PCH_PIC_INT_ID + 4 is used for PCH_PIC_INT_ID_HI. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c | 32 +++++++++++++------------- hw/loongarch/virt.c | 2 +- include/hw/intc/loongarch_pic_common.h | 27 ++++++++-------------- 3 files changed, 26 insertions(+), 35 deletions(-) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index 3fc4227159..428809b927 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -79,10 +79,10 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaqu= e, hwaddr addr, uint32_t offset =3D addr & 0xfff; =20 switch (offset) { - case PCH_PIC_INT_ID_LO: + case PCH_PIC_INT_ID: val =3D PCH_PIC_INT_ID_VAL; break; - case PCH_PIC_INT_ID_HI: + case PCH_PIC_INT_ID + 4: /* * With 7A1000 manual * bit 0-15 pch irqchip version @@ -90,22 +90,22 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaqu= e, hwaddr addr, */ val =3D deposit32(PCH_PIC_INT_ID_VER, 16, 16, s->irq_num - 1); break; - case PCH_PIC_INT_MASK_LO: + case PCH_PIC_INT_MASK: val =3D (uint32_t)s->int_mask; break; - case PCH_PIC_INT_MASK_HI: + case PCH_PIC_INT_MASK + 4: val =3D s->int_mask >> 32; break; - case PCH_PIC_INT_EDGE_LO: + case PCH_PIC_INT_EDGE: val =3D (uint32_t)s->intedge; break; - case PCH_PIC_INT_EDGE_HI: + case PCH_PIC_INT_EDGE + 4: val =3D s->intedge >> 32; break; - case PCH_PIC_HTMSI_EN_LO: + case PCH_PIC_HTMSI_EN: val =3D (uint32_t)s->htmsi_en; break; - case PCH_PIC_HTMSI_EN_HI: + case PCH_PIC_HTMSI_EN + 4: val =3D s->htmsi_en >> 32; break; default: @@ -135,7 +135,7 @@ static void loongarch_pch_pic_low_writew(void *opaque, = hwaddr addr, trace_loongarch_pch_pic_low_writew(size, addr, data); =20 switch (offset) { - case PCH_PIC_INT_MASK_LO: + case PCH_PIC_INT_MASK: old =3D s->int_mask; s->int_mask =3D get_writew_val(old, data, 0); old_valid =3D (uint32_t)old; @@ -146,7 +146,7 @@ static void loongarch_pch_pic_low_writew(void *opaque, = hwaddr addr, pch_pic_update_irq(s, (~old_valid & data), 0); } break; - case PCH_PIC_INT_MASK_HI: + case PCH_PIC_INT_MASK + 4: old =3D s->int_mask; s->int_mask =3D get_writew_val(old, data, 1); old_valid =3D (uint32_t)(old >> 32); @@ -159,20 +159,20 @@ static void loongarch_pch_pic_low_writew(void *opaque= , hwaddr addr, pch_pic_update_irq(s, int_mask << 32, 0); } break; - case PCH_PIC_INT_EDGE_LO: + case PCH_PIC_INT_EDGE: s->intedge =3D get_writew_val(s->intedge, data, 0); break; - case PCH_PIC_INT_EDGE_HI: + case PCH_PIC_INT_EDGE + 4: s->intedge =3D get_writew_val(s->intedge, data, 1); break; - case PCH_PIC_INT_CLEAR_LO: + case PCH_PIC_INT_CLEAR: if (s->intedge & data) { s->intirr &=3D (~data); pch_pic_update_irq(s, data, 0); s->intisr &=3D (~data); } break; - case PCH_PIC_INT_CLEAR_HI: + case PCH_PIC_INT_CLEAR + 4: value <<=3D 32; if (s->intedge & value) { s->intirr &=3D (~value); @@ -180,10 +180,10 @@ static void loongarch_pch_pic_low_writew(void *opaque= , hwaddr addr, s->intisr &=3D (~value); } break; - case PCH_PIC_HTMSI_EN_LO: + case PCH_PIC_HTMSI_EN: s->htmsi_en =3D get_writew_val(s->htmsi_en, data, 0); break; - case PCH_PIC_HTMSI_EN_HI: + case PCH_PIC_HTMSI_EN + 4: s->htmsi_en =3D get_writew_val(s->htmsi_en, data, 1); break; default: diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index a5840ff968..f886b08c6d 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -430,7 +430,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lv= ms) VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFF= SET, sysbus_mmio_get_region(d, 1)); memory_region_add_subregion(get_system_memory(), - VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, + VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS, sysbus_mmio_get_region(d, 2)); =20 /* Connect pch_pic irqs to extioi */ diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loong= arch_pic_common.h index 43cce48978..c04471b08d 100644 --- a/include/hw/intc/loongarch_pic_common.h +++ b/include/hw/intc/loongarch_pic_common.h @@ -12,28 +12,19 @@ =20 #define PCH_PIC_INT_ID_VAL 0x7000000UL #define PCH_PIC_INT_ID_VER 0x1UL -#define PCH_PIC_INT_ID_LO 0x00 -#define PCH_PIC_INT_ID_HI 0x04 -#define PCH_PIC_INT_MASK_LO 0x20 -#define PCH_PIC_INT_MASK_HI 0x24 -#define PCH_PIC_HTMSI_EN_LO 0x40 -#define PCH_PIC_HTMSI_EN_HI 0x44 -#define PCH_PIC_INT_EDGE_LO 0x60 -#define PCH_PIC_INT_EDGE_HI 0x64 -#define PCH_PIC_INT_CLEAR_LO 0x80 -#define PCH_PIC_INT_CLEAR_HI 0x84 -#define PCH_PIC_AUTO_CTRL0_LO 0xc0 -#define PCH_PIC_AUTO_CTRL0_HI 0xc4 -#define PCH_PIC_AUTO_CTRL1_LO 0xe0 -#define PCH_PIC_AUTO_CTRL1_HI 0xe4 +#define PCH_PIC_INT_ID 0x00 +#define PCH_PIC_INT_MASK 0x20 +#define PCH_PIC_HTMSI_EN 0x40 +#define PCH_PIC_INT_EDGE 0x60 +#define PCH_PIC_INT_CLEAR 0x80 +#define PCH_PIC_AUTO_CTRL0 0xc0 +#define PCH_PIC_AUTO_CTRL1 0xe0 #define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100 #define PCH_PIC_ROUTE_ENTRY_END 0x13f #define PCH_PIC_HTMSI_VEC_OFFSET 0x200 #define PCH_PIC_HTMSI_VEC_END 0x23f -#define PCH_PIC_INT_STATUS_LO 0x3a0 -#define PCH_PIC_INT_STATUS_HI 0x3a4 -#define PCH_PIC_INT_POL_LO 0x3e0 -#define PCH_PIC_INT_POL_HI 0x3e4 +#define PCH_PIC_INT_STATUS 0x3a0 +#define PCH_PIC_INT_POL 0x3e0 =20 #define STATUS_LO_START 0 #define STATUS_HI_START 0x4 --=20 2.39.3 From nobody Wed Dec 17 15:38:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742204675547768.0329738274896; Mon, 17 Mar 2025 02:44:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tu70v-00040e-Dt; Mon, 17 Mar 2025 05:44:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tu70u-00040E-Jm for qemu-devel@nongnu.org; Mon, 17 Mar 2025 05:44:04 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tu70q-0006zV-5t for qemu-devel@nongnu.org; Mon, 17 Mar 2025 05:44:04 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxaeHc7tdnAc2ZAA--.20113S3; Mon, 17 Mar 2025 17:43:56 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBxb8fa7tdnP3tPAA--.30227S5; Mon, 17 Mar 2025 17:43:56 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 3/4] hw/intc/loongarch_pch: Rename macro PCH_PIC_xxx_OFFSET with PCH_PIC_xxx Date: Mon, 17 Mar 2025 17:43:53 +0800 Message-Id: <20250317094354.1028221-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250317094354.1028221-1-maobibo@loongson.cn> References: <20250317094354.1028221-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBxb8fa7tdnP3tPAA--.30227S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742204679637019100 Content-Type: text/plain; charset="utf-8" Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_ENTRY_OFFSET is renamed as PCH_PIC_HTMSI_VEC and PCH_PIC_ROUTE_ENTRY separately, it is easier to understand. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c | 20 ++++++++++---------- hw/loongarch/virt.c | 2 +- include/hw/intc/loongarch_pic_common.h | 4 ++-- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index 428809b927..087ab80ff8 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -251,18 +251,18 @@ static uint64_t loongarch_pch_pic_readb(void *opaque,= hwaddr addr, { LoongArchPICCommonState *s =3D LOONGARCH_PIC_COMMON(opaque); uint64_t val =3D 0; - uint32_t offset =3D (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET; + uint32_t offset =3D (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY; int64_t offset_tmp; =20 switch (offset) { - case PCH_PIC_HTMSI_VEC_OFFSET ... PCH_PIC_HTMSI_VEC_END: - offset_tmp =3D offset - PCH_PIC_HTMSI_VEC_OFFSET; + case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: + offset_tmp =3D offset - PCH_PIC_HTMSI_VEC; if (offset_tmp >=3D 0 && offset_tmp < 64) { val =3D s->htmsi_vector[offset_tmp]; } break; - case PCH_PIC_ROUTE_ENTRY_OFFSET ... PCH_PIC_ROUTE_ENTRY_END: - offset_tmp =3D offset - PCH_PIC_ROUTE_ENTRY_OFFSET; + case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: + offset_tmp =3D offset - PCH_PIC_ROUTE_ENTRY; if (offset_tmp >=3D 0 && offset_tmp < 64) { val =3D s->route_entry[offset_tmp]; } @@ -280,19 +280,19 @@ static void loongarch_pch_pic_writeb(void *opaque, hw= addr addr, { LoongArchPICCommonState *s =3D LOONGARCH_PIC_COMMON(opaque); int32_t offset_tmp; - uint32_t offset =3D (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET; + uint32_t offset =3D (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY; =20 trace_loongarch_pch_pic_writeb(size, addr, data); =20 switch (offset) { - case PCH_PIC_HTMSI_VEC_OFFSET ... PCH_PIC_HTMSI_VEC_END: - offset_tmp =3D offset - PCH_PIC_HTMSI_VEC_OFFSET; + case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: + offset_tmp =3D offset - PCH_PIC_HTMSI_VEC; if (offset_tmp >=3D 0 && offset_tmp < 64) { s->htmsi_vector[offset_tmp] =3D (uint8_t)(data & 0xff); } break; - case PCH_PIC_ROUTE_ENTRY_OFFSET ... PCH_PIC_ROUTE_ENTRY_END: - offset_tmp =3D offset - PCH_PIC_ROUTE_ENTRY_OFFSET; + case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: + offset_tmp =3D offset - PCH_PIC_ROUTE_ENTRY; if (offset_tmp >=3D 0 && offset_tmp < 64) { s->route_entry[offset_tmp] =3D (uint8_t)(data & 0xff); } diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index f886b08c6d..a18455bc89 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -427,7 +427,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lv= ms) memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, sysbus_mmio_get_region(d, 0)); memory_region_add_subregion(get_system_memory(), - VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFF= SET, + VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY, sysbus_mmio_get_region(d, 1)); memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS, diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loong= arch_pic_common.h index c04471b08d..b33bebb129 100644 --- a/include/hw/intc/loongarch_pic_common.h +++ b/include/hw/intc/loongarch_pic_common.h @@ -19,9 +19,9 @@ #define PCH_PIC_INT_CLEAR 0x80 #define PCH_PIC_AUTO_CTRL0 0xc0 #define PCH_PIC_AUTO_CTRL1 0xe0 -#define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100 +#define PCH_PIC_ROUTE_ENTRY 0x100 #define PCH_PIC_ROUTE_ENTRY_END 0x13f -#define PCH_PIC_HTMSI_VEC_OFFSET 0x200 +#define PCH_PIC_HTMSI_VEC 0x200 #define PCH_PIC_HTMSI_VEC_END 0x23f #define PCH_PIC_INT_STATUS 0x3a0 #define PCH_PIC_INT_POL 0x3e0 --=20 2.39.3 From nobody Wed Dec 17 15:38:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1742204700884951.842964982253; Mon, 17 Mar 2025 02:45:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tu70u-0003zx-Q1; Mon, 17 Mar 2025 05:44:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tu70t-0003zi-55 for qemu-devel@nongnu.org; Mon, 17 Mar 2025 05:44:03 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tu70p-0006zX-Ly for qemu-devel@nongnu.org; Mon, 17 Mar 2025 05:44:02 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxaWrd7tdnBc2ZAA--.64961S3; Mon, 17 Mar 2025 17:43:57 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMBxb8fa7tdnP3tPAA--.30227S6; Mon, 17 Mar 2025 17:43:57 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 4/4] hw/intc/loongarch_pch: Remove some duplicate macro Date: Mon, 17 Mar 2025 17:43:54 +0800 Message-Id: <20250317094354.1028221-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250317094354.1028221-1-maobibo@loongson.cn> References: <20250317094354.1028221-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBxb8fa7tdnP3tPAA--.30227S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1742204701732019000 Content-Type: text/plain; charset="utf-8" The meaning of macro definition STATUS_LO_START is simliar with PCH_PIC_INT_STATUS, only that offset is different, the same for macro POL_LO_START. Now remove these duplicated macro definitions. Signed-off-by: Bibo Mao --- hw/intc/loongarch_pch_pic.c | 20 ++++++++++---------- include/hw/intc/loongarch_pic_common.h | 5 ----- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index 087ab80ff8..ce5ef5b926 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -196,19 +196,19 @@ static uint64_t loongarch_pch_pic_high_readw(void *op= aque, hwaddr addr, { LoongArchPICCommonState *s =3D LOONGARCH_PIC_COMMON(opaque); uint64_t val =3D 0; - uint32_t offset =3D addr & 0xfff; + uint32_t offset =3D addr + PCH_PIC_INT_STATUS; =20 switch (offset) { - case STATUS_LO_START: + case PCH_PIC_INT_STATUS: val =3D (uint32_t)(s->intisr & (~s->int_mask)); break; - case STATUS_HI_START: + case PCH_PIC_INT_STATUS + 4: val =3D (s->intisr & (~s->int_mask)) >> 32; break; - case POL_LO_START: + case PCH_PIC_INT_POL: val =3D (uint32_t)s->int_polarity; break; - case POL_HI_START: + case PCH_PIC_INT_POL + 4: val =3D s->int_polarity >> 32; break; default: @@ -224,21 +224,21 @@ static void loongarch_pch_pic_high_writew(void *opaqu= e, hwaddr addr, { LoongArchPICCommonState *s =3D LOONGARCH_PIC_COMMON(opaque); uint32_t offset, data =3D (uint32_t)value; - offset =3D addr & 0xfff; + offset =3D addr + PCH_PIC_INT_STATUS; =20 trace_loongarch_pch_pic_high_writew(size, addr, data); =20 switch (offset) { - case STATUS_LO_START: + case PCH_PIC_INT_STATUS: s->intisr =3D get_writew_val(s->intisr, data, 0); break; - case STATUS_HI_START: + case PCH_PIC_INT_STATUS + 4: s->intisr =3D get_writew_val(s->intisr, data, 1); break; - case POL_LO_START: + case PCH_PIC_INT_POL: s->int_polarity =3D get_writew_val(s->int_polarity, data, 0); break; - case POL_HI_START: + case PCH_PIC_INT_POL + 4: s->int_polarity =3D get_writew_val(s->int_polarity, data, 1); break; default: diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loong= arch_pic_common.h index b33bebb129..ef6edc15bf 100644 --- a/include/hw/intc/loongarch_pic_common.h +++ b/include/hw/intc/loongarch_pic_common.h @@ -26,11 +26,6 @@ #define PCH_PIC_INT_STATUS 0x3a0 #define PCH_PIC_INT_POL 0x3e0 =20 -#define STATUS_LO_START 0 -#define STATUS_HI_START 0x4 -#define POL_LO_START 0x40 -#define POL_HI_START 0x44 - #define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common" OBJECT_DECLARE_TYPE(LoongArchPICCommonState, LoongArchPICCommonClass, LOONGARCH_PIC_COMMON) --=20 2.39.3