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From: Michael Tokarev <mjt@tls.msk.ru>
To: qemu-devel@nongnu.org
Cc: qemu-stable@nongnu.org, Max Chou <max.chou@sifive.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>,
Michael Tokarev <mjt@tls.msk.ru>
Subject: [Stable-9.2.3 23/51] target/riscv: rvv: Fix unexpected behavior of
vector reduction instructions when vl is 0
Date: Sat, 15 Mar 2025 09:17:29 +0300
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From: Max Chou <max.chou@sifive.com>
According to the Vector Reduction Operations section in the RISC-V "V"
Vector Extension spec,
"If vl=3D0, no operation is performed and the destination register is not
updated."
The vd should be updated when vl is larger than 0.
Fixes: fe5c9ab1fc ("target/riscv: vector single-width integer reduction ins=
tructions")
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250124101452.2519171-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit ffd455963f230c7dc04965609d6675da687a5a78)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a85dd1d200..3731500717 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4648,7 +4648,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, =
\
} \
s1 =3D OP(s1, (TD)s2); \
} \
- *((TD *)vd + HD(0)) =3D s1; \
+ if (vl > 0) { \
+ *((TD *)vd + HD(0)) =3D s1; \
+ } \
env->vstart =3D 0; \
/* set tail elements to 1s */ \
vext_set_elems_1s(vd, vta, esz, vlenb); \
@@ -4734,7 +4736,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, =
\
} \
s1 =3D OP(s1, (TD)s2, &env->fp_status); \
} \
- *((TD *)vd + HD(0)) =3D s1; \
+ if (vl > 0) { \
+ *((TD *)vd + HD(0)) =3D s1; \
+ } \
env->vstart =3D 0; \
/* set tail elements to 1s */ \
vext_set_elems_1s(vd, vta, esz, vlenb); \
--=20
2.39.5