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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395cb7eb93csm5437923f8f.86.2025.03.14.06.16.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 06:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741958208; x=1742563008; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UHA95dpymGqv9/OSGqYWddDTp72SBRI3UEcR8U6Ysio=; b=mkp7yCX2o5NM3C/iM0Z1Ds0Pu0fsQgfYxUvx7GtlL3pcn7+GljkJVo8C+DCkFc6lP4 g6S+Ralx0paF8ZYcdX1KIzLTzQS78pE3xKmjVhnvSj/S2kfxjE1JZN9aR5wbJ5ZVoHcY U13B70J58cvD9BvCPLXH1feNcWrrdQNLr67gFqniVocrlA3eGKHo63GH1BaepSQV0Vjo maVvBsoloqUesQtgJyQJGqUWB1fGO4PLfBbtDamfmnAOLJFgCTmFz2YCjCz8I5V+/5WE pk0aL1u9OMTxQ2RMKXhi37SdC9YBS7uIeIrdZUoto7Imp7gy2l54cQVzuqegJkcrUUNv uPPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741958208; x=1742563008; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UHA95dpymGqv9/OSGqYWddDTp72SBRI3UEcR8U6Ysio=; b=ojqGHZgp3Df8Lf07zuJhQ0zuzG62CoTdE+uK8FhGUUCVzwp8nzA7fpyIz58TgbMP3G r3Oe/nTuvuPzGGXmMjKnvBGjoRLyoPp+/9OOse72E2BN0DNUBziKY2S6t/s+QPS97k9k 0T3mIBjVeEDkU3Pcl7kqPPYDumUM/mwNkzvJx35dFERU8rAdIa4qFrLD110HSjc4Gk/B Tr9+ZZCETUYSbS5OJ3kUryZgkp3NF+N6A/57vgPazt1rF2sn8axRHvUaHRM2Oeh8+jpc 8jBHlS5Q7TTBlhqoXwoDuIEOWnatgaY0ni9WbWmvK2YaXILMIjSyEPBw23n1vzySsuks bG4A== X-Gm-Message-State: AOJu0YwH0CIu5enn3UwbF6EPl7ZXn2YJrwsbknNHhGMfmrqep9qbx00y Y80hoQPMZtn3+/1eiMPeYtO/a43KhDpxzGndt8oFI7tqQVIriDl6CBc6cGPxVyNGcKjvB0WTcGw x X-Gm-Gg: ASbGncu6GLYB9JJRDOUksyNIE7lSQiOg0WOhc+V19ctzmq9ngSIJ06PCHNdMgtu4aI9 uEXmlHVc1rTH7vcGBGjIdWFMwOA+GiOwlzYvOyoXJ1nWHPqb0GhZfCGbcDi7lhmRhwZNXNxA4QI rskjjpQTsWFh/LkJ0fksoh4C3tC5uMJTLEzPZ33i+ToPrrNTsA4j2Xp3TJbHv1oEDCeCxa8bs8l DnP9wL4dMBsn2gi/3YjTsxoEaz+uC2kbbFiYhx2SIjOSU816gVWKesrk1JwJROVzwsqmx88txpz ZcS4t6HubodItfi46gGxIQ9nEDrBUrsMaLzn+hzj5UcVgVhZ3C4= X-Google-Smtp-Source: AGHT+IFp21aCGEDMzcZNgMKWtPY8jGffIj7BvPsq338BLgYlnCyyAQxIIMw/6mg9HALrCzDPAAMAUw== X-Received: by 2002:adf:a387:0:b0:38f:3224:65e5 with SMTP id ffacd0b85a97d-3971c3ad3cbmr2630987f8f.12.1741958207778; Fri, 14 Mar 2025 06:16:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/17] target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32 Date: Fri, 14 Mar 2025 13:16:28 +0000 Message-ID: <20250314131637.371866-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org> References: <20250314131637.371866-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741958369807019000 Content-Type: text/plain; charset="utf-8" When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to be RAO/WI. Enforce the RAO/WI behaviour. Note that we handle "reset value should honour RES1 bits" in the same way that SCR_EL3 does, via a reset function. We do already have some CPU types which don't implement AArch32 above EL0, so this is technically a bug; it doesn't seem worth backporting to stable because no sensible guest code will be deliberately attempting to set the RW bit to a value corresponding to an unimplemented execution state and then checking that we did the right thing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3df7d5347cb..bb445e30cd1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5326,6 +5326,11 @@ static void do_hcr_write(CPUARMState *env, uint64_t = value, uint64_t valid_mask) /* Clear RES0 bits. */ value &=3D valid_mask; =20 + /* RW is RAO/WI if EL1 is AArch64 only */ + if (!cpu_isar_feature(aa64_aa32_el1, cpu)) { + value |=3D HCR_RW; + } + /* * These bits change the MMU setup: * HCR_VM enables stage 2 translation @@ -5383,6 +5388,12 @@ static void hcr_writelow(CPUARMState *env, const ARM= CPRegInfo *ri, do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); } =20 +static void hcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* hcr_write will set the RES1 bits on an AArch64-only CPU */ + hcr_write(env, ri, 0); +} + /* * Return the effective value of HCR_EL2, at the given security state. * Bits that are not included here: @@ -5618,6 +5629,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), .nv2_redirect_offset =3D 0x78, + .resetfn =3D hcr_reset, .writefn =3D hcr_write, .raw_writefn =3D raw_write }, { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, .type =3D ARM_CP_ALIAS | ARM_CP_IO, --=20 2.43.0