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Fri, 14 Mar 2025 03:48:36 -0700 (PDT) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH RFC] target: riscv: Add Svrsw60b59b extension support Date: Fri, 14 Mar 2025 11:48:33 +0100 Message-Id: <20250314104833.369365-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1741949353549019000 Content-Type: text/plain; charset="utf-8" The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59 for software to use. Signed-off-by: Alexandre Ghiti --- I tested it by always setting the bits 60 and 59 in Linux which booted fine. target/riscv/cpu.c | 2 ++ target/riscv/cpu_bits.h | 3 ++- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu_helper.c | 3 ++- 4 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4bd157d2..ee89cdef46 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -219,6 +219,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(svrsw60b59b, PRIV_VERSION_1_13_0, ext_svrsw60b59b), ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), @@ -1644,6 +1645,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), + MULTI_EXT_CFG_BOOL("svrsw60b59b", ext_svrsw60b59b, false), MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true), =20 MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f97c48a394..71f9e603c5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -663,7 +663,8 @@ typedef enum { #define PTE_SOFT 0x300 /* Reserved for Software */ #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory typ= es */ #define PTE_N 0x8000000000000000ULL /* NAPOT translation */ -#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */ +#define PTE_RESERVED(svrsw60b59b) \ + (svrsw60b59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) /* Reserve= d bits */ #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ =20 /* Page table PPN shift amount */ diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index b410b1e603..f6e4b0068a 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -89,6 +89,7 @@ struct RISCVCPUConfig { bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; + bool ext_svrsw60b59b; bool ext_svvptc; bool ext_svukte; bool ext_zdinx; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1dfc4ecbf..6546cea403 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1156,6 +1156,7 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, bool svade =3D riscv_cpu_cfg(env)->ext_svade; bool svadu =3D riscv_cpu_cfg(env)->ext_svadu; bool adue =3D svadu ? env->menvcfg & MENVCFG_ADUE : !svade; + bool svrsw60b59b =3D riscv_cpu_cfg(env)->ext_svrsw60b59b; =20 if (first_stage && two_stage && env->virt_enabled) { pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); @@ -1225,7 +1226,7 @@ restart: if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { ppn =3D pte >> PTE_PPN_SHIFT; } else { - if (pte & PTE_RESERVED) { + if (pte & PTE_RESERVED(svrsw60b59b)) { return TRANSLATE_FAIL; } =20 --=20 2.39.2