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Thu, 13 Mar 2025 12:30:17 -0700 (PDT) From: =?UTF-8?q?Lo=C3=AFc=20Lefort?= To: qemu-devel@nongnu.org Cc: Liu Zhiwei , Weiwei Li , qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza , =?UTF-8?q?Lo=C3=AFc=20Lefort?= Subject: [PATCH v2 4/5] target/riscv: pmp: exit csr writes early if value was not changed Date: Thu, 13 Mar 2025 20:30:10 +0100 Message-ID: <20250313193011.720075-5-loic@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250313193011.720075-1-loic@rivosinc.com> References: <20250313193011.720075-1-loic@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=loic@rivosinc.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1741894395341019100 Signed-off-by: Lo=C3=AFc Lefort Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei --- target/riscv/pmp.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index c5f6cdaccb..845915e0c8 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -141,6 +141,11 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env,= uint32_t pmp_index) static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t = val) { if (pmp_index < MAX_RISCV_PMPS) { + if (env->pmp_state.pmp[pmp_index].cfg_reg =3D=3D val) { + /* no change */ + return false; + } + if (pmp_is_readonly(env, pmp_index)) { qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - read only\n"); @@ -528,6 +533,11 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t ad= dr_index, bool is_next_cfg_tor =3D false; =20 if (addr_index < MAX_RISCV_PMPS) { + if (env->pmp_state.pmp[addr_index].addr_reg =3D=3D val) { + /* no change */ + return; + } + /* * In TOR mode, need to check the lock bit of the next pmp * (if there is a next). @@ -544,14 +554,12 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t a= ddr_index, } =20 if (!pmp_is_readonly(env, addr_index)) { - if (env->pmp_state.pmp[addr_index].addr_reg !=3D val) { - env->pmp_state.pmp[addr_index].addr_reg =3D val; - pmp_update_rule_addr(env, addr_index); - if (is_next_cfg_tor) { - pmp_update_rule_addr(env, addr_index + 1); - } - tlb_flush(env_cpu(env)); + env->pmp_state.pmp[addr_index].addr_reg =3D val; + pmp_update_rule_addr(env, addr_index); + if (is_next_cfg_tor) { + pmp_update_rule_addr(env, addr_index + 1); } + tlb_flush(env_cpu(env)); } else { qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpaddr write - read only\n"); --=20 2.47.2