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To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>, Peter Maydell
<peter.maydell@linaro.org>, Troy Lee <leetroy@gmail.com>, Jamin Lin
<jamin_lin@aspeedtech.com>, Andrew Jeffery <andrew@codeconstruct.com.au>,
Joel Stanley <joel@jms.id.au>, "open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
CC: <troy_lee@aspeedtech.com>, <yunlin.tang@aspeedtech.com>
Subject: [PATCH 06/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
Date: Thu, 13 Mar 2025 13:40:10 +0800
Message-ID: <20250313054020.2583556-7-steven_lee@aspeedtech.com>
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Reply-to: Steven Lee <steven_lee@aspeedtech.com>
From: Steven Lee via <qemu-devel@nongnu.org>
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The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:
- Defined IRQ maps for AST27x0 A1 SSP SoC
- Implemented initialization functions
The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt controller.
Difference from AST2700:
- AST2700
- Support GICINT128 to GICINT136 in INTC
- The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-ssp
- Support SSPINT128 to SSPINT136 in INTC
- The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ic5121dd78c5dacf1ec4b4e791cc7bf476a8b608f
---
hw/arm/aspeed_ast27x0-ssp.c | 91 +++++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 88f27b9459..5553190a62 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -60,6 +60,24 @@ static const int aspeed_soc_ast27x0a0ssp_irqmap[] =3D {
[ASPEED_DEV_TIMER1] =3D 16,
};
=20
+static const int aspeed_soc_ast27x0a1ssp_irqmap[] =3D {
+ [ASPEED_DEV_SCU] =3D 12,
+ [ASPEED_DEV_UART0] =3D 164,
+ [ASPEED_DEV_UART1] =3D 164,
+ [ASPEED_DEV_UART2] =3D 164,
+ [ASPEED_DEV_UART3] =3D 164,
+ [ASPEED_DEV_UART4] =3D 8,
+ [ASPEED_DEV_UART5] =3D 164,
+ [ASPEED_DEV_UART6] =3D 164,
+ [ASPEED_DEV_UART7] =3D 164,
+ [ASPEED_DEV_UART8] =3D 164,
+ [ASPEED_DEV_UART9] =3D 164,
+ [ASPEED_DEV_UART10] =3D 164,
+ [ASPEED_DEV_UART11] =3D 164,
+ [ASPEED_DEV_UART12] =3D 164,
+ [ASPEED_DEV_TIMER1] =3D 16,
+};
+
/* SSPINT 164 */
static const int ast2700_ssp132_ssp164_intcmap[] =3D {
[ASPEED_DEV_UART0] =3D 7,
@@ -167,6 +185,46 @@ static void aspeed_soc_ast27x0a0ssp_init(Object *obj)
TYPE_UNIMPLEMENTED_DEVICE);
}
=20
+static void aspeed_soc_ast27x0a1ssp_init(Object *obj)
+{
+ Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(obj);
+ AspeedSoCState *s =3D ASPEED_SOC(obj);
+ AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s);
+ char socname[8];
+ char typename[64];
+ int i;
+
+ if (sscanf(object_get_typename(obj), "%7s", socname) !=3D 1) {
+ g_assert_not_reached();
+ }
+
+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
+
+ s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+
+ snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
+ object_initialize_child(obj, "scu", &s->scu, typename);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
+
+ for (i =3D 0; i < sc->uarts_num; i++) {
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M=
M);
+ }
+
+ object_initialize_child(obj, "intc0", &a->intc[0],
+ TYPE_ASPEED_2700SSP_INTC);
+ object_initialize_child(obj, "intc1", &a->intc[1],
+ TYPE_ASPEED_2700SSP_INTCIO);
+
+ object_initialize_child(obj, "timerctrl", &s->timerctrl,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc0", &a->ipc[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc1", &a->ipc[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "scuio", &a->scuio,
+ TYPE_UNIMPLEMENTED_DEVICE);
+}
+
static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **er=
rp)
{
Aspeed27x0SSPSoCState *a =3D ASPEED27X0SSP_SOC(dev_soc);
@@ -292,6 +350,34 @@ static void aspeed_soc_ast27x0a0ssp_class_init(ObjectC=
lass *klass, void *data)
sc->get_irq =3D aspeed_soc_ast27x0ssp_get_irq;
}
=20
+static void aspeed_soc_ast27x0a1ssp_class_init(ObjectClass *klass, void *d=
ata)
+{
+ static const char * const valid_cpu_types[] =3D {
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
+ NULL
+ };
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+ AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable =3D false;
+ dc->realize =3D aspeed_soc_ast27x0ssp_realize;
+
+ sc->valid_cpu_types =3D valid_cpu_types;
+ sc->silicon_rev =3D AST2700_A1_SILICON_REV;
+ sc->sram_size =3D AST2700_SSP_RAM_SIZE;
+ sc->spis_num =3D 0;
+ sc->ehcis_num =3D 0;
+ sc->wdts_num =3D 0;
+ sc->macs_num =3D 0;
+ sc->uarts_num =3D 13;
+ sc->uarts_base =3D ASPEED_DEV_UART0;
+ sc->irqmap =3D aspeed_soc_ast27x0a1ssp_irqmap;
+ sc->memmap =3D aspeed_soc_ast27x0ssp_memmap;
+ sc->num_cpus =3D 1;
+ sc->get_irq =3D aspeed_soc_ast27x0ssp_get_irq;
+}
+
static const TypeInfo aspeed_soc_ast27x0ssp_types[] =3D {
{
.name =3D TYPE_ASPEED27X0SSP_SOC,
@@ -303,6 +389,11 @@ static const TypeInfo aspeed_soc_ast27x0ssp_types[] =
=3D {
.parent =3D TYPE_ASPEED27X0SSP_SOC,
.instance_init =3D aspeed_soc_ast27x0a0ssp_init,
.class_init =3D aspeed_soc_ast27x0a0ssp_class_init,
+ }, {
+ .name =3D "ast2700ssp-a1",
+ .parent =3D TYPE_ASPEED27X0SSP_SOC,
+ .instance_init =3D aspeed_soc_ast27x0a1ssp_init,
+ .class_init =3D aspeed_soc_ast27x0a1ssp_class_init,
},
};
=20
--=20
2.34.1