From nobody Fri Apr 4 06:19:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741772528; cv=none; d=zohomail.com; s=zohoarc; b=nBL95YuBquJXZ7d2QJ8w5gQXpq/ZJt+xYcbwKw8MW0dLMy81LMEVO5pVv+FzgtlcfHjHNy1sEOFR5KuTTv+My39aJ64t8SyO8wMKN6OdY3elvU/kZqmSaVO0hdDcDxK1CJyBU4kCvzCdtLCh1PwWz30FAbTVUPLSrBbhc8Y6x/g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741772528; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=DqlBajiJVLlv6UxSpSuNvT0iMRR+rphTDyB0MHVMGlU=; b=TgrAlBOCzOGHbsJg0wvI/Fvsyre1MDvWYmlJU1wlk1Yea75nEnwDuqciw3DAVMoErZ8ENFtuFoh7BGtKu8zVLP83sSGc6nEpEJcJ7yiej5y8Hlj0QIbHgORi/6VCnx0ZQFtFGCzR0MzG7zjWb1lVIkYms9Nr3h2pB5hx2+DrpSE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741772527992349.3833671890163; Wed, 12 Mar 2025 02:42:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tsIYn-0003cl-3j; Wed, 12 Mar 2025 05:39:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tsIYc-0003YU-Mr; Wed, 12 Mar 2025 05:39:22 -0400 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tsIYX-0000mI-3O; Wed, 12 Mar 2025 05:39:22 -0400 Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 52C9bBOf069431 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 12 Mar 2025 17:37:11 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from atcpcw16.andestech.com (10.0.1.106) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server (TLS) id 14.3.498.0; Wed, 12 Mar 2025 17:38:42 +0800 To: CC: , , , , , , , , , , , Ethan Chen Subject: [PATCH v11 3/8] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size Date: Wed, 12 Mar 2025 17:37:27 +0800 Message-ID: <20250312093735.1517740-4-ethan84@andestech.com> X-Mailer: git-send-email 2.42.0.345.gaab89be2eb.dirty In-Reply-To: <20250312093735.1517740-1-ethan84@andestech.com> References: <20250312093735.1517740-1-ethan84@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.1.106] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 52C9bBOf069431 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741772529791019000 Content-Type: text/plain; charset="utf-8" If the IOMMU granularity is smaller than the TARGET_PAGE size, there may be multiple entries within the same page. To obtain the correct result, pass the original address to the IOMMU. Similar to the RISC-V PMP solution, the TLB_INVALID_MASK will be set when there are multiple entries in the same page, ensuring that the IOMMU is checked on every access. Signed-off-by: Ethan Chen Acked-by: Alistair Francis --- accel/tcg/cputlb.c | 20 ++++++++++++++++---- system/physmem.c | 4 ++++ 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 83d689f9a6..73551b649d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1043,8 +1043,23 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, =20 prot =3D full->prot; asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); - section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, + section =3D address_space_translate_for_iotlb(cpu, asidx, full->phys_a= ddr, &xlat, &sz, full->attrs, &= prot); + /* Update page size */ + full->lg_page_size =3D ctz64(sz); + if (full->lg_page_size > TARGET_PAGE_BITS) { + full->lg_page_size =3D TARGET_PAGE_BITS; + } else { + sz =3D TARGET_PAGE_SIZE; + } + + is_ram =3D memory_region_is_ram(section->mr); + is_romd =3D memory_region_is_romd(section->mr); + /* If the translated mr is ram/rom, make xlat align the TARGET_PAGE */ + if (is_ram || is_romd) { + xlat &=3D TARGET_PAGE_MASK; + } + assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx @@ -1057,9 +1072,6 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, read_flags |=3D TLB_INVALID_MASK; } =20 - is_ram =3D memory_region_is_ram(section->mr); - is_romd =3D memory_region_is_romd(section->mr); - if (is_ram || is_romd) { /* RAM and ROMD both have associated host memory. */ addend =3D (uintptr_t)memory_region_get_ram_ptr(section->mr) + xla= t; diff --git a/system/physmem.c b/system/physmem.c index e97de3ef65..c5059cb006 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -708,6 +708,10 @@ address_space_translate_for_iotlb(CPUState *cpu, int a= sidx, hwaddr orig_addr, iotlb =3D imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx); addr =3D ((iotlb.translated_addr & ~iotlb.addr_mask) | (addr & iotlb.addr_mask)); + /* Update size */ + if (iotlb.addr_mask !=3D -1 && *plen > iotlb.addr_mask + 1) { + *plen =3D iotlb.addr_mask + 1; + } /* Update the caller's prot bits to remove permissions the IOMMU * is giving us a failure response for. If we get down to no * permissions left at all we can give up now. --=20 2.34.1