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charset="utf-8" The AMD I/O Virtualization Technology (IOMMU) Specification (see Table 8: V, TV, and GV Fields in Device Table Entry), specifies that a DTE with V=3D0, TV=3D1 does not contain a valid address translation information. If a requ= est requires a table walk, the walk is terminated when this condition is encountered. Do not assume that addresses for a device with DTE[TV]=3D0 are passed throu= gh (i.e. not remapped) and instead terminate the page table walk early. Cc: qemu-stable@nongnu.org Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU") Signed-off-by: Alejandro Jimenez Reviewed-by: Vasant Hegde --- hw/i386/amd_iommu.c | 88 +++++++++++++++++++++++++-------------------- 1 file changed, 49 insertions(+), 39 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index cf00450ebe..31d5522a62 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -932,51 +932,61 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, ui= nt64_t *dte, uint64_t pte =3D dte[0], pte_addr, page_mask; =20 /* make sure the DTE has TV =3D 1 */ - if (pte & AMDVI_DEV_TRANSLATION_VALID) { - level =3D get_pte_translation_mode(pte); - if (level >=3D 7) { - trace_amdvi_mode_invalid(level, addr); + if (!(pte & AMDVI_DEV_TRANSLATION_VALID)) { + /* + * A DTE with V=3D1, TV=3D0 does not have a valid Page Table Root = Pointer. + * An IOMMU processing a request that requires a table walk termin= ates + * the walk when it encounters this condition. Do the same and ret= urn + * instead of assuming that the address is forwarded without trans= lation + * i.e. the passthrough case, as it is done for the case where DTE= [V]=3D0. + */ + return; + } + + level =3D get_pte_translation_mode(pte); + if (level >=3D 7) { + trace_amdvi_mode_invalid(level, addr); + return; + } + if (level =3D=3D 0) { + goto no_remap; + } + + /* we are at the leaf page table or page table encodes a huge page */ + do { + pte_perms =3D amdvi_get_perms(pte); + present =3D pte & 1; + if (!present || perms !=3D (perms & pte_perms)) { + amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); + trace_amdvi_page_fault(addr); return; } - if (level =3D=3D 0) { - goto no_remap; - } =20 - /* we are at the leaf page table or page table encodes a huge page= */ - do { - pte_perms =3D amdvi_get_perms(pte); - present =3D pte & 1; - if (!present || perms !=3D (perms & pte_perms)) { - amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); - trace_amdvi_page_fault(addr); - return; - } - - /* go to the next lower level */ - pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; - /* add offset and load pte */ - pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; - pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->dev= fn); - if (!pte) { - return; - } - oldlevel =3D level; - level =3D get_pte_translation_mode(pte); - } while (level > 0 && level < 7); - - if (level =3D=3D 0x7) { - page_mask =3D pte_override_page_mask(pte); - } else { - page_mask =3D pte_get_page_mask(oldlevel); + /* go to the next lower level */ + pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; + /* add offset and load pte */ + pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; + pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); + if (!pte) { + return; } + oldlevel =3D level; + level =3D get_pte_translation_mode(pte); + } while (level > 0 && level < 7); =20 - /* get access permissions from pte */ - ret->iova =3D addr & page_mask; - ret->translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mas= k; - ret->addr_mask =3D ~page_mask; - ret->perm =3D amdvi_get_perms(pte); - return; + if (level =3D=3D 0x7) { + page_mask =3D pte_override_page_mask(pte); + } else { + page_mask =3D pte_get_page_mask(oldlevel); } + + /* get access permissions from pte */ + ret->iova =3D addr & page_mask; + ret->translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mask; + ret->addr_mask =3D ~page_mask; + ret->perm =3D amdvi_get_perms(pte); + return; + no_remap: ret->iova =3D addr & AMDVI_PAGE_MASK_4K; ret->translated_addr =3D addr & AMDVI_PAGE_MASK_4K; --=20 2.43.5