From nobody Mon Apr 7 04:41:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702429; cv=none; d=zohomail.com; s=zohoarc; b=cbv6urh5ep4YPtdEI9TnhIMlkhCb2htyl1VOTYDc/K4plAkHjgKmj50t0PU5DWKsLSnRN90kj8cKf6+o4/iGN7m7chTZWlqwZeIWh0RXsbDAplc4ZI2mYxWE4/79jaUz/9/40nIPRr+eKHzz6n49nWqZ6XuB7rUfmc9vrIFqdS4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741702429; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=CIbThC2YFHd9oyntcKCOn6UL5VZsKKYkuHaWW5+wTz0=; b=mwIr5elRgenvPxC0IajOmC8ARi/YY208CLxf7lapE2LS6ZfnJPYJz8li4O3O3q2P013nUsDCN2H3rQLXElrkNsE7jO013l5n2iJ7A7KXxWUf8SAYgXpWDkbtFU3Ymp7FLlc+CIwZySFzhPNOSY6lNSKJKvdX5jp35JfC2XpjDlE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741702429030433.5222046808051; Tue, 11 Mar 2025 07:13:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ts0MV-0004F5-Qx; Tue, 11 Mar 2025 10:13:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0MO-0003zA-Ga; Tue, 11 Mar 2025 10:13:32 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0ML-00074T-4X; Tue, 11 Mar 2025 10:13:32 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwdR23DZz6D9Ry; Tue, 11 Mar 2025 22:10:19 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 2783C14034E; Tue, 11 Mar 2025 22:13:26 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:13:18 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 10/20] hw/arm/smmuv3-accel: Support nested STE install/uninstall support Date: Tue, 11 Mar 2025 14:10:35 +0000 Message-ID: <20250311141045.66620-11-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702430377019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Allocates a s1 HWPT for the Guest s1 stage and attaches that to the dev. This will be invoked in a subsequent patch when Guest issues SMMU_CMD_CFGI_STE. While at it, we are also exporting both smmu_find_ste() and smmuv3_flush_config() from smmuv3.c for use here. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 111 ++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-internal.h | 13 ++++ hw/arm/smmuv3.c | 5 +- hw/arm/trace-events | 1 + include/hw/arm/smmuv3-accel.h | 6 ++ 5 files changed, 133 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 1c696649d5..d3a5cf9551 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -13,6 +13,8 @@ #include "hw/arm/smmuv3-accel.h" #include "hw/pci/pci_bridge.h" =20 +#include "smmuv3-internal.h" + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *s, SMMUPciBus *s= bus, PCIBus *bus, int devfn) { @@ -32,6 +34,115 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *s, SMMUPciBus *sbus, return accel_dev; } =20 +static void +smmuv3_accel_dev_uninstall_nested_ste(SMMUv3AccelDevice *accel_dev, bool a= bort) +{ + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + SMMUS1Hwpt *s1_hwpt =3D accel_dev->s1_hwpt; + uint32_t hwpt_id; + + if (!s1_hwpt || !accel_dev->viommu) { + return; + } + + if (abort) { + hwpt_id =3D accel_dev->viommu->abort_hwpt_id; + } else { + hwpt_id =3D accel_dev->viommu->bypass_hwpt_id; + } + + host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, &error_abort); + iommufd_backend_free_id(s1_hwpt->iommufd, s1_hwpt->hwpt_id); + accel_dev->s1_hwpt =3D NULL; + g_free(s1_hwpt); +} + +static int +smmuv3_accel_dev_install_nested_ste(SMMUv3AccelDevice *accel_dev, + uint32_t data_type, uint32_t data_len, + void *data) +{ + SMMUViommu *viommu =3D accel_dev->viommu; + SMMUS1Hwpt *s1_hwpt =3D accel_dev->s1_hwpt; + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + + if (!idev || !viommu) { + return -ENOENT; + } + + if (s1_hwpt) { + smmuv3_accel_dev_uninstall_nested_ste(accel_dev, false); + } + + s1_hwpt =3D g_new0(SMMUS1Hwpt, 1); + if (!s1_hwpt) { + return -ENOMEM; + } + + s1_hwpt->iommufd =3D idev->iommufd; + iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, data_type, data_= len, + data, &s1_hwpt->hwpt_id, &error_abort); + host_iommu_device_iommufd_attach_hwpt(idev, s1_hwpt->hwpt_id, &error_a= bort); + accel_dev->s1_hwpt =3D s1_hwpt; + return 0; +} + +void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int sid) +{ + SMMUv3AccelDevice *accel_dev; + SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, + .inval_ste_allowed =3D true}; + struct iommu_hwpt_arm_smmuv3 nested_data =3D {}; + SMMUv3State *s =3D sdev->smmu; + SMMUState *bs =3D &s->smmu_state; + uint32_t config; + STE ste; + int ret; + + if (!bs->accel) { + return; + } + + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!accel_dev->viommu) { + return; + } + + ret =3D smmu_find_ste(sdev->smmu, sid, &ste, &event); + if (ret) { + /* + * For a 2-level Stream Table, the level-2 table might not be ready + * until the device gets inserted to the stream table. Ignore this. + */ + return; + } + + config =3D STE_CONFIG(&ste); + if (!STE_VALID(&ste) || !STE_CFG_S1_ENABLED(config)) { + smmuv3_accel_dev_uninstall_nested_ste(accel_dev, STE_CFG_ABORT(con= fig)); + smmuv3_flush_config(sdev); + return; + } + + nested_data.ste[0] =3D (uint64_t)ste.word[0] | (uint64_t)ste.word[1] <= < 32; + nested_data.ste[1] =3D (uint64_t)ste.word[2] | (uint64_t)ste.word[3] <= < 32; + /* V | CONFIG | S1FMT | S1CTXPTR | S1CDMAX */ + nested_data.ste[0] &=3D 0xf80fffffffffffffULL; + /* S1DSS | S1CIR | S1COR | S1CSH | S1STALLD | EATS */ + nested_data.ste[1] &=3D 0x380000ffULL; + ret =3D smmuv3_accel_dev_install_nested_ste(accel_dev, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(nested_data), + &nested_data); + if (ret) { + error_report("Unable to install nested STE=3D%16LX:%16LX, ret=3D%d= ", + nested_data.ste[1], nested_data.ste[0], ret); + } + trace_smmuv3_accel_install_nested_ste(sid, nested_data.ste[1], + nested_data.ste[0]); +} + static bool smmuv3_accel_dev_attach_viommu(SMMUv3AccelDevice *accel_dev, HostIOMMUDeviceIOMMUFD *idev, Error **errp) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index b6b7399347..46c8bcae14 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -24,6 +24,8 @@ #include "hw/registerfields.h" #include "hw/arm/smmu-common.h" =20 +#include CONFIG_DEVICES + typedef enum SMMUTranslationStatus { SMMU_TRANS_DISABLE, SMMU_TRANS_ABORT, @@ -547,6 +549,17 @@ typedef struct CD { uint32_t word[16]; } CD; =20 +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, + SMMUEventInfo *event); +void smmuv3_flush_config(SMMUDevice *sdev); + +#if defined(CONFIG_ARM_SMMUV3_ACCEL) && defined(CONFIG_IOMMUFD) +void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int sid); +#else +static inline void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int s= id) +{ +} +#endif /* STE fields */ =20 #define STE_VALID(x) extract32((x)->word[0], 0, 1) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b49a59b64c..ea63731d61 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -628,8 +628,7 @@ bad_ste: * Supports linear and 2-level stream table * Return 0 on success, -EINVAL otherwise */ -static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, - SMMUEventInfo *event) +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *e= vent) { dma_addr_t addr, strtab_base; uint32_t log2size; @@ -898,7 +897,7 @@ static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev= , SMMUEventInfo *event) return cfg; } =20 -static void smmuv3_flush_config(SMMUDevice *sdev) +void smmuv3_flush_config(SMMUDevice *sdev) { SMMUv3State *s =3D sdev->smmu; SMMUState *bc =3D &s->smmu_state; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 17960794bf..cd2eac31c2 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -61,6 +61,7 @@ smmu_reset_exit(void) "" #smmuv3-accel.c smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x" +smmuv3_accel_install_nested_ste(uint32_t sid, uint64_t ste_1, uint64_t ste= _0) "sid=3D%d ste=3D%"PRIx64":%"PRIx64 =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h index aca6838dca..d6b0b1ca30 100644 --- a/include/hw/arm/smmuv3-accel.h +++ b/include/hw/arm/smmuv3-accel.h @@ -35,9 +35,15 @@ typedef struct SMMUViommu { QLIST_ENTRY(SMMUViommu) next; } SMMUViommu; =20 +typedef struct SMMUS1Hwpt { + IOMMUFDBackend *iommufd; + uint32_t hwpt_id; +} SMMUS1Hwpt; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; HostIOMMUDeviceIOMMUFD *idev; + SMMUS1Hwpt *s1_hwpt; SMMUViommu *viommu; QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; --=20 2.34.1