From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702338; cv=none; d=zohomail.com; s=zohoarc; b=cNHw/dMY6DwiECPS42zqNYFR/iaFHYpbmSS0VSVUKTeRuAzIstM2feZqAzqKwmlwdPwe+CXhpf8PljCCphMiAszMosU/DktZufz2K96EHHGOv6yxbvPVXl3lXzJiHC+OXSnLaa0ahamsz0TXGdzXOR34f0/sE5APUPPOkDEEepA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741702338; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=CawNJVP/7ZlOL296MedQQS1yoXCFM/S857FlCi6csVs=; b=cRaViX5WtziLIhCstoKUmCnjKrque4cxCyYrInMi5I+cPnCZJ4MWlIu04uvkSm/MaS+yKGgvtGrAwjAdykEb4JuPz06v4BoBeQVW2kZc9TVPe2JYH1cpK0GUGXr4z88r9nb79lHvlfyBJrIS+g8Oc5qARhKXKlv1zVTVA7BiSgo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741702338175768.2421040418812; Tue, 11 Mar 2025 07:12:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ts0Kv-0008R8-RL; Tue, 11 Mar 2025 10:12:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Kt-0008M9-Qu; Tue, 11 Mar 2025 10:12:00 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Ks-0006of-0S; Tue, 11 Mar 2025 10:11:59 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwcM4DR0z6D8Yh; Tue, 11 Mar 2025 22:09:23 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 30EE014034E; Tue, 11 Mar 2025 22:11:56 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:11:48 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 01/20] backends/iommufd: Introduce iommufd_backend_alloc_viommu Date: Tue, 11 Mar 2025 14:10:26 +0000 Message-ID: <20250311141045.66620-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702340595019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a helper to allocate a viommu object. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- backends/iommufd.c | 25 +++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 4 ++++ 3 files changed, 30 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 3c23caef96..3fac08c96e 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -341,6 +341,31 @@ int iommufd_backend_invalidate_cache(IOMMUFDBackend *b= e, uint32_t hwpt_id, return ret; } =20 +bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_type, uint32_t hwpt_id, + uint32_t *out_viommu_id, Error **errp) +{ + int ret, fd =3D be->fd; + struct iommu_viommu_alloc alloc_viommu =3D { + .size =3D sizeof(alloc_viommu), + .type =3D viommu_type, + .dev_id =3D dev_id, + .hwpt_id =3D hwpt_id, + }; + + ret =3D ioctl(fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu); + + trace_iommufd_backend_alloc_viommu(fd, viommu_type, dev_id, hwpt_id, + alloc_viommu.out_viommu_id, ret); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_VIOMMU_ALLOC failed"); + return false; + } + + *out_viommu_id =3D alloc_viommu.out_viommu_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 5a23db6c8a..a835827540 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -19,3 +19,4 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret= ) " iommufd=3D%d id=3D%d (% iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t page_size, int ret) " iommufd=3D%d hwpt=3D%u i= ova=3D0x%"PRIx64" size=3D0x%"PRIx64" page_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t hwpt_id, uint32_t d= ata_type, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64= _t data_ptr, int ret) " iommufd=3D%d hwpt_id=3D%u data_type=3D%u entry_len= =3D%u entry_num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" +iommufd_backend_alloc_viommu(int iommufd, uint32_t type, uint32_t dev_id, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index b93421ac7c..7e5507f2db 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -55,6 +55,10 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint= 32_t dev_id, uint32_t data_type, uint32_t data_len, void *data_ptr, uint32_t *out_hwpt, Error **errp); +bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_type, uint32_t hwpt_id, + uint32_t *out_hwpt, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702375; cv=none; d=zohomail.com; s=zohoarc; b=K2dJl5FG34bN+Q7E45vLJS91OJG20NsxAzB+3KLBaSSz827cJEKt55Km+Gaz/DVmIUXiANF6PLZXbB8LxzRaQTVRNg2LDcVyXHAD8JCEH+ZaK3BDh7ktcWoEk4XDyiNxVEYUeJks5l4j/N55oCI+/UcZeXIRW7n7vndtPCNzbCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Tue, 11 Mar 2025 10:12:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0L5-00008y-CU; Tue, 11 Mar 2025 10:12:11 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0L3-0006qs-Jk; Tue, 11 Mar 2025 10:12:11 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwcb03GGz6D8cc; Tue, 11 Mar 2025 22:09:35 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 951F1140D26; Tue, 11 Mar 2025 22:12:07 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:12:00 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 02/20] backends/iommufd: Introduce iommufd_vdev_alloc Date: Tue, 11 Mar 2025 14:10:27 +0000 Message-ID: <20250311141045.66620-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702377183019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a helper to allocate an iommufd device's virtual device (in the user space) per a viommu instance. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- backends/iommufd.c | 26 ++++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 4 ++++ 3 files changed, 31 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 3fac08c96e..3511dd32ab 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -366,6 +366,32 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, = uint32_t dev_id, return true; } =20 +bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_id, uint64_t virt_id, + uint32_t *out_vdev_id, Error **errp) +{ + int ret, fd =3D be->fd; + struct iommu_vdevice_alloc alloc_vdev =3D { + .size =3D sizeof(alloc_vdev), + .viommu_id =3D viommu_id, + .dev_id =3D dev_id, + .virt_id =3D virt_id, + }; + + ret =3D ioctl(fd, IOMMU_VDEVICE_ALLOC, &alloc_vdev); + + trace_iommufd_backend_alloc_vdev(fd, dev_id, viommu_id, virt_id, + alloc_vdev.out_vdevice_id, ret); + + if (ret) { + error_setg_errno(errp, errno, "IOMMU_VDEVICE_ALLOC failed"); + return false; + } + + *out_vdev_id =3D alloc_vdev.out_vdevice_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index a835827540..86c8f89e8a 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -20,3 +20,4 @@ iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, = bool start, int ret) " iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t page_size, int ret) " iommufd=3D%d hwpt=3D%u i= ova=3D0x%"PRIx64" size=3D0x%"PRIx64" page_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t hwpt_id, uint32_t d= ata_type, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64= _t data_ptr, int ret) " iommufd=3D%d hwpt_id=3D%u data_type=3D%u entry_len= =3D%u entry_num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" iommufd_backend_alloc_viommu(int iommufd, uint32_t type, uint32_t dev_id, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" +iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 7e5507f2db..53920bae5b 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -59,6 +59,10 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, ui= nt32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, uint32_t *out_hwpt, Error **errp); =20 +bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_id, uint64_t virt_id, + uint32_t *out_vdev_id, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702427; cv=none; d=zohomail.com; s=zohoarc; b=RBSkxSe96koL1LkoCgRIVgFYQ4y8UwqOvAylQNqNPoiYvtsD/Z9W2T47LtZLkGv80EteSfcq4IJyUIcDfM5eKfvdpL5V/bTunUvvvALNtftTFJ+GRJS1W+B0tgBfRKbq7bgylbOiubbQrIE+E0XPBcS6+Nm+xr5p4tfjV39viso= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Tue, 11 Mar 2025 10:12:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0LE-0000Ul-J4; Tue, 11 Mar 2025 10:12:20 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0LC-0006sl-JW; Tue, 11 Mar 2025 10:12:20 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwc55ggtz6D9b5; Tue, 11 Mar 2025 22:09:09 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id A266D140B63; Tue, 11 Mar 2025 22:12:16 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:12:09 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 03/20] hw/arm/smmuv3-accel: Add initial infrastructure for smmuv3-accel device Date: Tue, 11 Mar 2025 14:10:28 +0000 Message-ID: <20250311141045.66620-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702429992019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Based on SMMUv3 as a parent device, add a user-creatable smmuv3-accel device. In order to support vfio-pci dev assignment with a Guest SMMUv3, the physical SMMUv3 has to be configured in nested(S1+s2) mode, with Guest owning the S1 page tables. Subsequent patches will add support for smmuv3-accel to provide this. Signed-off-by: Shameer Kolothum --- hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 1 + hw/arm/smmu-common.c | 1 + hw/arm/smmuv3-accel.c | 51 +++++++++++++++++++++++++++++++++++ include/hw/arm/smmu-common.h | 3 +++ include/hw/arm/smmuv3-accel.h | 31 +++++++++++++++++++++ 6 files changed, 92 insertions(+) create mode 100644 hw/arm/smmuv3-accel.c create mode 100644 include/hw/arm/smmuv3-accel.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 504841ccab..f889842dd8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -14,6 +14,7 @@ config ARM_VIRT select ARM_GIC select ACPI select ARM_SMMUV3 + select ARM_SMMUV3_ACCEL select GPIO_KEY select DEVICE_TREE select FW_CFG_DMA @@ -596,6 +597,10 @@ config FSL_IMX7 config ARM_SMMUV3 bool =20 +config ARM_SMMUV3_ACCEL + select ARM_SMMUV3 + bool + config FSL_IMX6UL bool default y diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 465c757f97..e8593363b0 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -55,6 +55,7 @@ arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c'= )) arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-= sabre.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c= ')) arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcim= x6ul-evk.c')) arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 8c1b407b82..f5caf1665c 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -943,6 +943,7 @@ static const Property smmu_dev_properties[] =3D { DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0), DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, TYPE_PCI_BUS, PCIBus *), + DEFINE_PROP_BOOL("accel", SMMUState, accel, false), }; =20 static void smmu_base_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c new file mode 100644 index 0000000000..c327661636 --- /dev/null +++ b/hw/arm/smmuv3-accel.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3-accel.h" + +static void smmu_accel_realize(DeviceState *d, Error **errp) +{ + SMMUv3AccelState *s_accel =3D ARM_SMMUV3_ACCEL(d); + SMMUv3AccelClass *c =3D ARM_SMMUV3_ACCEL_GET_CLASS(s_accel); + SysBusDevice *dev =3D SYS_BUS_DEVICE(d); + Error *local_err =3D NULL; + + object_property_set_bool(OBJECT(dev), "accel", true, &error_abort); + c->parent_realize(d, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } +} + +static void smmuv3_accel_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + SMMUv3AccelClass *c =3D ARM_SMMUV3_ACCEL_CLASS(klass); + + device_class_set_parent_realize(dc, smmu_accel_realize, + &c->parent_realize); + dc->hotpluggable =3D false; +} + +static const TypeInfo smmuv3_accel_type_info =3D { + .name =3D TYPE_ARM_SMMUV3_ACCEL, + .parent =3D TYPE_ARM_SMMUV3, + .instance_size =3D sizeof(SMMUv3AccelState), + .class_size =3D sizeof(SMMUv3AccelClass), + .class_init =3D smmuv3_accel_class_init, +}; + +static void smmuv3_accel_register_types(void) +{ + type_register_static(&smmuv3_accel_type_info); +} + +type_init(smmuv3_accel_register_types) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index d1a4a64551..b5c63cfd5d 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -157,6 +157,9 @@ struct SMMUState { QLIST_HEAD(, SMMUDevice) devices_with_notifiers; uint8_t bus_num; PCIBus *primary_bus; + + /* For smmuv3-accel */ + bool accel; }; =20 struct SMMUBaseClass { diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h new file mode 100644 index 0000000000..56fe376bf4 --- /dev/null +++ b/include/hw/arm/smmuv3-accel.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_SMMUV3_ACCEL_H +#define HW_ARM_SMMUV3_ACCEL_H + +#include "hw/arm/smmu-common.h" +#include "hw/arm/smmuv3.h" +#include "qom/object.h" + +#define TYPE_ARM_SMMUV3_ACCEL "arm-smmuv3-accel" +OBJECT_DECLARE_TYPE(SMMUv3AccelState, SMMUv3AccelClass, ARM_SMMUV3_ACCEL) + +struct SMMUv3AccelState { + SMMUv3State smmuv3_state; +}; + +struct SMMUv3AccelClass { + /*< private >*/ + SMMUv3Class smmuv3_class; + /*< public >*/ + + DeviceRealize parent_realize; +}; + +#endif /* HW_ARM_SMMUV3_ACCEL_H */ --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702360; cv=none; d=zohomail.com; s=zohoarc; b=ngwcL2VR1LHmlpx0Ug4YCV7/B3Z68FNKnsC1wWz3Z80LQKosm+t9ZtcQ249uU/C6JMhd7EtafWkqic3G5BnKrpCZKKF9KH5xxG80+Nvf+mVKKHlwg0inUDgl+JTeGOMYKA2RJ199vJCjTEMXM3BO4tjnbKkPUSCposHMfDJXnhE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741702360; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 11 Mar 2025 10:12:32 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwZm2z2nz6F9Br; Tue, 11 Mar 2025 22:08:00 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id EED41140CB9; Tue, 11 Mar 2025 22:12:25 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:12:18 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 04/20] hw/arm/virt: Add support for smmuv3-accel Date: Tue, 11 Mar 2025 14:10:29 +0000 Message-ID: <20250311141045.66620-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702362677019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow cold-plug smmuv3-accel to virt If the machine wide smmuv3 is not specified. No FDT support is added for now. Signed-off-by: Shameer Kolothum --- hw/arm/virt.c | 12 ++++++++++++ hw/core/sysbus-fdt.c | 1 + include/hw/arm/virt.h | 1 + 3 files changed, 14 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4a5a9666e9..84a323da55 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -73,6 +73,7 @@ #include "qobject/qlist.h" #include "standard-headers/linux/input.h" #include "hw/arm/smmuv3.h" +#include "hw/arm/smmuv3-accel.h" #include "hw/acpi/acpi.h" #include "target/arm/cpu-qom.h" #include "target/arm/internals.h" @@ -2911,6 +2912,16 @@ static void virt_machine_device_plug_cb(HotplugHandl= er *hotplug_dev, platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus= _dev), SYS_BUS_DEVICE(dev)); } + if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3_ACCEL)) { + if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { + error_setg(errp, + "iommu=3Dsmmuv3 is already specified. can't cre= ate smmuv3-accel dev"); + return; + } + if (vms->iommu !=3D VIRT_IOMMU_SMMUV3_ACCEL) { + vms->iommu =3D VIRT_IOMMU_SMMUV3_ACCEL; + } + } } =20 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { @@ -3120,6 +3131,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ARM_SMMUV3_ACCEL); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); #endif diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c index 774c0aed41..c8502ad830 100644 --- a/hw/core/sysbus-fdt.c +++ b/hw/core/sysbus-fdt.c @@ -489,6 +489,7 @@ static const BindingEntry bindings[] =3D { #ifdef CONFIG_LINUX TYPE_BINDING(TYPE_VFIO_CALXEDA_XGMAC, add_calxeda_midway_xgmac_fdt_nod= e), TYPE_BINDING(TYPE_VFIO_AMD_XGBE, add_amd_xgbe_fdt_node), + TYPE_BINDING("arm-smmuv3-accel", no_fdt_node), VFIO_PLATFORM_BINDING("amd,xgbe-seattle-v1a", add_amd_xgbe_fdt_node), #endif #ifdef CONFIG_TPM diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index c8e94e6aed..849d1cd5b5 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -92,6 +92,7 @@ enum { typedef enum VirtIOMMUType { VIRT_IOMMU_NONE, VIRT_IOMMU_SMMUV3, + VIRT_IOMMU_SMMUV3_ACCEL, VIRT_IOMMU_VIRTIO, } VirtIOMMUType; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702392349019100 User=C2=A0must associate a pxb-pcie root bus to smmuv3-accel and that is=C2=A0set as the primary-bus for the smmu dev. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index c327661636..1471b65374 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -9,6 +9,21 @@ #include "qemu/osdep.h" =20 #include "hw/arm/smmuv3-accel.h" +#include "hw/pci/pci_bridge.h" + +static int smmuv3_accel_pxb_pcie_bus(Object *obj, void *opaque) +{ + DeviceState *d =3D opaque; + + if (object_dynamic_cast(obj, "pxb-pcie-bus")) { + PCIBus *bus =3D PCI_HOST_BRIDGE(obj->parent)->bus; + if (d->parent_bus && !strcmp(bus->qbus.name, d->parent_bus->name))= { + object_property_set_link(OBJECT(d), "primary-bus", OBJECT(bus), + &error_abort); + } + } + return 0; +} =20 static void smmu_accel_realize(DeviceState *d, Error **errp) { @@ -17,6 +32,9 @@ static void smmu_accel_realize(DeviceState *d, Error **er= rp) SysBusDevice *dev =3D SYS_BUS_DEVICE(d); Error *local_err =3D NULL; =20 + object_child_foreach_recursive(object_get_root(), + smmuv3_accel_pxb_pcie_bus, d); + object_property_set_bool(OBJECT(dev), "accel", true, &error_abort); c->parent_realize(d, &local_err); if (local_err) { @@ -33,6 +51,7 @@ static void smmuv3_accel_class_init(ObjectClass *klass, v= oid *data) device_class_set_parent_realize(dc, smmu_accel_realize, &c->parent_realize); dc->hotpluggable =3D false; + dc->bus_type =3D TYPE_PCIE_BUS; } =20 static const TypeInfo smmuv3_accel_type_info =3D { --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702413; cv=none; d=zohomail.com; s=zohoarc; b=Wnc9k+ugyw688lsw3jWOi5RXeOtqxetpD4JwMA6ArEeDztK5m4RetOZnfyXZJnc5DmqwZunLMa0ZZ38Srx+8NNA3IuCJiceVbRkEjfPjn7EuEZcOYSTy8e0YVAr7S5uEZvvviZd0XSbSgpzHjAurMoQ4Yt5tIUSkAKCZbXtEE84= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702415244019000 Subsequent=C2=A0patches for smmuv3-accel will make use of this Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- hw/arm/smmu-common.c | 48 ++++++++++++++++++++++-------------- include/hw/arm/smmu-common.h | 6 +++++ 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index f5caf1665c..83c0693f5a 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -826,12 +826,28 @@ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8= _t bus_num) return NULL; } =20 -static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +void smmu_init_sdev(SMMUState *s, SMMUDevice *sdev, + PCIBus *bus, int devfn) { - SMMUState *s =3D opaque; - SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); - SMMUDevice *sdev; static unsigned int index; + char *name =3D g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, index= ++); + + sdev->smmu =3D s; + sdev->bus =3D bus; + sdev->devfn =3D devfn; + + memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), + s->mrtypename, + OBJECT(s), name, UINT64_MAX); + address_space_init(&sdev->as, + MEMORY_REGION(&sdev->iommu), name); + trace_smmu_add_mr(name); + g_free(name); +} + +SMMUPciBus *smmu_get_sbus(SMMUState *s, PCIBus *bus) +{ + SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); =20 if (!sbus) { sbus =3D g_malloc0(sizeof(SMMUPciBus) + @@ -840,23 +856,19 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, vo= id *opaque, int devfn) g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus); } =20 + return sbus; +} + +static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +{ + SMMUDevice *sdev; + SMMUState *s =3D opaque; + SMMUPciBus *sbus =3D smmu_get_sbus(s, bus); + sdev =3D sbus->pbdev[devfn]; if (!sdev) { - char *name =3D g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, i= ndex++); - sdev =3D sbus->pbdev[devfn] =3D g_new0(SMMUDevice, 1); - - sdev->smmu =3D s; - sdev->bus =3D bus; - sdev->devfn =3D devfn; - - memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), - s->mrtypename, - OBJECT(s), name, UINT64_MAX); - address_space_init(&sdev->as, - MEMORY_REGION(&sdev->iommu), name); - trace_smmu_add_mr(name); - g_free(name); + smmu_init_sdev(s, sdev, bus, devfn); } =20 return &sdev->as; diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index b5c63cfd5d..80ff2ef6aa 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -178,6 +178,12 @@ OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) /* Return the SMMUPciBus handle associated to a PCI bus number */ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); =20 +/* Return the SMMUPciBus handle associated to a PCI bus */ +SMMUPciBus *smmu_get_sbus(SMMUState *s, PCIBus *bus); + +/* Initialize SMMUDevice handle associated to a SMMUPCIBus */ +void smmu_init_sdev(SMMUState *s, SMMUDevice *sdev, PCIBus *bus, int devfn= ); + /* Return the stream ID of an SMMU device */ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) { --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702427; cv=none; d=zohomail.com; s=zohoarc; b=RY0BeLeLUmBnrg5ecQdfEA+5vr37Vx7SITJ4P6dzzeFPKj6ZJsm20efWZAyBoiJtGDkbBdQzWJPnUB/bmtQGGnXYpB25dW6J2NpNEXiEukG35lDFUWOI526Ei6cMMtRiHWEEw0C27rO2nwnlB92QuKpt5opwbPF5KywTfmKFfvQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Tue, 11 Mar 2025 10:13:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Lq-0001z4-BO; Tue, 11 Mar 2025 10:13:01 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Lo-0006za-Ln; Tue, 11 Mar 2025 10:12:58 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwdT5Y4pz6D8cG; Tue, 11 Mar 2025 22:10:21 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 5D7DC140B63; Tue, 11 Mar 2025 22:12:54 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:12:46 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 07/20] hw/arm/smmu-common: Introduce callbacks for PCIIOMMUOps Date: Tue, 11 Mar 2025 14:10:32 +0000 Message-ID: <20250311141045.66620-8-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702429511019000 Subsequently smmuv3-accel will provide=C2=A0these callbacks Signed-off-by: Shameer Kolothum --- hw/arm/smmu-common.c | 27 +++++++++++++++++++++++++++ include/hw/arm/smmu-common.h | 5 +++++ 2 files changed, 32 insertions(+) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 83c0693f5a..9fd455baa0 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -865,6 +865,10 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, voi= d *opaque, int devfn) SMMUState *s =3D opaque; SMMUPciBus *sbus =3D smmu_get_sbus(s, bus); =20 + if (s->accel && s->get_address_space) { + return s->get_address_space(bus, opaque, devfn); + } + sdev =3D sbus->pbdev[devfn]; if (!sdev) { sdev =3D sbus->pbdev[devfn] =3D g_new0(SMMUDevice, 1); @@ -874,8 +878,31 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, voi= d *opaque, int devfn) return &sdev->as; } =20 +static bool smmu_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, + HostIOMMUDevice *hiod, Error **errp) +{ + SMMUState *s =3D opaque; + + if (s->accel && s->set_iommu_device) { + return s->set_iommu_device(bus, opaque, devfn, hiod, errp); + } + + return false; +} + +static void smmu_dev_unset_iommu_device(PCIBus *bus, void *opaque, int dev= fn) +{ + SMMUState *s =3D opaque; + + if (s->accel && s->unset_iommu_device) { + s->unset_iommu_device(bus, opaque, devfn); + } +} + static const PCIIOMMUOps smmu_ops =3D { .get_address_space =3D smmu_find_add_as, + .set_iommu_device =3D smmu_dev_set_iommu_device, + .unset_iommu_device =3D smmu_dev_unset_iommu_device, }; =20 SMMUDevice *smmu_find_sdev(SMMUState *s, uint32_t sid) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 80ff2ef6aa..7b05640167 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -160,6 +160,11 @@ struct SMMUState { =20 /* For smmuv3-accel */ bool accel; + + AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int dev= fn); + bool (*set_iommu_device)(PCIBus *bus, void *opaque, int devfn, + HostIOMMUDevice *dev, Error **errp); + void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); }; =20 struct SMMUBaseClass { --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702427; cv=none; d=zohomail.com; s=zohoarc; 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Tue, 11 Mar 2025 15:12:57 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 08/20] hw/arm/smmuv3-accel: Provide get_address_space callback Date: Tue, 11 Mar 2025 14:10:33 +0000 Message-ID: <20250311141045.66620-9-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702429643019000 Also introduce a struct SMMUv3AccelDevice=C2=A0to hold accelerator specific device info. This will be populated accordingly in subsequent=C2=A0patches. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 36 +++++++++++++++++++++++++++++++++++ include/hw/arm/smmuv3-accel.h | 4 ++++ 2 files changed, 40 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 1471b65374..6610ebe4be 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -11,6 +11,40 @@ #include "hw/arm/smmuv3-accel.h" #include "hw/pci/pci_bridge.h" =20 +static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *s, SMMUPciBus *s= bus, + PCIBus *bus, int devfn) +{ + SMMUDevice *sdev =3D sbus->pbdev[devfn]; + SMMUv3AccelDevice *accel_dev; + + if (sdev) { + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + } else { + accel_dev =3D g_new0(SMMUv3AccelDevice, 1); + sdev =3D &accel_dev->sdev; + + sbus->pbdev[devfn] =3D sdev; + smmu_init_sdev(s, sdev, bus, devfn); + } + + return accel_dev; +} + +static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *s =3D opaque; + SMMUPciBus *sbus; + SMMUv3AccelDevice *accel_dev; + SMMUDevice *sdev; + + sbus =3D smmu_get_sbus(s, bus); + accel_dev =3D smmuv3_accel_get_dev(s, sbus, bus, devfn); + sdev =3D &accel_dev->sdev; + + return &sdev->as; +} + static int smmuv3_accel_pxb_pcie_bus(Object *obj, void *opaque) { DeviceState *d =3D opaque; @@ -30,6 +64,7 @@ static void smmu_accel_realize(DeviceState *d, Error **er= rp) SMMUv3AccelState *s_accel =3D ARM_SMMUV3_ACCEL(d); SMMUv3AccelClass *c =3D ARM_SMMUV3_ACCEL_GET_CLASS(s_accel); SysBusDevice *dev =3D SYS_BUS_DEVICE(d); + SMMUState *bs =3D ARM_SMMU(d); Error *local_err =3D NULL; =20 object_child_foreach_recursive(object_get_root(), @@ -41,6 +76,7 @@ static void smmu_accel_realize(DeviceState *d, Error **er= rp) error_propagate(errp, local_err); return; } + bs->get_address_space =3D smmuv3_accel_find_add_as; } =20 static void smmuv3_accel_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h index 56fe376bf4..86c0523063 100644 --- a/include/hw/arm/smmuv3-accel.h +++ b/include/hw/arm/smmuv3-accel.h @@ -16,6 +16,10 @@ #define TYPE_ARM_SMMUV3_ACCEL "arm-smmuv3-accel" OBJECT_DECLARE_TYPE(SMMUv3AccelState, SMMUv3AccelClass, ARM_SMMUV3_ACCEL) =20 +typedef struct SMMUv3AccelDevice { + SMMUDevice sdev; +} SMMUv3AccelDevice; + struct SMMUv3AccelState { SMMUv3State smmuv3_state; }; --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702426; cv=none; d=zohomail.com; s=zohoarc; b=OPcGJJ1lHLIKfIs4f4vxcb083UGMK69LOvrvMtCb6d59X6K7ldMJLnfpn+F9A0GO5iVK2sJGb3e3mSRjuXoY7LD1WVjfKIbwZAQLmJkT3AXGcraXVL2N7tydS1iFn2jyHv6vvcyEdJulz0qUfBgkI1J802bTBKjKvb9Uqc/98+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741702426; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=rtHvLcVu9UM+iGiSX/4f2MoBi5KGjfENs08W+Da/+Oc=; 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Tue, 11 Mar 2025 10:13:22 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwdG1bclz6D9dy; Tue, 11 Mar 2025 22:10:10 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 07C451404F5; Tue, 11 Mar 2025 22:13:17 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:13:09 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 09/20] hw/arm/smmuv3-accel: Add set/unset_iommu_device callback Date: Tue, 11 Mar 2025 14:10:34 +0000 Message-ID: <20250311141045.66620-10-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702427265019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Implement a set_iommu_device callback: -Find an existing S2 hwpt to test attach() or allocate a new one (Devices behind the same physical SMMU should share an S2 HWPT.) -Attach the device to the S2 hwp -Allocate a viommu with the returned s2 hwpt. -Allocate bypass and abort hwpt and attach bypass hwpt. -and add it to its device list Also add an unset_iommu_device doing the opposite cleanup routine. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/meson.build | 2 +- hw/arm/smmuv3-accel.c | 183 ++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 4 + include/hw/arm/smmuv3-accel.h | 23 +++++ include/system/iommufd.h | 6 ++ 5 files changed, 217 insertions(+), 1 deletion(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index e8593363b0..dd41a86619 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -55,7 +55,7 @@ arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c'= )) arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-= sabre.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) -arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c= ')) +arm_ss.add(when: ['CONFIG_ARM_SMMUV3_ACCEL', 'CONFIG_IOMMUFD'], if_true: f= iles('smmuv3-accel.c')) arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcim= x6ul-evk.c')) arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 6610ebe4be..1c696649d5 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -7,6 +7,8 @@ */ =20 #include "qemu/osdep.h" +#include "trace.h" +#include "qemu/error-report.h" =20 #include "hw/arm/smmuv3-accel.h" #include "hw/pci/pci_bridge.h" @@ -30,6 +32,185 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *s, SMMUPciBus *sbus, return accel_dev; } =20 +static bool +smmuv3_accel_dev_attach_viommu(SMMUv3AccelDevice *accel_dev, + HostIOMMUDeviceIOMMUFD *idev, Error **errp) +{ + struct iommu_hwpt_arm_smmuv3 bypass_data =3D { + .ste =3D { 0x9ULL, 0x0ULL }, + }; + struct iommu_hwpt_arm_smmuv3 abort_data =3D { + .ste =3D { 0x1ULL, 0x0ULL }, + }; + SMMUDevice *sdev =3D &accel_dev->sdev; + SMMUState *s =3D sdev->smmu; + SMMUv3AccelState *s_accel =3D ARM_SMMUV3_ACCEL(s); + SMMUS2Hwpt *s2_hwpt; + SMMUViommu *viommu; + uint32_t s2_hwpt_id; + uint32_t viommu_id; + + if (s_accel->viommu) { + accel_dev->viommu =3D s_accel->viommu; + return host_iommu_device_iommufd_attach_hwpt( + idev, s_accel->viommu->s2_hwpt->hwpt_id, errp); + } + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, idev->ioas= _id, + IOMMU_HWPT_ALLOC_NEST_PARENT, + IOMMU_HWPT_DATA_NONE, 0, NULL, + &s2_hwpt_id, errp)) { + return false; + } + + /* Attach to S2 for MSI cookie */ + if (!host_iommu_device_iommufd_attach_hwpt(idev, s2_hwpt_id, errp)) { + goto free_s2_hwpt; + } + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, &viommu_id, errp)) { + goto detach_s2_hwpt; + } + + viommu =3D g_new0(SMMUViommu, 1); + viommu->core.viommu_id =3D viommu_id; + viommu->core.s2_hwpt_id =3D s2_hwpt_id; + viommu->core.iommufd =3D idev->iommufd; + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(abort_data), &abort_data, + &viommu->abort_hwpt_id, errp)) { + error_report("failed to allocate an abort pagetable"); + goto free_viommu; + } + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(bypass_data), &bypass_data, + &viommu->bypass_hwpt_id, errp)) { + error_report("failed to allocate a bypass pagetable"); + goto free_abort_hwpt; + } + + /* + * Attach the bypass STE which means S1 bypass and S2 translate. + * This is to make sure that the vIOMMU object is now associated + * with the device and has this STE installed in the host SMMUV3. + */ + if (!host_iommu_device_iommufd_attach_hwpt( + idev, viommu->bypass_hwpt_id, errp)) { + error_report("failed to attach the bypass pagetable"); + goto free_bypass_hwpt; + } + + s2_hwpt =3D g_new0(SMMUS2Hwpt, 1); + s2_hwpt->iommufd =3D idev->iommufd; + s2_hwpt->hwpt_id =3D s2_hwpt_id; + s2_hwpt->ioas_id =3D idev->ioas_id; + + viommu->iommufd =3D idev->iommufd; + viommu->s2_hwpt =3D s2_hwpt; + + s_accel->viommu =3D viommu; + accel_dev->viommu =3D viommu; + return true; + +free_bypass_hwpt: + iommufd_backend_free_id(idev->iommufd, viommu->bypass_hwpt_id); +free_abort_hwpt: + iommufd_backend_free_id(idev->iommufd, viommu->abort_hwpt_id); +free_viommu: + iommufd_backend_free_id(idev->iommufd, viommu->core.viommu_id); + g_free(viommu); +detach_s2_hwpt: + host_iommu_device_iommufd_attach_hwpt(idev, accel_dev->idev->ioas_id, = errp); +free_s2_hwpt: + iommufd_backend_free_id(idev->iommufd, s2_hwpt_id); + return false; +} + +static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, + HostIOMMUDevice *hiod, Error **e= rrp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); + SMMUState *s =3D opaque; + SMMUv3AccelState *s_accel =3D ARM_SMMUV3_ACCEL(s); + SMMUPciBus *sbus =3D smmu_get_sbus(s, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(s, sbus, bus, de= vfn); + SMMUDevice *sdev =3D &accel_dev->sdev; + + if (!idev) { + return true; + } + + if (accel_dev->idev) { + if (accel_dev->idev !=3D idev) { + error_report("Device 0x%x already ha an associated idev", + smmu_get_sid(sdev)); + return false; + } else { + return true; + } + } + + if (!smmuv3_accel_dev_attach_viommu(accel_dev, idev, errp)) { + error_report("Unable to attach viommu"); + return false; + } + + accel_dev->idev =3D idev; + QLIST_INSERT_HEAD(&s_accel->viommu->device_list, accel_dev, next); + trace_smmuv3_accel_set_iommu_device(devfn, smmu_get_sid(sdev)); + return true; +} + +static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUDevice *sdev; + SMMUv3AccelDevice *accel_dev; + SMMUViommu *viommu; + SMMUState *s =3D opaque; + SMMUv3AccelState *s_accel =3D ARM_SMMUV3_ACCEL(s); + SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); + + if (!sbus) { + return; + } + + sdev =3D sbus->pbdev[devfn]; + if (!sdev) { + return; + } + + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->idev, + accel_dev->idev->ioas_id, + NULL)) { + error_report("Unable to attach dev to the default HW pagetable"); + } + + + accel_dev->idev =3D NULL; + QLIST_REMOVE(accel_dev, next); + trace_smmuv3_accel_unset_iommu_device(devfn, smmu_get_sid(sdev)); + + viommu =3D s_accel->viommu; + if (QLIST_EMPTY(&viommu->device_list)) { + iommufd_backend_free_id(viommu->iommufd, viommu->bypass_hwpt_id); + iommufd_backend_free_id(viommu->iommufd, viommu->abort_hwpt_id); + iommufd_backend_free_id(viommu->iommufd, viommu->core.viommu_id); + iommufd_backend_free_id(viommu->iommufd, viommu->s2_hwpt->hwpt_id); + g_free(viommu->s2_hwpt); + g_free(viommu); + s_accel->viommu =3D NULL; + } +} static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, int devfn) { @@ -77,6 +258,8 @@ static void smmu_accel_realize(DeviceState *d, Error **e= rrp) return; } bs->get_address_space =3D smmuv3_accel_find_add_as; + bs->set_iommu_device =3D smmuv3_accel_set_iommu_device; + bs->unset_iommu_device =3D smmuv3_accel_unset_iommu_device; } =20 static void smmuv3_accel_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 7790db780e..17960794bf 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -58,6 +58,10 @@ smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotif= ier node for iommu mr=3D%s smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=3D%s asid=3D%d vm= id=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" stage=3D%d" smmu_reset_exit(void) "" =20 +#smmuv3-accel.c +smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" +smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h index 86c0523063..aca6838dca 100644 --- a/include/hw/arm/smmuv3-accel.h +++ b/include/hw/arm/smmuv3-accel.h @@ -12,16 +12,39 @@ #include "hw/arm/smmu-common.h" #include "hw/arm/smmuv3.h" #include "qom/object.h" +#include "system/iommufd.h" + +#include =20 #define TYPE_ARM_SMMUV3_ACCEL "arm-smmuv3-accel" OBJECT_DECLARE_TYPE(SMMUv3AccelState, SMMUv3AccelClass, ARM_SMMUV3_ACCEL) =20 +typedef struct SMMUS2Hwpt { + IOMMUFDBackend *iommufd; + uint32_t hwpt_id; + uint32_t ioas_id; +} SMMUS2Hwpt; + +typedef struct SMMUViommu { + IOMMUFDBackend *iommufd; + IOMMUFDViommu core; + SMMUS2Hwpt *s2_hwpt; + uint32_t bypass_hwpt_id; + uint32_t abort_hwpt_id; + QLIST_HEAD(, SMMUv3AccelDevice) device_list; + QLIST_ENTRY(SMMUViommu) next; +} SMMUViommu; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; + HostIOMMUDeviceIOMMUFD *idev; + SMMUViommu *viommu; + QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; =20 struct SMMUv3AccelState { SMMUv3State smmuv3_state; + SMMUViommu *viommu; }; =20 struct SMMUv3AccelClass { diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 53920bae5b..9c106ea078 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -37,6 +37,12 @@ struct IOMMUFDBackend { /*< public >*/ }; =20 +typedef struct IOMMUFDViommu { + IOMMUFDBackend *iommufd; + uint32_t s2_hwpt_id; + uint32_t viommu_id; +} IOMMUFDViommu; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); 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Tue, 11 Mar 2025 10:13:32 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwdR23DZz6D9Ry; Tue, 11 Mar 2025 22:10:19 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 2783C14034E; Tue, 11 Mar 2025 22:13:26 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:13:18 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 10/20] hw/arm/smmuv3-accel: Support nested STE install/uninstall support Date: Tue, 11 Mar 2025 14:10:35 +0000 Message-ID: <20250311141045.66620-11-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702430377019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Allocates a s1 HWPT for the Guest s1 stage and attaches that to the dev. This will be invoked in a subsequent patch when Guest issues SMMU_CMD_CFGI_STE. While at it, we are also exporting both smmu_find_ste() and smmuv3_flush_config() from smmuv3.c for use here. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 111 ++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-internal.h | 13 ++++ hw/arm/smmuv3.c | 5 +- hw/arm/trace-events | 1 + include/hw/arm/smmuv3-accel.h | 6 ++ 5 files changed, 133 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 1c696649d5..d3a5cf9551 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -13,6 +13,8 @@ #include "hw/arm/smmuv3-accel.h" #include "hw/pci/pci_bridge.h" =20 +#include "smmuv3-internal.h" + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *s, SMMUPciBus *s= bus, PCIBus *bus, int devfn) { @@ -32,6 +34,115 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *s, SMMUPciBus *sbus, return accel_dev; } =20 +static void +smmuv3_accel_dev_uninstall_nested_ste(SMMUv3AccelDevice *accel_dev, bool a= bort) +{ + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + SMMUS1Hwpt *s1_hwpt =3D accel_dev->s1_hwpt; + uint32_t hwpt_id; + + if (!s1_hwpt || !accel_dev->viommu) { + return; + } + + if (abort) { + hwpt_id =3D accel_dev->viommu->abort_hwpt_id; + } else { + hwpt_id =3D accel_dev->viommu->bypass_hwpt_id; + } + + host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, &error_abort); + iommufd_backend_free_id(s1_hwpt->iommufd, s1_hwpt->hwpt_id); + accel_dev->s1_hwpt =3D NULL; + g_free(s1_hwpt); +} + +static int +smmuv3_accel_dev_install_nested_ste(SMMUv3AccelDevice *accel_dev, + uint32_t data_type, uint32_t data_len, + void *data) +{ + SMMUViommu *viommu =3D accel_dev->viommu; + SMMUS1Hwpt *s1_hwpt =3D accel_dev->s1_hwpt; + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + + if (!idev || !viommu) { + return -ENOENT; + } + + if (s1_hwpt) { + smmuv3_accel_dev_uninstall_nested_ste(accel_dev, false); + } + + s1_hwpt =3D g_new0(SMMUS1Hwpt, 1); + if (!s1_hwpt) { + return -ENOMEM; + } + + s1_hwpt->iommufd =3D idev->iommufd; + iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, data_type, data_= len, + data, &s1_hwpt->hwpt_id, &error_abort); + host_iommu_device_iommufd_attach_hwpt(idev, s1_hwpt->hwpt_id, &error_a= bort); + accel_dev->s1_hwpt =3D s1_hwpt; + return 0; +} + +void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int sid) +{ + SMMUv3AccelDevice *accel_dev; + SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, + .inval_ste_allowed =3D true}; + struct iommu_hwpt_arm_smmuv3 nested_data =3D {}; + SMMUv3State *s =3D sdev->smmu; + SMMUState *bs =3D &s->smmu_state; + uint32_t config; + STE ste; + int ret; + + if (!bs->accel) { + return; + } + + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!accel_dev->viommu) { + return; + } + + ret =3D smmu_find_ste(sdev->smmu, sid, &ste, &event); + if (ret) { + /* + * For a 2-level Stream Table, the level-2 table might not be ready + * until the device gets inserted to the stream table. Ignore this. + */ + return; + } + + config =3D STE_CONFIG(&ste); + if (!STE_VALID(&ste) || !STE_CFG_S1_ENABLED(config)) { + smmuv3_accel_dev_uninstall_nested_ste(accel_dev, STE_CFG_ABORT(con= fig)); + smmuv3_flush_config(sdev); + return; + } + + nested_data.ste[0] =3D (uint64_t)ste.word[0] | (uint64_t)ste.word[1] <= < 32; + nested_data.ste[1] =3D (uint64_t)ste.word[2] | (uint64_t)ste.word[3] <= < 32; + /* V | CONFIG | S1FMT | S1CTXPTR | S1CDMAX */ + nested_data.ste[0] &=3D 0xf80fffffffffffffULL; + /* S1DSS | S1CIR | S1COR | S1CSH | S1STALLD | EATS */ + nested_data.ste[1] &=3D 0x380000ffULL; + ret =3D smmuv3_accel_dev_install_nested_ste(accel_dev, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(nested_data), + &nested_data); + if (ret) { + error_report("Unable to install nested STE=3D%16LX:%16LX, ret=3D%d= ", + nested_data.ste[1], nested_data.ste[0], ret); + } + trace_smmuv3_accel_install_nested_ste(sid, nested_data.ste[1], + nested_data.ste[0]); +} + static bool smmuv3_accel_dev_attach_viommu(SMMUv3AccelDevice *accel_dev, HostIOMMUDeviceIOMMUFD *idev, Error **errp) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index b6b7399347..46c8bcae14 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -24,6 +24,8 @@ #include "hw/registerfields.h" #include "hw/arm/smmu-common.h" =20 +#include CONFIG_DEVICES + typedef enum SMMUTranslationStatus { SMMU_TRANS_DISABLE, SMMU_TRANS_ABORT, @@ -547,6 +549,17 @@ typedef struct CD { uint32_t word[16]; } CD; =20 +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, + SMMUEventInfo *event); +void smmuv3_flush_config(SMMUDevice *sdev); + +#if defined(CONFIG_ARM_SMMUV3_ACCEL) && defined(CONFIG_IOMMUFD) +void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int sid); +#else +static inline void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int s= id) +{ +} +#endif /* STE fields */ =20 #define STE_VALID(x) extract32((x)->word[0], 0, 1) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b49a59b64c..ea63731d61 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -628,8 +628,7 @@ bad_ste: * Supports linear and 2-level stream table * Return 0 on success, -EINVAL otherwise */ -static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, - SMMUEventInfo *event) +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *e= vent) { dma_addr_t addr, strtab_base; uint32_t log2size; @@ -898,7 +897,7 @@ static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev= , SMMUEventInfo *event) return cfg; } =20 -static void smmuv3_flush_config(SMMUDevice *sdev) +void smmuv3_flush_config(SMMUDevice *sdev) { SMMUv3State *s =3D sdev->smmu; SMMUState *bc =3D &s->smmu_state; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 17960794bf..cd2eac31c2 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -61,6 +61,7 @@ smmu_reset_exit(void) "" #smmuv3-accel.c smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x" +smmuv3_accel_install_nested_ste(uint32_t sid, uint64_t ste_1, uint64_t ste= _0) "sid=3D%d ste=3D%"PRIx64":%"PRIx64 =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h index aca6838dca..d6b0b1ca30 100644 --- a/include/hw/arm/smmuv3-accel.h +++ b/include/hw/arm/smmuv3-accel.h @@ -35,9 +35,15 @@ typedef struct SMMUViommu { QLIST_ENTRY(SMMUViommu) next; } SMMUViommu; =20 +typedef struct SMMUS1Hwpt { + IOMMUFDBackend *iommufd; + uint32_t hwpt_id; +} SMMUS1Hwpt; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; HostIOMMUDeviceIOMMUFD *idev; + SMMUS1Hwpt *s1_hwpt; SMMUViommu *viommu; QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702435; cv=none; d=zohomail.com; s=zohoarc; b=n5kG8FvRZ2joe1A9pXzLh0jkW8RUzGiPmY4YRy+n1t2LPyT2vFE3Pr2VLqZwKkZopb+s+3YgLWpsHFvEcNgRST9m7mSvNjdJuqzVCjCcdSCeI1LVG1ZNNzRbHuqc+QUa91e7/DXXlOVjY0Ampp4kV93U6hfJos5uQ3cRwghj8IU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741702435; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702436298019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Allocate and associate a vDEVICE object for the Guest device with the vIOMMU. This will help the kernel to do the vSID --> sid translation whenever required (eg: device specific invalidations). Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 22 ++++++++++++++++++++++ include/hw/arm/smmuv3-accel.h | 6 ++++++ 2 files changed, 28 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index d3a5cf9551..056bd23b2e 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -109,6 +109,20 @@ void smmuv3_accel_install_nested_ste(SMMUDevice *sdev,= int sid) return; } =20 + if (!accel_dev->vdev && accel_dev->idev) { + SMMUVdev *vdev; + uint32_t vdev_id; + SMMUViommu *viommu =3D accel_dev->viommu; + + iommufd_backend_alloc_vdev(viommu->core.iommufd, accel_dev->idev->= devid, + viommu->core.viommu_id, sid, &vdev_id, + &error_abort); + vdev =3D g_new0(SMMUVdev, 1); + vdev->vdev_id =3D vdev_id; + vdev->sid =3D sid; + accel_dev->vdev =3D vdev; + } + ret =3D smmu_find_ste(sdev->smmu, sid, &ste, &event); if (ret) { /* @@ -283,6 +297,7 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus, = void *opaque, int devfn, static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque, int devfn) { + SMMUVdev *vdev; SMMUDevice *sdev; SMMUv3AccelDevice *accel_dev; SMMUViommu *viommu; @@ -312,6 +327,13 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, trace_smmuv3_accel_unset_iommu_device(devfn, smmu_get_sid(sdev)); =20 viommu =3D s_accel->viommu; + vdev =3D accel_dev->vdev; + if (vdev) { + iommufd_backend_free_id(viommu->iommufd, vdev->vdev_id); + g_free(vdev); + accel_dev->vdev =3D NULL; + } + if (QLIST_EMPTY(&viommu->device_list)) { iommufd_backend_free_id(viommu->iommufd, viommu->bypass_hwpt_id); iommufd_backend_free_id(viommu->iommufd, viommu->abort_hwpt_id); diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h index d6b0b1ca30..54b217ab4f 100644 --- a/include/hw/arm/smmuv3-accel.h +++ b/include/hw/arm/smmuv3-accel.h @@ -35,6 +35,11 @@ typedef struct SMMUViommu { QLIST_ENTRY(SMMUViommu) next; } SMMUViommu; =20 +typedef struct SMMUVdev { + uint32_t vdev_id; + uint32_t sid; +} SMMUVdev; + typedef struct SMMUS1Hwpt { IOMMUFDBackend *iommufd; uint32_t hwpt_id; @@ -45,6 +50,7 @@ typedef struct SMMUv3AccelDevice { HostIOMMUDeviceIOMMUFD *idev; SMMUS1Hwpt *s1_hwpt; SMMUViommu *viommu; + SMMUVdev *vdev; QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; =20 --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702436; cv=none; d=zohomail.com; s=zohoarc; b=iEVb6Q0ETVqIHWp4Ubhtl3MatjF0bdAgkmix2zV+ACxljel3yWr/pqx/XRiJTYCR/8mRx8tL//cmFK1JDbzHLR7dkQoWPRlB+5AnuSaJ0QqRD+7vypgucegahXD2/pZcEuViO2WwuPljg39rtRCevGK2G7Xqa/e1gEQrtWrGShM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741702436; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 11 Mar 2025 10:13:50 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwdp1tZcz6D9r2; Tue, 11 Mar 2025 22:10:38 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 211F3140CF4; Tue, 11 Mar 2025 22:13:45 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:13:37 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 12/20] hw/arm/smmuv3-accel: Return sysmem if stage-1 is bypassed Date: Tue, 11 Mar 2025 14:10:37 +0000 Message-ID: <20250311141045.66620-13-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702438297019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen When nested translation is enabled, there are 2-stage translation occuring to two different address spaces: stage-1 in the iommu as, while stage-2 in the system as. If a device attached to the vSMMU doesn't enable stage-1 translation, e.g. vSTE sets to Config=3DBypass, the system as should be returned, so QEMU can set up system memory mappings onto the stage-2 page table. This is crucial for an iommufd enabled VFIO device as the VFIO core code would register an iommu notifier and replay the address space which should be bypassed for this nested translation case. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 22 +++++++++++++++++++++- include/hw/arm/smmuv3-accel.h | 3 +++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 056bd23b2e..76134d106a 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -18,6 +18,7 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *s, SMMUPciBus *s= bus, PCIBus *bus, int devfn) { + SMMUv3AccelState *s_accel =3D ARM_SMMUV3_ACCEL(s); SMMUDevice *sdev =3D sbus->pbdev[devfn]; SMMUv3AccelDevice *accel_dev; =20 @@ -29,6 +30,8 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState = *s, SMMUPciBus *sbus, =20 sbus->pbdev[devfn] =3D sdev; smmu_init_sdev(s, sdev, bus, devfn); + address_space_init(&accel_dev->as_sysmem, &s_accel->root, + "smmuv3-accel-sysmem"); } =20 return accel_dev; @@ -351,12 +354,23 @@ static AddressSpace *smmuv3_accel_find_add_as(PCIBus = *bus, void *opaque, SMMUPciBus *sbus; SMMUv3AccelDevice *accel_dev; SMMUDevice *sdev; + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); + bool has_iommufd =3D false; + + if (pdev) { + has_iommufd =3D object_property_find(OBJECT(pdev), "iommufd"); + } =20 sbus =3D smmu_get_sbus(s, bus); accel_dev =3D smmuv3_accel_get_dev(s, sbus, bus, devfn); sdev =3D &accel_dev->sdev; =20 - return &sdev->as; + /* Return the system as if the device uses stage-2 only */ + if (has_iommufd && !accel_dev->s1_hwpt) { + return &accel_dev->as_sysmem; + } else { + return &sdev->as; + } } =20 static int smmuv3_accel_pxb_pcie_bus(Object *obj, void *opaque) @@ -390,6 +404,12 @@ static void smmu_accel_realize(DeviceState *d, Error *= *errp) error_propagate(errp, local_err); return; } + + memory_region_init(&s_accel->root, OBJECT(s_accel), "root", UINT64_MAX= ); + memory_region_init_alias(&s_accel->sysmem, OBJECT(s_accel), + "smmuv3-accel-sysmem", get_system_memory(), 0, + memory_region_size(get_system_memory())); + memory_region_add_subregion(&s_accel->root, 0, &s_accel->sysmem); bs->get_address_space =3D smmuv3_accel_find_add_as; bs->set_iommu_device =3D smmuv3_accel_set_iommu_device; bs->unset_iommu_device =3D smmuv3_accel_unset_iommu_device; diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h index 54b217ab4f..58e68534c0 100644 --- a/include/hw/arm/smmuv3-accel.h +++ b/include/hw/arm/smmuv3-accel.h @@ -51,12 +51,15 @@ typedef struct SMMUv3AccelDevice { SMMUS1Hwpt *s1_hwpt; SMMUViommu *viommu; SMMUVdev *vdev; + AddressSpace as_sysmem; QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; =20 struct SMMUv3AccelState { SMMUv3State smmuv3_state; SMMUViommu *viommu; + MemoryRegion root; + MemoryRegion sysmem; }; =20 struct SMMUv3AccelClass { --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Tue, 11 Mar 2025 15:13:48 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 13/20] hw/arm/smmuv3-accel: Introduce helpers to batch and issue cache invalidations Date: Tue, 11 Mar 2025 14:10:38 +0000 Message-ID: <20250311141045.66620-14-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702464384019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Inroduce an SMMUCommandBatch and some helpers to batch and issue the commands. Currently separate out TLBI commands and device cache commands to avoid some errata on certain versions of SMMUs. Later it should check IIDR register to detect if underlying SMMU hw has such an erratum. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 69 ++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-internal.h | 29 +++++++++++++++++ 2 files changed, 98 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 76134d106a..09be838d22 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -160,6 +160,75 @@ void smmuv3_accel_install_nested_ste(SMMUDevice *sdev,= int sid) nested_data.ste[0]); } =20 +/* Update batch->ncmds to the number of execute cmds */ +int smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch) +{ + SMMUv3AccelState *s_accel =3D ARM_SMMUV3_ACCEL(bs); + uint32_t total =3D batch->ncmds; + IOMMUFDViommu *viommu_core; + int ret; + + if (!bs->accel) { + return 0; + } + + if (!s_accel->viommu) { + return 0; + } + viommu_core =3D &s_accel->viommu->core; + ret =3D iommufd_backend_invalidate_cache(viommu_core->iommufd, + viommu_core->viommu_id, + IOMMU_VIOMMU_INVALIDATE_DATA_AR= M_SMMUV3, + sizeof(Cmd), &batch->ncmds, + batch->cmds); + if (total !=3D batch->ncmds) { + error_report("%s failed: ret=3D%d, total=3D%d, done=3D%d", + __func__, ret, total, batch->ncmds); + return ret; + } + + batch->ncmds =3D 0; + batch->dev_cache =3D false; + return ret; +} + +int smmuv3_accel_batch_cmds(SMMUState *bs, SMMUDevice *sdev, + SMMUCommandBatch *batch, Cmd *cmd, + uint32_t *cons, bool dev_cache) +{ + int ret; + + if (!bs->accel) { + return 0; + } + + if (sdev) { + SMMUv3AccelDevice *accel_dev; + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!accel_dev->s1_hwpt) { + return 0; + } + } + + /* + * Currently separate out dev_cache and hwpt for safety, which might + * not be necessary if underlying HW SMMU does not have the errata. + * + * TODO check IIDR register values read from hw_info. + */ + if (batch->ncmds && (dev_cache !=3D batch->dev_cache)) { + ret =3D smmuv3_accel_issue_cmd_batch(bs, batch); + if (ret) { + *cons =3D batch->cons[batch->ncmds]; + return ret; + } + } + batch->dev_cache =3D dev_cache; + batch->cmds[batch->ncmds] =3D *cmd; + batch->cons[batch->ncmds++] =3D *cons; + return 0; +} + static bool smmuv3_accel_dev_attach_viommu(SMMUv3AccelDevice *accel_dev, HostIOMMUDeviceIOMMUFD *idev, Error **errp) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 46c8bcae14..4602ae6728 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -549,13 +549,42 @@ typedef struct CD { uint32_t word[16]; } CD; =20 +/** + * SMMUCommandBatch - batch of invalidation commands for smmuv3-accel + * @cmds: Pointer to list of commands + * @cons: Pointer to list of CONS corresponding to the commands + * @ncmds: Total ncmds in the batch + * @dev_cache: Issue to a device cache + */ +typedef struct SMMUCommandBatch { + Cmd *cmds; + uint32_t *cons; + uint32_t ncmds; + bool dev_cache; +} SMMUCommandBatch; + int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event); void smmuv3_flush_config(SMMUDevice *sdev); =20 #if defined(CONFIG_ARM_SMMUV3_ACCEL) && defined(CONFIG_IOMMUFD) +int smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch); +int smmuv3_accel_batch_cmds(SMMUState *bs, SMMUDevice *sdev, + SMMUCommandBatch *batch, Cmd *cmd, + uint32_t *cons, bool dev_cache); void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int sid); #else +static inline int smmuv3_accel_issue_cmd_batch(SMMUState *bs, + SMMUCommandBatch *batch) +{ + return 0; +} +static inline int smmuv3_accel_batch_cmds(SMMUState *bs, SMMUDevice *sdev, + SMMUCommandBatch *batch, Cmd *cm= d, + uint32_t *cons, bool dev_cache) +{ + return 0; +} static inline void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int s= id) { } --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702486; cv=none; d=zohomail.com; s=zohoarc; b=Wv/1Tmo+noKbz5DjScL150K40+hk5okLQ/9KUgWb/dgAr2YBrB+CegJobWarDhf9W1UBOowhbiEeZD2ZKWmHs7KbGhj41/LRGiuO7BjBjvnmFbfJttW/LT+OQAmT75JajytftXJQkWFWt6sexHa6IYnwRDWihmRhSVaMFYuETvo= ARC-Message-Signature: i=1; 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Tue, 11 Mar 2025 10:14:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Mz-0007Bh-7v; Tue, 11 Mar 2025 10:14:09 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Mw-0007At-Px; Tue, 11 Mar 2025 10:14:08 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwf96gGNz6D9js; Tue, 11 Mar 2025 22:10:57 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id C5DCF140DB0; Tue, 11 Mar 2025 22:14:04 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:13:57 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 14/20] hw/arm/smmuv3: Install nested ste for CFGI_STE Date: Tue, 11 Mar 2025 14:10:39 +0000 Message-ID: <20250311141045.66620-15-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ea63731d61..83159db1d4 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1286,6 +1286,7 @@ smmuv3_invalidate_ste(gpointer key, gpointer value, g= pointer user_data) if (sid < sid_range->start || sid > sid_range->end) { return false; } + smmuv3_accel_install_nested_ste(sdev, sid); trace_smmuv3_config_cache_inv(sid); return true; } @@ -1353,6 +1354,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_cfgi_ste(sid); smmuv3_flush_config(sdev); + smmuv3_accel_install_nested_ste(sdev, sid); =20 break; } --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Tue, 11 Mar 2025 15:14:07 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 15/20] hw/arm/smmuv3: Forward invalidation commands to hw Date: Tue, 11 Mar 2025 14:10:40 +0000 Message-ID: <20250311141045.66620-16-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702652392019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Use the provided smmuv3-accel helper functions to issue the command to physical SMMUv3. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-internal.h | 11 ++++++++ hw/arm/smmuv3.c | 58 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 4602ae6728..546f8faac0 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -235,6 +235,17 @@ static inline bool smmuv3_gerror_irq_enabled(SMMUv3Sta= te *s) #define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size) #define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size) =20 +static inline int smmuv3_q_ncmds(SMMUQueue *q) +{ + uint32_t prod =3D Q_PROD(q); + uint32_t cons =3D Q_CONS(q); + + if (Q_PROD_WRAP(q) =3D=3D Q_CONS_WRAP(q)) + return prod - cons; + else + return WRAP_MASK(q) - cons + prod; +} + static inline bool smmuv3_q_full(SMMUQueue *q) { return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) =3D=3D WRAP_MASK(q); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 83159db1d4..e0f225d0df 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1297,10 +1297,18 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) SMMUCmdError cmd_error =3D SMMU_CERROR_NONE; SMMUQueue *q =3D &s->cmdq; SMMUCommandType type =3D 0; + SMMUCommandBatch batch =3D {}; + uint32_t ncmds =3D 0; + =20 if (!smmuv3_cmdq_enabled(s)) { return 0; } + + ncmds =3D smmuv3_q_ncmds(q); + batch.cmds =3D g_new0(Cmd, ncmds); + batch.cons =3D g_new0(uint32_t, ncmds); + /* * some commands depend on register values, typically CR0. In case tho= se * register values change while handling the command, spec says it @@ -1395,6 +1403,13 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_cfgi_cd(sid); smmuv3_flush_config(sdev); + + if (smmuv3_accel_batch_cmds(sdev->smmu, sdev, &batch, &cmd, + &q->cons, true)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + break; } case SMMU_CMD_TLBI_NH_ASID: @@ -1418,6 +1433,13 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) trace_smmuv3_cmdq_tlbi_nh_asid(asid); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_asid_vmid(bs, asid, vmid); + + if (smmuv3_accel_batch_cmds(bs, NULL, &batch, &cmd, &q->cons, + false)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + break; } case SMMU_CMD_TLBI_NH_ALL: @@ -1445,6 +1467,12 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) trace_smmuv3_cmdq_tlbi_nsnh(); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_all(bs); + + if (smmuv3_accel_batch_cmds(bs, NULL, &batch, &cmd, &q->cons, + false)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; case SMMU_CMD_TLBI_NH_VAA: case SMMU_CMD_TLBI_NH_VA: @@ -1453,7 +1481,24 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; } smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1); + + if (smmuv3_accel_batch_cmds(bs, NULL, &batch, &cmd, &q->cons, + false)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + break; + case SMMU_CMD_ATC_INV: + { + SMMUDevice *sdev =3D smmu_find_sdev(bs, CMD_SID(&cmd)); + + if (smmuv3_accel_batch_cmds(sdev->smmu, sdev, &batch, &cmd, + &q->cons, true)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } break; + } case SMMU_CMD_TLBI_S12_VMALL: { int vmid =3D CMD_VMID(&cmd); @@ -1485,7 +1530,6 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) case SMMU_CMD_TLBI_EL2_ASID: case SMMU_CMD_TLBI_EL2_VA: case SMMU_CMD_TLBI_EL2_VAA: - case SMMU_CMD_ATC_INV: case SMMU_CMD_PRI_RESP: case SMMU_CMD_RESUME: case SMMU_CMD_STALL_TERM: @@ -1511,12 +1555,24 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) queue_cons_incr(q); } =20 + qemu_mutex_lock(&s->mutex); + if (!cmd_error && batch.ncmds) { + if (smmuv3_accel_issue_cmd_batch(bs, &batch)) { + q->cons =3D batch.cons[batch.ncmds]; + cmd_error =3D SMMU_CERROR_ILL; + } + } + qemu_mutex_unlock(&s->mutex); + if (cmd_error) { trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type), cmd_error); smmu_write_cmdq_err(s, cmd_error); smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_CMDQ_ERR_MASK); } =20 + g_free(batch.cmds); + g_free(batch.cons); + trace_smmuv3_cmdq_consume_out(Q_PROD(q), Q_CONS(q), Q_PROD_WRAP(q), Q_CONS_WRAP(q)); =20 --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702621; cv=none; d=zohomail.com; s=zohoarc; b=g/bp/bPfifqrFxMt/POCd6SImz9mxiVWrQpikLpz0KWQWvFsX253MsiTee1McyCsYc5f6VBSW6WANfwjmncKaKIhdNIZKSAkfzSg2feF2KrEUvKbcTsQvvwZkhlm3Z/eQX6p0rqILq2QvVUxw7AXLpFhkPWl5BQfiUibF7QDLOY= ARC-Message-Signature: i=1; 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Tue, 11 Mar 2025 10:14:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0NO-0001Y5-BB; Tue, 11 Mar 2025 10:14:34 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0NH-0007Dt-56; Tue, 11 Mar 2025 10:14:34 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwd245Fyz6FGWY; Tue, 11 Mar 2025 22:09:58 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 21667140CB9; Tue, 11 Mar 2025 22:14:24 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:14:16 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 16/20] hw/arm/smmuv3-accel: Read host SMMUv3 device info Date: Tue, 11 Mar 2025 14:10:41 +0000 Message-ID: <20250311141045.66620-17-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702622788019100 From: Nicolin Chen Read the underlying SMMUv3 device info and set corresponding IDR bits. We need at least one cold-plugged vfio-pci dev associated with the smmuv3-accel instance to do this now.=C2=A0 Hence fail if it is not available. ToDo: The above requirement will be relaxed in future when we add support in the kernel. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 104 ++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + include/hw/arm/smmuv3-accel.h | 2 + 3 files changed, 107 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 09be838d22..fb08e1d66b 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -15,6 +15,96 @@ =20 #include "smmuv3-internal.h" =20 +static int +smmuv3_accel_dev_get_info(SMMUv3AccelDevice *accel_dev, uint32_t *data_typ= e, + uint32_t data_len, void *data) +{ + uint64_t caps; + + if (!accel_dev || !accel_dev->idev) { + return -ENOENT; + } + + return !iommufd_backend_get_device_info(accel_dev->idev->iommufd, + accel_dev->idev->devid, + data_type, data, + data_len, &caps, NULL); +} + +static void smmuv3_accel_init_regs(SMMUv3AccelState *s_accel) +{ + SMMUv3State *s =3D ARM_SMMUV3(s_accel); + SMMUv3AccelDevice *accel_dev; + uint32_t data_type; + uint32_t val; + int ret; + + if (!s_accel->viommu || QLIST_EMPTY(&s_accel->viommu->device_list)) { + error_report("At least one cold-plugged vfio-pci is required for s= mmuv3-accel!"); + exit(1); + } + + accel_dev =3D QLIST_FIRST(&s_accel->viommu->device_list); + if (accel_dev->info.idr[0]) { + info_report("reusing the previous hw_info"); + goto out; + } + + ret =3D smmuv3_accel_dev_get_info(accel_dev, &data_type, + sizeof(accel_dev->info), &accel_dev->i= nfo); + if (ret) { + error_report("failed to get SMMU device info"); + return; + } + + if (data_type !=3D IOMMU_HW_INFO_TYPE_ARM_SMMUV3) { + error_report("Wrong data type (%d)!", data_type); + return; + } + +out: + trace_smmuv3_accel_get_device_info(accel_dev->info.idr[0], + accel_dev->info.idr[1], + accel_dev->info.idr[3], + accel_dev->info.idr[5]); + + val =3D FIELD_EX32(accel_dev->info.idr[0], IDR0, BTM); + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, BTM, val); + val =3D FIELD_EX32(accel_dev->info.idr[0], IDR0, ATS); + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, val); + val =3D FIELD_EX32(accel_dev->info.idr[0], IDR0, ASID16); + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ASID16, val); + val =3D FIELD_EX32(accel_dev->info.idr[0], IDR0, TERM_MODEL); + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, val); + val =3D FIELD_EX32(accel_dev->info.idr[0], IDR0, STALL_MODEL); + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, val); + val =3D FIELD_EX32(accel_dev->info.idr[0], IDR0, STLEVEL); + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STLEVEL, val); + + val =3D FIELD_EX32(accel_dev->info.idr[1], IDR1, SIDSIZE); + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SIDSIZE, val); + val =3D FIELD_EX32(accel_dev->info.idr[1], IDR1, SSIDSIZE); + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, val); + + val =3D FIELD_EX32(accel_dev->info.idr[3], IDR3, HAD); + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, HAD, val); + val =3D FIELD_EX32(accel_dev->info.idr[3], IDR3, RIL); + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, val); + val =3D FIELD_EX32(accel_dev->info.idr[3], IDR3, BBML); + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, BBML, val); + + val =3D FIELD_EX32(accel_dev->info.idr[5], IDR5, GRAN4K); + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, val); + val =3D FIELD_EX32(accel_dev->info.idr[5], IDR5, GRAN16K); + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, val); + val =3D FIELD_EX32(accel_dev->info.idr[5], IDR5, GRAN64K); + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, val); + val =3D FIELD_EX32(accel_dev->info.idr[5], IDR5, OAS); + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, val); + + /* FIXME check iidr and aidr registrs too */ +} + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *s, SMMUPciBus *s= bus, PCIBus *bus, int devfn) { @@ -484,11 +574,25 @@ static void smmu_accel_realize(DeviceState *d, Error = **errp) bs->unset_iommu_device =3D smmuv3_accel_unset_iommu_device; } =20 +static void smmuv3_accel_reset_hold(Object *obj, ResetType type) +{ + SMMUv3AccelState *s =3D ARM_SMMUV3_ACCEL(obj); + SMMUv3AccelClass *c =3D ARM_SMMUV3_ACCEL_GET_CLASS(s); + + if (c->parent_phases.hold) { + c->parent_phases.hold(obj, type); + } + smmuv3_accel_init_regs(s); +} + static void smmuv3_accel_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); SMMUv3AccelClass *c =3D ARM_SMMUV3_ACCEL_CLASS(klass); =20 + resettable_class_set_parent_phases(rc, NULL, smmuv3_accel_reset_hold, = NULL, + &c->parent_phases); device_class_set_parent_realize(dc, smmu_accel_realize, &c->parent_realize); dc->hotpluggable =3D false; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index cd2eac31c2..c7a7e58291 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -62,6 +62,7 @@ smmu_reset_exit(void) "" smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x" smmuv3_accel_install_nested_ste(uint32_t sid, uint64_t ste_1, uint64_t ste= _0) "sid=3D%d ste=3D%"PRIx64":%"PRIx64 +smmuv3_accel_get_device_info(uint32_t idr0, uint32_t idr1, uint32_t idr3, = uint32_t idr5) "idr0=3D0x%x idr1=3D0x%x idr3=3D0x%x idr5=3D0x%x" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h index 58e68534c0..9e30d7d351 100644 --- a/include/hw/arm/smmuv3-accel.h +++ b/include/hw/arm/smmuv3-accel.h @@ -52,6 +52,7 @@ typedef struct SMMUv3AccelDevice { SMMUViommu *viommu; SMMUVdev *vdev; AddressSpace as_sysmem; + struct iommu_hw_info_arm_smmuv3 info; QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; =20 @@ -68,6 +69,7 @@ struct SMMUv3AccelClass { /*< public >*/ =20 DeviceRealize parent_realize; + ResettablePhases parent_phases; }; =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702617; cv=none; d=zohomail.com; s=zohoarc; b=DUMAVBNL5bl87/bab6llkpRk0usVCh+WW4zten5a0ECANHtzZQGc2AVsuLU6PQc3eS6EAkKMnmcV8RD2IjuvAMrLz2Lpl0PcRhNZ+1mUecqh3sbBAcvlehmGEo5dIC5YITuX0YduTQhiuf8+xsYyvLtakj+WxftV6OLD7BbUBGs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741702617; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 11 Mar 2025 10:14:37 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwdD1rGQz6F9Cc; Tue, 11 Mar 2025 22:10:08 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id C95A8140D26; Tue, 11 Mar 2025 22:14:33 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:14:26 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 17/20] hw/arm/smmuv3: Check idr registers for STE_S1CDMAX and STE_S1STALLD Date: Tue, 11 Mar 2025 14:10:42 +0000 Message-ID: <20250311141045.66620-18-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702619115019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen With nested translation, the underlying HW could support those two fields. Allow them according to the updated idr registers after the hw_info ioctl. When substreams are enabled (S1CDMax !=3D 0), S1DSS field determines the behavior of a transaction. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 546f8faac0..530284a9c0 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -612,6 +612,7 @@ static inline void smmuv3_accel_install_nested_ste(SMMU= Device *sdev, int sid) =20 #define STE_S1FMT(x) extract32((x)->word[0], 4 , 2) #define STE_S1CDMAX(x) extract32((x)->word[1], 27, 5) +#define STE_S1DSS(x) extract32((x)->word[2], 0, 2) #define STE_S1STALLD(x) extract32((x)->word[2], 27, 1) #define STE_EATS(x) extract32((x)->word[2], 28, 2) #define STE_STRW(x) extract32((x)->word[2], 30, 2) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e0f225d0df..e8a6c50056 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -561,6 +561,16 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cf= g, =20 decode_ste_config(cfg, config); =20 + /* S1DSS.Terminate is same as Config.abort for default stream */ + if (STE_CFG_S1_ENABLED(config) && STE_S1DSS(ste) =3D=3D 0) { + cfg->aborted =3D true; + } + + /* S1DSS.Bypass is same as Config.bypass for default stream */ + if (STE_CFG_S1_ENABLED(config) && STE_S1DSS(ste) =3D=3D 0x1) { + cfg->bypassed =3D true; + } + if (cfg->aborted || cfg->bypassed) { return 0; } @@ -598,13 +608,14 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *c= fg, } } =20 - if (STE_S1CDMAX(ste) !=3D 0) { + if (!FIELD_EX32(s->idr[1], IDR1, SSIDSIZE) && STE_S1CDMAX(ste) !=3D 0)= { qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support multiple context descriptor= s yet\n"); goto bad_ste; } =20 - if (STE_S1STALLD(ste)) { + /* STALL_MODEL being 0b01 means "stall is not supported" */ + if ((FIELD_EX32(s->idr[0], IDR0, STALL_MODEL) & 0x1) && STE_S1STALLD(s= te)) { qemu_log_mask(LOG_UNIMP, "SMMUv3 S1 stalling fault model not allowed yet\n"); goto bad_ste; --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702549; cv=none; d=zohomail.com; s=zohoarc; b=PLNkn55TkSr0mERcfGm0m/xxRYIxxy836nXFMvve3Ts6s7B9+BjBZvFtMrGKGlJfgXpao9xh+pULC1MKRcZ+bg5zsP/xoYOOLzvtuwDBS/LMi39V8Z612IWc427kdClGvxM0jAfA6D0/vML2bLPHMLOU94AN2WA4TMwfUVABW1U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741702549; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=G5z5zixkeY9kaY2v/YD+76iMvMlnGLuYBMP/HFXOIvY=; b=QXY+MMHu2yvaiHgheXjhr4CfEEqzXyeyGPlAx5/ewfVaaypawwBUSILqLSQfOjvMYuEZnvpwc8Z6g5hD8RVD/9Y+1UwrfBRHNNxdbMp/n+w/lWRCnLOrl90/AKU/84cacG75UE1yMu7o6AYRwpzpNGwLFjdZfCLRjpSNqtv/XBk= ARC-Authentication-Results: i=1; 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Tue, 11 Mar 2025 22:11:36 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 7D2B71404F5; Tue, 11 Mar 2025 22:14:43 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:14:36 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 18/20] hw/arm/smmu-common: Bypass emulated IOTLB for a accel SMMUv3 Date: Tue, 11 Mar 2025 14:10:43 +0000 Message-ID: <20250311141045.66620-19-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702558697019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen If a vSMMU is configured as a accelerated one, HW IOTLB will be used and all cache invalidation should be done to the HW IOTLB too, v.s. the emulated iotlb. In this case, an iommu notifier isn't registered, as the devices behind a SMMUv3-accel would stay in the system address space for stage-2 mappings. However, the KVM code still requests an iommu address space to translate an MSI doorbell gIOVA via get_msi_address_space() and translate(). Since a SMMUv3-accel doesn't register an iommu notifier to flush emulated iotlb, bypass the emulated IOTLB and always walk through the guest-level IO page table. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmu-common.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 9fd455baa0..fd10df8866 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -77,6 +77,17 @@ static SMMUTLBEntry *smmu_iotlb_lookup_all_levels(SMMUSt= ate *bs, uint8_t level =3D 4 - (inputsize - 4) / stride; SMMUTLBEntry *entry =3D NULL; =20 + /* + * Stage-1 translation with a accel SMMU in general uses HW IOTLB. How= ever, + * KVM still requests for an iommu address space for an MSI fixup by l= ooking + * up stage-1 page table. Make sure we don't go through the emulated p= athway + * so that the emulated iotlb will not need any invalidation. + */ + + if (bs->accel) { + return NULL; + } + while (level <=3D 3) { uint64_t subpage_size =3D 1ULL << level_shift(level, tt->granule_s= z); uint64_t mask =3D subpage_size - 1; @@ -142,6 +153,16 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cf= g, SMMUTLBEntry *new) SMMUIOTLBKey *key =3D g_new0(SMMUIOTLBKey, 1); uint8_t tg =3D (new->granule - 10) / 2; =20 + /* + * Stage-1 translation with a accel SMMU in general uses HW IOTLB. How= ever, + * KVM still requests for an iommu address space for an MSI fixup by l= ooking + * up stage-1 page table. Make sure we don't go through the emulated p= athway + * so that the emulated iotlb will not need any invalidation. + */ + if (bs->accel) { + return; + } + if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { smmu_iotlb_inv_all(bs); } --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702582; cv=none; d=zohomail.com; s=zohoarc; b=Qb9mwpBaOBTG7yfIpOmBkHSCLGe9ncrOxjgpuwJVKvnVFLNNvLsAl5Qef3o5S1gNguohL8Dr8+MsMAZ3QEkCjjO6VSZ/G/nxOaIu1KTTU4U8bnwjNytn72FcwMk2zVzMZOgqFRpMwdMSKaFljEzP217EKqX3Bkvp2CH/WSygG5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741702582; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=V+M/yDx9N2sYsh5+HxsTqs7QHJDX8m5rj1i79V2AmEk=; b=iRqFRKpX2lghOwg4+XIC/6aYU8t0DGUmqHtidULxx0K20piUkX0gKirsUkGoTC9jJ2l7Uon10pdBgLzu0gv9jiD+Zmwv9whCXjbPt+v633PuBGQfyFFnj+7WagIf4S4oqTzQdlPI0LxT8/B4MTUkN18gK4J0PW2/IssEebz/tTY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741702582838271.71634701342464; Tue, 11 Mar 2025 07:16:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ts0OI-0002wE-14; Tue, 11 Mar 2025 10:15:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Nm-0002UM-AR; Tue, 11 Mar 2025 10:15:05 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Nj-0007IC-5O; Tue, 11 Mar 2025 10:14:58 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwg63KRZz6D9ln; Tue, 11 Mar 2025 22:11:46 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 526471404F5; Tue, 11 Mar 2025 22:14:53 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:14:46 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 19/20] hw/arm/virt-acpi-build: Update IORT with multiple smmuv3-accel nodes Date: Tue, 11 Mar 2025 14:10:44 +0000 Message-ID: <20250311141045.66620-20-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702584271019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that we can have multiple user-creatable smmuv3-accel devices, each associated with different pci buses, update IORT ID mappings accordingly. Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 113 +++++++++++++++++++++++++++++++++------ 1 file changed, 97 insertions(+), 16 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3ac8f8e178..c232850e36 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -43,6 +43,7 @@ #include "hw/acpi/generic_event_device.h" #include "hw/acpi/tpm.h" #include "hw/acpi/hmat.h" +#include "hw/arm/smmuv3-accel.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -233,6 +234,51 @@ struct AcpiIortIdMapping { }; typedef struct AcpiIortIdMapping AcpiIortIdMapping; =20 +struct SMMUv3Accel { + int irq; + hwaddr base; + AcpiIortIdMapping smmu_idmap; +}; +typedef struct SMMUv3Accel SMMUv3Accel; + +static int smmuv3_accel_idmap_compare(gconstpointer a, gconstpointer b) +{ + SMMUv3Accel *accel_a =3D (SMMUv3Accel *)a; + SMMUv3Accel *accel_b =3D (SMMUv3Accel *)b; + + return accel_a->smmu_idmap.input_base - accel_b->smmu_idmap.input_base; +} + +static int get_smmuv3_accel(Object *obj, void *opaque) +{ + GArray *s_accel_blob =3D opaque; + + if (object_dynamic_cast(obj, TYPE_ARM_SMMUV3_ACCEL)) { + PCIBus *bus =3D (PCIBus *) object_property_get_link(obj, "primary-= bus", + &error_abort); + if (bus && !pci_bus_bypass_iommu(bus)) { + SMMUv3Accel accel; + int min_bus, max_bus; + VirtMachineState *v =3D VIRT_MACHINE(qdev_get_machine()); + PlatformBusDevice *pbus =3D PLATFORM_BUS_DEVICE(v->platform_bu= s_dev); + SysBusDevice *sbdev =3D SYS_BUS_DEVICE(obj); + hwaddr base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + int irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + + base +=3D v->memmap[VIRT_PLATFORM_BUS].base; + irq +=3D v->irqmap[VIRT_PLATFORM_BUS]; + + pci_bus_range(bus, &min_bus, &max_bus); + accel.smmu_idmap.input_base =3D min_bus << 8; + accel.smmu_idmap.id_count =3D (max_bus - min_bus + 1) << 8; + accel.base =3D base; + accel.irq =3D irq + ARM_SPI_BASE; + g_array_append_val(s_accel_blob, accel); + } + } + return 0; +} + /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ static int iort_host_bridges(Object *obj, void *opaque) @@ -275,30 +321,51 @@ static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { int i, nb_nodes, rc_mapping_count; - size_t node_size, smmu_offset =3D 0; + size_t node_size, *smmu_offset =3D NULL; AcpiIortIdMapping *idmap; + SMMUv3Accel *accel; + int num_smmus =3D 0; uint32_t id =3D 0; GArray *smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); GArray *its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMappi= ng)); + GArray *smmuv3_accel =3D g_array_new(false, true, sizeof(SMMUv3Accel)); =20 AcpiTable table =3D { .sig =3D "IORT", .rev =3D 3, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; /* Table 2 The IORT */ acpi_table_begin(&table, table_data); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - AcpiIortIdMapping next_range =3D {0}; - + nb_nodes =3D 2; /* RC, ITS */ + if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3_ACCEL) { + object_child_foreach_recursive(object_get_root(), + get_smmuv3_accel, smmuv3_accel); + /* Sort the smmuv3-accel by smmu idmap input_base */ + g_array_sort(smmuv3_accel, smmuv3_accel_idmap_compare); + + /* Fill smmu idmap from sorted accel array */ + for (i =3D 0; i < smmuv3_accel->len; i++) { + accel =3D &g_array_index(smmuv3_accel, SMMUv3Accel, i); + g_array_append_val(smmu_idmaps, accel->smmu_idmap); + } + num_smmus =3D smmuv3_accel->len; + } else if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { object_child_foreach_recursive(object_get_root(), iort_host_bridges, smmu_idmaps); =20 /* Sort the smmu idmap by input_base */ g_array_sort(smmu_idmaps, iort_idmap_compare); + num_smmus =3D 1; + } =20 - /* - * Split the whole RIDs by mapping from RC to SMMU, - * build the ID mapping from RC to ITS directly. - */ + /* + * Split the whole RIDs by mapping from RC to SMMU, + * build the ID mapping from RC to ITS directly. + */ + if (num_smmus) { + AcpiIortIdMapping next_range =3D {0}; + + smmu_offset =3D g_new0(size_t, num_smmus); + nb_nodes +=3D num_smmus; for (i =3D 0; i < smmu_idmaps->len; i++) { idmap =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); =20 @@ -316,10 +383,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) g_array_append_val(its_idmaps, next_range); } =20 - nb_nodes =3D 3; /* RC, ITS, SMMUv3 */ rc_mapping_count =3D smmu_idmaps->len + its_idmaps->len; } else { - nb_nodes =3D 2; /* RC, ITS */ rc_mapping_count =3D 1; } /* Number of IORT Nodes */ @@ -341,10 +406,19 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) /* GIC ITS Identifier Array */ build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + for (i =3D 0; i < num_smmus; i++) { + hwaddr base; + int irq; + if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3_ACCEL) { + accel =3D &g_array_index(smmuv3_accel, SMMUv3Accel, i); + base =3D accel->base; + irq =3D accel->irq; + } else { + base =3D vms->memmap[VIRT_SMMU].base; + irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + } =20 - smmu_offset =3D table_data->len - table.table_offset; + smmu_offset[i] =3D table_data->len - table.table_offset; /* Table 9 SMMUv3 Format */ build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type = */ node_size =3D SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; @@ -355,7 +429,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Reference to ID Array */ build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); /* Base address */ - build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base,= 8); + build_append_int_noprefix(table_data, base, 8); /* Flags */ build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ @@ -404,15 +478,22 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 /* Output Reference */ - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { + if (num_smmus) { AcpiIortIdMapping *range; + size_t offset; =20 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ for (i =3D 0; i < smmu_idmaps->len; i++) { + if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3_ACCEL) { + offset =3D smmu_offset[i]; + } else { + offset =3D smmu_offset[0]; + } + range =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); /* output IORT node is the smmuv3 node */ build_iort_id_mapping(table_data, range->input_base, - range->id_count, smmu_offset); + range->id_count, offset); } =20 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ --=20 2.34.1 From nobody Sun Apr 6 06:02:29 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741702577; cv=none; d=zohomail.com; s=zohoarc; b=egJe/GyfhIpvXXS0EeYk7UOFkBzRHoy9SckC9sPKqooEcN44Gx24ZZDQOiz0F4Uh6mfvEN8tVq3TyMEGC8mL96P/h3U3vuZshWJpwszYtNeURE9963pprVWnkH6EtQTQD+5N8XbVfpGYmTLlnbgnnsUAvqJV62AesJBz5nx8/tg= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741702578239019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index fb08e1d66b..812f8e358f 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -595,6 +595,7 @@ static void smmuv3_accel_class_init(ObjectClass *klass,= void *data) &c->parent_phases); device_class_set_parent_realize(dc, smmu_accel_realize, &c->parent_realize); + dc->user_creatable =3D true; dc->hotpluggable =3D false; dc->bus_type =3D TYPE_PCIE_BUS; } --=20 2.34.1