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Tue, 11 Mar 2025 05:59:15 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org Subject: [PULL 14/72] ppc/pnv/occ: Add POWER10 OCC-OPAL data format Date: Tue, 11 Mar 2025 22:57:08 +1000 Message-ID: <20250311125815.903177-15-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250311125815.903177-1-npiggin@gmail.com> References: <20250311125815.903177-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=npiggin@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1741698040170019100 Content-Type: text/plain; charset="utf-8" Add POWER10 OCC-OPAL data format. POWER10 changes major version and adds a few fields. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_occ.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 19ccfe1bbf..34decb1700 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -263,14 +263,20 @@ static const TypeInfo pnv_occ_power9_type_info =3D { =20 static void pnv_occ_power10_class_init(ObjectClass *klass, void *data) { + PnvOCCClass *poc =3D PNV_OCC_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->desc =3D "PowerNV OCC Controller (POWER10)"; + poc->opal_shared_memory_offset =3D P9_HOMER_OPAL_DATA_OFFSET; + poc->opal_shared_memory_version =3D 0xA0; + poc->xscom_size =3D PNV9_XSCOM_OCC_SIZE; + poc->xscom_ops =3D &pnv_occ_power9_xscom_ops; + assert(!dc->user_creatable); } =20 static const TypeInfo pnv_occ_power10_type_info =3D { .name =3D TYPE_PNV10_OCC, - .parent =3D TYPE_PNV9_OCC, + .parent =3D TYPE_PNV_OCC, .class_init =3D pnv_occ_power10_class_init, }; =20 @@ -711,6 +717,37 @@ static bool occ_init_homer_memory(PnvOCC *occ, Error *= *errp) static_data.v9.core_max[i] =3D 1; } break; + case 0xA0: + if (chip->chip_id =3D=3D 0) { + static_data.v10.occ_role =3D OCC_ROLE_MASTER; + } else { + static_data.v10.occ_role =3D OCC_ROLE_SLAVE; + } + static_data.v10.pstate_min =3D 4; + static_data.v10.pstate_fixed_freq =3D 3; + static_data.v10.pstate_base =3D 2; + static_data.v10.pstate_ultra_turbo =3D 0; + static_data.v10.pstate_fmax =3D 1; + static_data.v10.minor =3D 0x01; + static_data.v10.pstates[0].valid =3D 1; + static_data.v10.pstates[0].id =3D 0; + static_data.v10.pstates[0].freq_khz =3D cpu_to_be32(4200000); + static_data.v10.pstates[1].valid =3D 1; + static_data.v10.pstates[1].id =3D 1; + static_data.v10.pstates[1].freq_khz =3D cpu_to_be32(4000000); + static_data.v10.pstates[2].valid =3D 1; + static_data.v10.pstates[2].id =3D 2; + static_data.v10.pstates[2].freq_khz =3D cpu_to_be32(3800000); + static_data.v10.pstates[3].valid =3D 1; + static_data.v10.pstates[3].id =3D 3; + static_data.v10.pstates[3].freq_khz =3D cpu_to_be32(3000000); + static_data.v10.pstates[4].valid =3D 1; + static_data.v10.pstates[4].id =3D 4; + static_data.v10.pstates[4].freq_khz =3D cpu_to_be32(2000000); + for (i =3D 0; i < chip->nr_cores; i++) { + static_data.v10.core_max[i] =3D 1; + } + break; default: g_assert_not_reached(); } @@ -726,6 +763,10 @@ static bool occ_init_homer_memory(PnvOCC *occ, Error *= *errp) dynamic_data.cur_pwr_cap =3D cpu_to_be16(PCAP_MAX_POWER_W); dynamic_data.soft_min_pwr_cap =3D cpu_to_be16(PCAP_SOFT_MIN_POWER_W); switch (poc->opal_shared_memory_version) { + case 0xA0: + dynamic_data.minor_version =3D 0x1; + dynamic_data.v10.wof_enabled =3D 0x1; + break; case 0x90: dynamic_data.minor_version =3D 0x1; break; --=20 2.47.1