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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfad7sm13082199f8f.26.2025.03.09.17.06.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:06:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741565210; x=1742170010; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vtO10CroBFmuxTQ9PueWoinPmmKwM9K54hdlvVGKzAE=; b=BCNszlUosgkoC0FflU7TUIVgnJwJEjU70ZlfSChey97FnYKWjbcnJp9hHIL7ob7nCj i3IIeLieE4oX0uMr/tR6xKqrxucI0mHWiptKlx2P4SoAa6aYa+DW3CJYgAU7fkwRGrwq TThsrhVIgN69nP4V6ibRomM4QQPJodZptrrHN5oaD+vLuDft+xl3cQGvtltjLPWJD/8D 4FJZbDIFhefL9f9wkJ1IwcGJ2YQUi1CRkh0vxOcEJWfpHxpaeAy/WI/c9wfyKkATciTa kir5AylEdZqfTzw81u3jKHDTMX7FfbAryDFpHZsuFph6C5zx2frdD/YwGMfN0X0Glnu0 240w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741565210; x=1742170010; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vtO10CroBFmuxTQ9PueWoinPmmKwM9K54hdlvVGKzAE=; b=Ks9Z7fe326/AvMZOP6yZcLTjb3LxGOxJpIQ82mDESE9ZGlThwqvV1IfFZO1p/vofD9 IhqjwqQlJoViqWiZWMZX8bbApo0jjOdxU2rhDApsft7KGCyKjV4kLFW8BT9FRyYfbjkv VDS0SKoPY9bPXsbUWXJjZNGOvjIl+x0U7s7u7UYaluFAvFs6WsYaB8dz93PvVWfNXkcO q+08uHkwDTAAr4lJK++AXTL7dEmilKv2XxkPtfoYjZT11gqJnZrnYr8lW54UovBWACZB gQCOWkgH4nozmgH125AVW2ZUak++mh/Fkuwem4rOau4CcyuC1hApxwRY/nGn0vRYXFN9 /mYA== X-Forwarded-Encrypted: i=1; AJvYcCVbtRvJRNMX2N8rEwqFHlcRrUF2ifXNW80/qlongrwqZN6YZdI9pUBYPZExMjGFdWQNHICmPm9pODsW@nongnu.org X-Gm-Message-State: AOJu0Yw0LqRsY5kTK6m2HX5GZMOLgrSMloG2bxAvSjwGum6DOKYQ09TQ 3Ck6JVz8fCcIWa43RzZ2XF2tB2+tgZ21rYKIDv1SH0UwTBMaEN8QHf/UZOdt+yjbvpj7o1Id5uq MsFc= X-Gm-Gg: ASbGncsJs6lec8ETNJ81Rtppni3DZ456pQZvcIU/xCEtyH99bgSrdBMd5RySZjoFesh h6esMn1qTTY4rCbVKUT3iKYPjNIcBUpMxhdSV8NPJGtFeYvUCiQUQBcQf2E22UiSK1XX994RJb0 ClqRFaZHtgoZhy7mk9qBtSrRMDERcJtXQIvuBSbbEOpOhDjQZ6ux3RBbS9VnrKa+1iMpWeCp5Kb fp37DDHbp99dkjCqzmHAYsBepdwwtLCq5YHPm+DMuCn+9mbpIKCU5u8ab68Ezmr9nMUi+JT/HOH Op9dUkRP6pd8IoVTQa3Kr6/95NA8IisqTDqVPzjzT/OjqAu+ATycyNKZbs0yKuMfQH3CRB9H7Fh 9bnxHbtVCXMtvbcj/FAE= X-Google-Smtp-Source: AGHT+IFhNGrH+72dBBuvE39rw4Xrbpi7OKmGDcXtRHzlYrrJp2PqWtacezAZubHFNdsjwdLBS5eItw== X-Received: by 2002:a05:600c:3ba1:b0:43c:fbbf:7bf1 with SMTP id 5b1f17b1804b1-43cfbbf7eb2mr1844265e9.30.1741565210286; Sun, 09 Mar 2025 17:06:50 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 05/14] hw/sd/sdhci: Include 'pending-insert-quirk' property in quirk bitmask Date: Mon, 10 Mar 2025 01:06:11 +0100 Message-ID: <20250310000620.70120-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741565310067019100 Import Linux's SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET quirk definition. Replace 'pending_insert_quirk' boolean (originally introduce in commit 0a7ac9f9e72 "sdhci: quirk property for card insert interrupt status on Raspberry Pi") by a bit in quirk bitmask. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/sd/sdhci.h | 5 ++++- hw/sd/sdhci.c | 8 ++++---- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index d2e4f0f0050..2e6e719df7b 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -34,6 +34,8 @@ * SD/MMC host controller state * * QEMU interface: + * + QOM property "pending-insert-quirk" re-enables pending "card inserte= d" + * IRQ after reset (used by the Raspberry Pi controllers). * + QOM property "wp-inverted-quirk" inverts the Write Protect pin * polarity (by default the polarity is active low for detecting SD * card to be protected). @@ -101,7 +103,6 @@ struct SDHCIState { /* RO Host Controller Version Register always reads as 0x2401 */ =20 /* Configurable properties */ - bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */ uint32_t quirks; uint8_t endianness; uint8_t sd_spec_version; @@ -118,6 +119,8 @@ enum { SDHCI_QUIRK_NO_BUSY_IRQ =3D 14, /* Controller reports inverted write-protect state */ SDHCI_QUIRK_INVERTED_WRITE_PROTECT =3D 16, + /* Controller losing signal/interrupt enable states after reset */ + SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET =3D 19, }; =20 #define TYPE_PCI_SDHCI "sdhci-pci" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 19c600d5bfc..d1b1b187874 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -320,7 +320,7 @@ static void sdhci_poweron_reset(DeviceState *dev) =20 sdhci_reset(s); =20 - if (s->pending_insert_quirk) { + if (s->quirks & BIT(SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)) { s->pending_insert_state =3D true; } } @@ -1307,7 +1307,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val= , unsigned size) * appears when first enabled after power on */ if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_stat= e) { - assert(s->pending_insert_quirk); + assert(s->quirks & BIT(SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)); s->norintsts |=3D SDHC_NIS_INSERT; s->pending_insert_state =3D false; } @@ -1557,8 +1557,8 @@ static const Property sdhci_sysbus_properties[] =3D { DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), DEFINE_PROP_BIT("wp-inverted-quirk", SDHCIState, quirks, SDHCI_QUIRK_INVERTED_WRITE_PROTECT, false), - DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_qu= irk, - false), + DEFINE_PROP_BIT("pending-insert-quirk", SDHCIState, quirks, + SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET, false), DEFINE_PROP_LINK("dma", SDHCIState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), }; --=20 2.47.1