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From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 08/38] accel: Prefer cached CpuClass over CPU_GET_CLASS() macro
Date: Sun, 9 Mar 2025 18:51:37 +0100
Message-ID: <20250309175207.43828-9-philmd@linaro.org>
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CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250122093028.52416-6-philmd@linaro.org>
---
accel/accel-target.c | 12 +++++-------
accel/tcg/tcg-accel-ops.c | 3 +--
accel/tcg/translate-all.c | 2 +-
accel/tcg/watchpoint.c | 9 ++++-----
4 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/accel/accel-target.c b/accel/accel-target.c
index 83587274626..33a539b4cbb 100644
--- a/accel/accel-target.c
+++ b/accel/accel-target.c
@@ -113,22 +113,20 @@ void accel_init_interfaces(AccelClass *ac)
=20
void accel_cpu_instance_init(CPUState *cpu)
{
- CPUClass *cc =3D CPU_GET_CLASS(cpu);
-
- if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) {
- cc->accel_cpu->cpu_instance_init(cpu);
+ if (cpu->cc->accel_cpu && cpu->cc->accel_cpu->cpu_instance_init) {
+ cpu->cc->accel_cpu->cpu_instance_init(cpu);
}
}
=20
bool accel_cpu_common_realize(CPUState *cpu, Error **errp)
{
- CPUClass *cc =3D CPU_GET_CLASS(cpu);
AccelState *accel =3D current_accel();
AccelClass *acc =3D ACCEL_GET_CLASS(accel);
=20
/* target specific realization */
- if (cc->accel_cpu && cc->accel_cpu->cpu_target_realize
- && !cc->accel_cpu->cpu_target_realize(cpu, errp)) {
+ if (cpu->cc->accel_cpu
+ && cpu->cc->accel_cpu->cpu_target_realize
+ && !cpu->cc->accel_cpu->cpu_target_realize(cpu, errp)) {
return false;
}
=20
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 53e580d128b..d9b662efe3b 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -121,10 +121,9 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdb=
type)
[GDB_WATCHPOINT_ACCESS] =3D BP_GDB | BP_MEM_ACCESS,
};
=20
- CPUClass *cc =3D CPU_GET_CLASS(cpu);
int cputype =3D xlat[gdbtype];
=20
- if (cc->gdb_stop_before_watchpoint) {
+ if (cpu->cc->gdb_stop_before_watchpoint) {
cputype |=3D BP_STOP_BEFORE_ACCESS;
}
return cputype;
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 0914d6e98b2..82bc16bd535 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -630,7 +630,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
* to account for the re-execution of the branch.
*/
n =3D 1;
- cc =3D CPU_GET_CLASS(cpu);
+ cc =3D cpu->cc;
if (cc->tcg_ops->io_recompile_replay_branch &&
cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) {
cpu->neg.icount_decr.u16.low++;
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
index ba8c9859cf4..65b21884cec 100644
--- a/accel/tcg/watchpoint.c
+++ b/accel/tcg/watchpoint.c
@@ -68,7 +68,6 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr a=
ddr, vaddr len)
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
MemTxAttrs attrs, int flags, uintptr_t ra)
{
- CPUClass *cc =3D CPU_GET_CLASS(cpu);
CPUWatchpoint *wp;
=20
assert(tcg_enabled());
@@ -84,9 +83,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vadd=
r len,
return;
}
=20
- if (cc->tcg_ops->adjust_watchpoint_address) {
+ if (cpu->cc->tcg_ops->adjust_watchpoint_address) {
/* this is currently used only by ARM BE32 */
- addr =3D cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
+ addr =3D cpu->cc->tcg_ops->adjust_watchpoint_address(cpu, addr, le=
n);
}
=20
assert((flags & ~BP_MEM_ACCESS) =3D=3D 0);
@@ -118,8 +117,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va=
ddr len,
wp->hitattrs =3D attrs;
=20
if (wp->flags & BP_CPU
- && cc->tcg_ops->debug_check_watchpoint
- && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
+ && cpu->cc->tcg_ops->debug_check_watchpoint
+ && !cpu->cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
wp->flags &=3D ~BP_WATCHPOINT_HIT;
continue;
}
--=20
2.47.1