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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ceaac390bsm53503015e9.35.2025.03.09.10.53.32 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 10:53:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741542813; x=1742147613; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CR9qHcPdMx1za2MutCx4NKVWEwgwRQ/k65jZmcbEmWI=; b=eV8Ae0rlDpAun0EPpM/DJ6KtikB2IfP08Uvf12VmXFmjQuxX+l6+gKScXecqtWK5Cr aV7WyYYJAKIyzu/qeeKg1n1rbUWhB5NldD29014J0XEtZQxeVHW+blbZku40RmP/A6Ud yPQ2dBSk8Ufl2L6bM4tIq3IHlHLCkxqiTxpOzUq5LFpXPa1EFieJy623lR+Trb7/Uzsq Z3jbyk5t/a2Wx1KpyDxQPT+MN3kSTIS30LkiSMTwMAj5UsJ/iZJKuNpf2tR0qTFUS0Uh Fx5lzuotGHKcFBncywR4LRcyb0FaMDs9VbxcBw+PGXIvLKp2MefBJ/LMWepe1cyGPF84 aa1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741542813; x=1742147613; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CR9qHcPdMx1za2MutCx4NKVWEwgwRQ/k65jZmcbEmWI=; b=ewqsJPofsZS96dPNY77J4u0cnquEjygXV/qZE5iXChMlhSNc+FxjNz0qst78d94Urg tYbPLQs1cxslEfOZ87rRb+nhsecJif1sr3e+yGDbgGQ00XWRBqvomU211/Tkjic7LH1h vPj5FM9OFwelRmo1bzPKQdvtOp+DBwmwnrcwe45JIxt8AsXKKrbKoMp5GvBdLKW0sMC+ 7RTFbSgMmvvqjd+ZUloxUQ+rw3UMRlOy7xkp7LZzuFtYGKuoyYBAkEjSydL3BqCbJhCw ErUiQJo+5iBelrEoDJX6eLQosqNDMJ2zNYnkE2dtSAsyBAXEypJScTkRzF1vWXDh9JT5 4f7g== X-Gm-Message-State: AOJu0Yy0UtzpVIC7TLSdvxb/F0JFkPap90zUIwPGtZ8AwW4fO4blVKld YZKp2UxIeEbFZ5aPgjAJ6WiGHatwhAYcrP6JnBqBUgEeOQjwf7CwZfaCmMwcIOplClXiAR7WhW1 r+Kw= X-Gm-Gg: ASbGncvh7iXDGo8L9gY+JXGaULsVZvXpVIMRIm9CM7ZSstuhp/X8QHNWbLNLJsil1XV WBxHoCSPUr8AwG+IfiwmNTJeNx8ivM3wC71CQWW3vNJXV3UtWP0d2Fcvm93qIlSLCHirSIX2KJT 30wrZKZ2scLXpxT7yagktPltvAMfwiUbamL/paOYgQql6CIAresYGChAgbA8kE+3W9KxytZUtJ4 gldme+Rg0iwO9eaGbDm+QkzFxBO11h5d2w3aK3xN5hZOCQ1VmaqVSN7KBaQsPjoHLimNHVVkc/Y lOBD+oZ1E3kimNkpEDDDW4O81e26p3XCrXGVk3vsVXN6o4jHYjROu6z/cLonKH8+wDsKBmQ/oqJ p+fr2z0M2DSrhn8Tjfqk= X-Google-Smtp-Source: AGHT+IH2f+EX/rt4pFnmHBWq6sWTKZFfrwVOJ/0JNg6e3IbZpBAm/xM7owoDljZEb3LnPSvIaKy8tQ== X-Received: by 2002:a5d:5987:0:b0:391:2bab:d2fd with SMTP id ffacd0b85a97d-39132da96c9mr6963404f8f.37.1741542812830; Sun, 09 Mar 2025 10:53:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 18/38] target/arm: Move has_work() from CPUClass to SysemuCPUOps Date: Sun, 9 Mar 2025 18:51:47 +0100 Message-ID: <20250309175207.43828-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250309175207.43828-1-philmd@linaro.org> References: <20250309175207.43828-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741542861665019100 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20250125170125.32855-6-philmd@linaro.org> --- target/arm/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d7e61d08bbb..01786ac7879 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -123,6 +123,7 @@ void arm_restore_state_to_opc(CPUState *cs, } #endif /* CONFIG_TCG */ =20 +#ifndef CONFIG_USER_ONLY /* * With SCTLR_ELx.NMI =3D=3D 0, IRQ with Superpriority is masked identical= ly with * IRQ without Superpriority. Moreover, if the GIC is configured so that @@ -141,6 +142,7 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } +#endif /* !CONFIG_USER_ONLY */ =20 static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) { @@ -2655,6 +2657,7 @@ static const gchar *arm_gdb_arch_name(CPUState *cs) #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps arm_sysemu_ops =3D { + .has_work =3D arm_cpu_has_work, .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, @@ -2705,7 +2708,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) &acc->parent_phases); =20 cc->class_by_name =3D arm_cpu_class_by_name; - cc->has_work =3D arm_cpu_has_work; cc->mmu_index =3D arm_cpu_mmu_index; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; --=20 2.47.1