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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1741528397; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lY/mgkz7UKbtun2cufg6h3yp/eLSgCuByf8NHRBx48M=; b=DJEXSXqOjABfR6hG4/4tPHdnXQ0QoVGQJVsFwpufjQP5kk2gUPKZh+Mou7KNVqkXhPXStA aLmrjFUXB7FhftqftT7vFBxepdDjGDmUXAZLm9yzINYXgl1wwjXkQsgjiNQ8oauoBC6WRo 8T4fqT5rzsffyKQXDoPI6+dt33505Dk= X-MC-Unique: HoPlnY55N2mTQ43_Vz7RuA-1 X-Mimecast-MFC-AGG-ID: HoPlnY55N2mTQ43_Vz7RuA_1741528393 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 39/46] hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1 Date: Sun, 9 Mar 2025 14:51:23 +0100 Message-ID: <20250309135130.545764-40-clg@redhat.com> In-Reply-To: <20250309135130.545764-1-clg@redhat.com> References: <20250309135130.545764-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1741528519209019100 From: Jamin Lin The memory map for AST2700 A1 remains compatible with AST2700 A0. However, = the IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1. Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-23-jamin_li= n@aspeedtech.com [ clg: Removed sc->name ] Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 79 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 8ed57d23ef1c..682ab9bf8a38 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -120,6 +120,52 @@ static const int aspeed_soc_ast2700a0_irqmap[] =3D { [ASPEED_DEV_SDHCI] =3D 133, }; =20 +static const int aspeed_soc_ast2700a1_irqmap[] =3D { + [ASPEED_DEV_SDMC] =3D 0, + [ASPEED_DEV_HACE] =3D 4, + [ASPEED_DEV_XDMA] =3D 5, + [ASPEED_DEV_UART4] =3D 8, + [ASPEED_DEV_SCU] =3D 12, + [ASPEED_DEV_RTC] =3D 13, + [ASPEED_DEV_EMMC] =3D 15, + [ASPEED_DEV_TIMER1] =3D 16, + [ASPEED_DEV_TIMER2] =3D 17, + [ASPEED_DEV_TIMER3] =3D 18, + [ASPEED_DEV_TIMER4] =3D 19, + [ASPEED_DEV_TIMER5] =3D 20, + [ASPEED_DEV_TIMER6] =3D 21, + [ASPEED_DEV_TIMER7] =3D 22, + [ASPEED_DEV_TIMER8] =3D 23, + [ASPEED_DEV_DP] =3D 28, + [ASPEED_DEV_LPC] =3D 192, + [ASPEED_DEV_IBT] =3D 192, + [ASPEED_DEV_KCS] =3D 192, + [ASPEED_DEV_I2C] =3D 194, + [ASPEED_DEV_ADC] =3D 194, + [ASPEED_DEV_GPIO] =3D 194, + [ASPEED_DEV_FMC] =3D 195, + [ASPEED_DEV_WDT] =3D 195, + [ASPEED_DEV_PWM] =3D 195, + [ASPEED_DEV_I3C] =3D 195, + [ASPEED_DEV_UART0] =3D 196, + [ASPEED_DEV_UART1] =3D 196, + [ASPEED_DEV_UART2] =3D 196, + [ASPEED_DEV_UART3] =3D 196, + [ASPEED_DEV_UART5] =3D 196, + [ASPEED_DEV_UART6] =3D 196, + [ASPEED_DEV_UART7] =3D 196, + [ASPEED_DEV_UART8] =3D 196, + [ASPEED_DEV_UART9] =3D 196, + [ASPEED_DEV_UART10] =3D 196, + [ASPEED_DEV_UART11] =3D 196, + [ASPEED_DEV_UART12] =3D 196, + [ASPEED_DEV_ETH1] =3D 196, + [ASPEED_DEV_ETH2] =3D 196, + [ASPEED_DEV_ETH3] =3D 196, + [ASPEED_DEV_PECI] =3D 197, + [ASPEED_DEV_SDHCI] =3D 197, +}; + /* GICINT 128 */ /* GICINT 192 */ static const int ast2700_gic128_gic192_intcmap[] =3D { @@ -864,6 +910,33 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClas= s *oc, void *data) sc->get_irq =3D aspeed_soc_ast2700_get_irq; } =20 +static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, void *data) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a35"), + NULL + }; + DeviceClass *dc =3D DEVICE_CLASS(oc); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); + + /* Reason: The Aspeed SoC can only be instantiated from a board */ + dc->user_creatable =3D false; + dc->realize =3D aspeed_soc_ast2700_realize; + + sc->valid_cpu_types =3D valid_cpu_types; + sc->silicon_rev =3D AST2700_A1_SILICON_REV; + sc->sram_size =3D 0x20000; + sc->spis_num =3D 3; + sc->wdts_num =3D 8; + sc->macs_num =3D 3; + sc->uarts_num =3D 13; + sc->num_cpus =3D 4; + sc->uarts_base =3D ASPEED_DEV_UART0; + sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; + sc->memmap =3D aspeed_soc_ast2700_memmap; + sc->get_irq =3D aspeed_soc_ast2700_get_irq; +} + static const TypeInfo aspeed_soc_ast27x0_types[] =3D { { .name =3D TYPE_ASPEED27X0_SOC, @@ -876,6 +949,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[] =3D { .instance_init =3D aspeed_soc_ast2700_init, .class_init =3D aspeed_soc_ast2700a0_class_init, }, + { + .name =3D "ast2700-a1", + .parent =3D TYPE_ASPEED27X0_SOC, + .instance_init =3D aspeed_soc_ast2700_init, + .class_init =3D aspeed_soc_ast2700a1_class_init, + }, }; =20 DEFINE_TYPES(aspeed_soc_ast27x0_types) --=20 2.48.1