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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1741528373; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0TeyI2ZvNoOQ+1/3m4h1/bu3rnf8Ko87ZNeYweXrzg0=; b=UCwZdj80/5c43NfF8jhUT2Ug34fP31nK2NkSoa5BgkGsF9f9aIxqULXyISVh1SeSXU/WXi fj3oEHZviOKaxCJ3ROBLXfvNPvCyCErZcUAmpBb9vp/hFYSnQ5JibCSR8AoqWekcvKclUU XLl9p0KDFG1tGGGU2A9w0wu7Y2tQghI= X-MC-Unique: _19AyY2UPZmcU2Ypng1V4g-1 X-Mimecast-MFC-AGG-ID: _19AyY2UPZmcU2Ypng1V4g_1741528369 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 28/46] hw/intc/aspeed: Rename num_ints to num_inpins for clarity Date: Sun, 9 Mar 2025 14:51:12 +0100 Message-ID: <20250309135130.545764-29-clg@redhat.com> In-Reply-To: <20250309135130.545764-1-clg@redhat.com> References: <20250309135130.545764-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1741528404914019000 From: Jamin Lin To support AST2700 A1, some registers of the INTC(CPU Die) support one input pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC controller code for better clarity and consistency in naming conventions. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-12-jamin_li= n@aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/intc/aspeed_intc.h | 11 ++++++----- hw/arm/aspeed_ast27x0.c | 2 +- hw/intc/aspeed_intc.c | 31 +++++++++++++++++-------------- 3 files changed, 24 insertions(+), 20 deletions(-) diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 3433277d8715..58be5b3e1323 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -17,6 +17,7 @@ OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) =20 #define ASPEED_INTC_NR_INTS 9 +#define ASPEED_INTC_MAX_INPINS 9 =20 struct AspeedINTCState { /*< private >*/ @@ -27,19 +28,19 @@ struct AspeedINTCState { MemoryRegion iomem_container; =20 uint32_t *regs; - OrIRQState orgates[ASPEED_INTC_NR_INTS]; + OrIRQState orgates[ASPEED_INTC_MAX_INPINS]; qemu_irq output_pins[ASPEED_INTC_NR_INTS]; =20 - uint32_t enable[ASPEED_INTC_NR_INTS]; - uint32_t mask[ASPEED_INTC_NR_INTS]; - uint32_t pending[ASPEED_INTC_NR_INTS]; + uint32_t enable[ASPEED_INTC_MAX_INPINS]; + uint32_t mask[ASPEED_INTC_MAX_INPINS]; + uint32_t pending[ASPEED_INTC_MAX_INPINS]; }; =20 struct AspeedINTCClass { SysBusDeviceClass parent_class; =20 uint32_t num_lines; - uint32_t num_ints; + uint32_t num_inpins; uint64_t mem_size; uint64_t nr_regs; uint64_t reg_offset; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 642a8f55212f..1a3eb02af3bf 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -535,7 +535,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) sc->memmap[ASPEED_DEV_INTC]); =20 /* GICINT orgates -> INTC -> GIC */ - for (i =3D 0; i < ic->num_ints; i++) { + for (i =3D 0; i < ic->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, qdev_get_gpio_in(DEVICE(&a->intc), i)); sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index d8ee6e1c0406..217fda6fe001 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -47,8 +47,9 @@ static void aspeed_intc_update(AspeedINTCState *s, int ir= q, int level) AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); const char *name =3D object_get_typename(OBJECT(s)); =20 - if (irq >=3D aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", + if (irq >=3D aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -60,7 +61,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int ir= q, int level) /* * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804. * Utilize "address & 0x0f00" to get the irq and irq output pin index - * The value of irq should be 0 to num_ints. + * The value of irq should be 0 to num_inpins. * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on. */ static void aspeed_intc_set_irq(void *opaque, int irq, int level) @@ -73,8 +74,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) uint32_t enable; int i; =20 - if (irq >=3D aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", + if (irq >=3D aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -134,8 +135,9 @@ static void aspeed_intc_enable_handler(AspeedINTCState = *s, hwaddr offset, =20 irq =3D (offset & 0x0f00) >> 8; =20 - if (irq >=3D aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", + if (irq >=3D aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -190,8 +192,9 @@ static void aspeed_intc_status_handler(AspeedINTCState = *s, hwaddr offset, =20 irq =3D (offset & 0x0f00) >> 8; =20 - if (irq >=3D aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", + if (irq >=3D aic->num_inpins) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid input pin index: %d\n", __func__, irq); return; } @@ -299,8 +302,8 @@ static void aspeed_intc_instance_init(Object *obj) AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); int i; =20 - assert(aic->num_ints <=3D ASPEED_INTC_NR_INTS); - for (i =3D 0; i < aic->num_ints; i++) { + assert(aic->num_inpins <=3D ASPEED_INTC_MAX_INPINS); + for (i =3D 0; i < aic->num_inpins; i++) { object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i], TYPE_OR_IRQ); object_property_set_int(OBJECT(&s->orgates[i]), "num-lines", @@ -338,9 +341,9 @@ static void aspeed_intc_realize(DeviceState *dev, Error= **errp) memory_region_add_subregion(&s->iomem_container, aic->reg_offset, &s->iomem); =20 - qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints); + qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins); =20 - for (i =3D 0; i < aic->num_ints; i++) { + for (i =3D 0; i < aic->num_inpins; i++) { if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) { return; } @@ -387,7 +390,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *kl= ass, void *data) =20 dc->desc =3D "ASPEED 2700 INTC Controller"; aic->num_lines =3D 32; - aic->num_ints =3D 9; + aic->num_inpins =3D 9; aic->mem_size =3D 0x4000; aic->nr_regs =3D 0x808 >> 2; aic->reg_offset =3D 0x1000; --=20 2.48.1