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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1741528352; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aUaQKzsvhvvy0N0j9W7320QdEQpLL7U7lFSz1/+kwS4=; b=Ssjmz3Cd6IW5l37dQrmHrLXSTovRHPosFerTBGn8OhTP/u59KB9y5OK2LOFAup7wztYWJB 3KCW8ORz2fl2qle2zKb0iZOadRWsyJOegcPydb/LWKvPZvVFpFXS9jjqz+k+vHugpo0ic/ uVpEkfy5JG8Btl539Gp4LB3hgGUe5z0= X-MC-Unique: 0MGdjmzFMpWoIey5A9bx3g-1 X-Mimecast-MFC-AGG-ID: 0MGdjmzFMpWoIey5A9bx3g_1741528348 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 21/46] hw/intc/aspeed: Support setting different register size Date: Sun, 9 Mar 2025 14:51:05 +0100 Message-ID: <20250309135130.545764-22-clg@redhat.com> In-Reply-To: <20250309135130.545764-1-clg@redhat.com> References: <20250309135130.545764-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1741528416956019100 From: Jamin Lin Currently, the size of the regs array is 0x2000, which is too large. So far, it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unu= sed. To save code size, introduce a new class attribute "reg_size" to set the different register sizes for the INTC models in AST2700 and add a regs sub-region in the memory container. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-5-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/intc/aspeed_intc.h | 2 +- hw/intc/aspeed_intc.c | 22 +++++----------------- 2 files changed, 6 insertions(+), 18 deletions(-) diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 47ea0520b5d8..ec4936b3f486 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -16,7 +16,6 @@ #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) =20 -#define ASPEED_INTC_NR_REGS (0x2000 >> 2) #define ASPEED_INTC_NR_INTS 9 =20 struct AspeedINTCState { @@ -42,6 +41,7 @@ struct AspeedINTCClass { uint32_t num_lines; uint32_t num_ints; uint64_t mem_size; + uint64_t nr_regs; }; =20 #endif /* ASPEED_INTC_H */ diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 558901570f82..134922e46fdc 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -120,13 +120,6 @@ static uint64_t aspeed_intc_read(void *opaque, hwaddr = offset, unsigned int size) uint32_t reg =3D offset >> 2; uint32_t value =3D 0; =20 - if (reg >=3D ASPEED_INTC_NR_REGS) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", - __func__, offset); - return 0; - } - value =3D s->regs[reg]; trace_aspeed_intc_read(offset, size, value); =20 @@ -143,13 +136,6 @@ static void aspeed_intc_write(void *opaque, hwaddr off= set, uint64_t data, uint32_t change; uint32_t irq; =20 - if (reg >=3D ASPEED_INTC_NR_REGS) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", - __func__, offset); - return; - } - trace_aspeed_intc_write(offset, size, data); =20 switch (reg) { @@ -288,8 +274,9 @@ static void aspeed_intc_instance_init(Object *obj) static void aspeed_intc_reset(DeviceState *dev) { AspeedINTCState *s =3D ASPEED_INTC(dev); + AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); =20 - memset(s->regs, 0, ASPEED_INTC_NR_REGS << 2); + memset(s->regs, 0, aic->nr_regs << 2); memset(s->enable, 0, sizeof(s->enable)); memset(s->mask, 0, sizeof(s->mask)); memset(s->pending, 0, sizeof(s->pending)); @@ -307,9 +294,9 @@ static void aspeed_intc_realize(DeviceState *dev, Error= **errp) =20 sysbus_init_mmio(sbd, &s->iomem_container); =20 - s->regs =3D g_new(uint32_t, ASPEED_INTC_NR_REGS); + s->regs =3D g_new(uint32_t, aic->nr_regs); memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s, - TYPE_ASPEED_INTC ".regs", ASPEED_INTC_NR_REGS <<= 2); + TYPE_ASPEED_INTC ".regs", aic->nr_regs << 2); =20 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); =20 @@ -361,6 +348,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *kl= ass, void *data) aic->num_lines =3D 32; aic->num_ints =3D 9; aic->mem_size =3D 0x4000; + aic->nr_regs =3D 0x2000 >> 2; } =20 static const TypeInfo aspeed_2700_intc_info =3D { --=20 2.48.1