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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1741528346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=O8tZK7aBxCKxDPkAn4/Vz+BlTdZiPZ62vS/YeE4Ouis=; b=Ye25SORKhiqoWlhSMXEbeopbn+If2ROuVb7I3dHd67fMB+uZhSJH9TcJXrUv8XGWN7AsI4 MsxsHygNn0fN2jqdug6Pu/OYOld/uKQgIoeuRUQDoIMsWOgq90WPJuu8qqUslHEsfvfaWv I3qNFzzwmEcYC/9gZhx0vJQEFoGdwkE= X-MC-Unique: tIyXLVA4Plqjw5CorHmhkw-1 X-Mimecast-MFC-AGG-ID: tIyXLVA4Plqjw5CorHmhkw_1741528343 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 19/46] hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarity Date: Sun, 9 Mar 2025 14:51:03 +0100 Message-ID: <20250309135130.545764-20-clg@redhat.com> In-Reply-To: <20250309135130.545764-1-clg@redhat.com> References: <20250309135130.545764-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1741528383015019000 From: Jamin Lin Rename the variables "status_addr" to "status_reg" and "addr" to "reg" beca= use they are used as register index. This change makes the code more appropriate and improves readability. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-3-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/aspeed_intc.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 033b574c1e24..465f41e4fd35 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -60,7 +60,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) { AspeedINTCState *s =3D (AspeedINTCState *)opaque; AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); - uint32_t status_addr =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2); + uint32_t status_reg =3D GICINT_STATUS_BASE + ((0x100 * irq) >> 2); uint32_t select =3D 0; uint32_t enable; int i; @@ -92,7 +92,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq, in= t level) =20 trace_aspeed_intc_select(select); =20 - if (s->mask[irq] || s->regs[status_addr]) { + if (s->mask[irq] || s->regs[status_reg]) { /* * a. mask is not 0 means in ISR mode * sources interrupt routine are executing. @@ -108,8 +108,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, = int level) * notify firmware which source interrupt are coming * by setting status register */ - s->regs[status_addr] =3D select; - trace_aspeed_intc_trigger_irq(irq, s->regs[status_addr]); + s->regs[status_reg] =3D select; + trace_aspeed_intc_trigger_irq(irq, s->regs[status_reg]); aspeed_intc_update(s, irq, 1); } } @@ -117,17 +117,17 @@ static void aspeed_intc_set_irq(void *opaque, int irq= , int level) static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int= size) { AspeedINTCState *s =3D ASPEED_INTC(opaque); - uint32_t addr =3D offset >> 2; + uint32_t reg =3D offset >> 2; uint32_t value =3D 0; =20 - if (addr >=3D ASPEED_INTC_NR_REGS) { + if (reg >=3D ASPEED_INTC_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", __func__, offset); return 0; } =20 - value =3D s->regs[addr]; + value =3D s->regs[reg]; trace_aspeed_intc_read(offset, size, value); =20 return value; @@ -138,12 +138,12 @@ static void aspeed_intc_write(void *opaque, hwaddr of= fset, uint64_t data, { AspeedINTCState *s =3D ASPEED_INTC(opaque); AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); - uint32_t addr =3D offset >> 2; + uint32_t reg =3D offset >> 2; uint32_t old_enable; uint32_t change; uint32_t irq; =20 - if (addr >=3D ASPEED_INTC_NR_REGS) { + if (reg >=3D ASPEED_INTC_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", __func__, offset); @@ -152,7 +152,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, =20 trace_aspeed_intc_write(offset, size, data); =20 - switch (addr) { + switch (reg) { case R_GICINT128_EN: case R_GICINT129_EN: case R_GICINT130_EN: @@ -177,7 +177,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, =20 /* disable all source interrupt */ if (!data && !s->enable[irq]) { - s->regs[addr] =3D data; + s->regs[reg] =3D data; return; } =20 @@ -187,12 +187,12 @@ static void aspeed_intc_write(void *opaque, hwaddr of= fset, uint64_t data, /* enable new source interrupt */ if (old_enable !=3D s->enable[irq]) { trace_aspeed_intc_enable(s->enable[irq]); - s->regs[addr] =3D data; + s->regs[reg] =3D data; return; } =20 /* mask and unmask source interrupt */ - change =3D s->regs[addr] ^ data; + change =3D s->regs[reg] ^ data; if (change & data) { s->mask[irq] &=3D ~change; trace_aspeed_intc_unmask(change, s->mask[irq]); @@ -200,7 +200,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, s->mask[irq] |=3D change; trace_aspeed_intc_mask(change, s->mask[irq]); } - s->regs[addr] =3D data; + s->regs[reg] =3D data; break; case R_GICINT128_STATUS: case R_GICINT129_STATUS: @@ -220,7 +220,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, } =20 /* clear status */ - s->regs[addr] &=3D ~data; + s->regs[reg] &=3D ~data; =20 /* * These status registers are used for notify sources ISR are exec= uted. @@ -233,7 +233,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, } =20 /* All source ISR execution are done */ - if (!s->regs[addr]) { + if (!s->regs[reg]) { trace_aspeed_intc_all_isr_done(irq); if (s->pending[irq]) { /* @@ -241,9 +241,9 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, * notify firmware which source interrupt are pending * by setting status register */ - s->regs[addr] =3D s->pending[irq]; + s->regs[reg] =3D s->pending[irq]; s->pending[irq] =3D 0; - trace_aspeed_intc_trigger_irq(irq, s->regs[addr]); + trace_aspeed_intc_trigger_irq(irq, s->regs[reg]); aspeed_intc_update(s, irq, 1); } else { /* clear irq */ @@ -253,7 +253,7 @@ static void aspeed_intc_write(void *opaque, hwaddr offs= et, uint64_t data, } break; default: - s->regs[addr] =3D data; + s->regs[reg] =3D data; break; } =20 --=20 2.48.1