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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1741528336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JNPAU5k1s0L03xvqrFVQx6ossP+Jgo9X576iOaJVLOw=; b=hQs7c45uj72fkodH+StBFNqMLCXXz8Zg5nCFQHaoQwSSo0TjTYyIlYjF70LFivY6d6cYXF d6xQHBiQe81aMQ1Jrrv3rV/xnmh1wGPDFzqba8aXhd4XybAoB3oVYPQTl6oq0aRAhgUvA7 ab6Yy+DOjFmKjISbnxE+eLHa61YXStI= X-MC-Unique: B_p-CwjXNkG5xbiORtfHNg-1 X-Mimecast-MFC-AGG-ID: B_p-CwjXNkG5xbiORtfHNg_1741528330 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , Nabih Estefan , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 13/46] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700 Date: Sun, 9 Mar 2025 14:50:57 +0100 Message-ID: <20250309135130.545764-14-clg@redhat.com> In-Reply-To: <20250309135130.545764-1-clg@redhat.com> References: <20250309135130.545764-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1741528376040019100 From: Jamin Lin According to the design of the AST2600, it has a Silicon Revision ID Regist= er, specifically SCU004 and SCU014, to set the Revision ID for the AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x0503= 0303. In the "aspeed_ast2600_scu_reset" function, the hardcoded value "AST2600_A3_SILICON_REV" is set in SCU004, and "s->silicon_rev" is set in SCU014. The value of "s->silicon_rev" is set by the SOC layer via the "silicon-rev" property. However, the design of the AST2700 is different. There are two SCU controll= ers: SCU0 (CPU Die) and SCU1 (IO Die). In the AST2700, the firmware reads the SCU Silicon Revision ID register (SCU0_000) and the SCUIO Silicon Revision ID register (SCU1_000), combining them into a single 64-bit value. The upper 32 bits represent the SCUIO, while the lower 32 bits correspond t= o the SCU. For example, the AST2700-A1 revision is represented as 0x0601010306010= 103. SCUIO_000 occupies bits [63:32] with a value of 0x06010103 and SCU_000 occu= pies bits [31:0] with a value of 0x06010103. Reference: https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/arch/a= rm/mach-aspeed/ast2700/cpu-info.c Signed-off-by: Jamin Lin Tested-by: Nabih Estefan Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250304064710.2128993-3-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 50f74fbabd6e..545d00474968 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -910,7 +910,6 @@ static const MemoryRegionOps aspeed_ast2700_scu_ops =3D= { }; =20 static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] =3D { - [AST2700_SILICON_REV] =3D AST2700_A0_SILICON_REV, [AST2700_HW_STRAP1] =3D 0x00000800, [AST2700_HW_STRAP1_CLR] =3D 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] =3D 0x00000FFF, @@ -940,6 +939,7 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev) AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(dev); =20 memcpy(s->regs, asc->resets, asc->nr_regs * 4); + s->regs[AST2700_SILICON_REV] =3D s->silicon_rev; } =20 static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data) @@ -1032,7 +1032,6 @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops= =3D { }; =20 static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] =3D= { - [AST2700_SILICON_REV] =3D 0x06000003, [AST2700_HW_STRAP1] =3D 0x00000504, [AST2700_HW_STRAP1_CLR] =3D 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] =3D 0x00000FFF, --=20 2.48.1