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b=DkDwfGcCm3LOXcEPaNFCSN P0UuUba6IHn55czmniCSkgTUc6Ew3eD74zQ6nbGOTeNRoYATsviKlgRiTM8gtnch nxMPuSLwQO8sZrIFeIC3j/YQDG4+VVsxwPQ3+K3O5MsLUau4OEDOtF8rRA+ezGJt dYwI67Vpz49Kyveu1pqlK+hnyOaxO42Ezn7gW56QYf4iKa6BNd8r1h80988Ri6QM cILrLn9/Ej9OCHXWC+Rp4Uusf8G5iK88QEAYPzKQ5ScAYHEa1xaVBnpcekABZ9rC hpJZK5IHvGo9sXWeCiAc9QMy3PM7q2y0Xq0fEjoQsA4M+ckfTxpkvV20B+3dVkvg == From: Aditya Gupta To: Mahesh J Salgaonkar , Madhavan Srinivasan , Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Harsh Prateek Bora , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= Cc: , Subject: [PATCH v5 7/8] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine Date: Sun, 9 Mar 2025 02:21:40 +0530 Message-ID: <20250308205141.3219333-8-adityag@linux.ibm.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250308205141.3219333-1-adityag@linux.ibm.com> References: <20250308205141.3219333-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 9WxBH2UQGpWDRiz7WE1WOlmy95pfpcl6 X-Proofpoint-ORIG-GUID: d4WONWM7_twnjEKP2O0kK6WoGEM9DjT- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-08_08,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 mlxscore=0 suspectscore=0 adultscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503080159 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1741467230020019100 Power11 core is same as Power10. Introduce a Power11 chip and machine, with Power10 chip as parent of Power11 chip. Due to Power10 chip being declared as Power11 chip, all functions can cast 'Pnv11Chip' as 'Pnv10Chip' thus allowing it to reuse Power10's functionality, such as in PHB. Homer code PowerNV11 declares a separate class_init and instance_init to be able to declare correct CFAM, and initialise Power11 specific child objects such as Homer, OCC etc. Other functionalities will use the Power10's codepath in Power11 for most cases. Cc: C=C3=A9dric Le Goater Cc: Fr=C3=A9d=C3=A9ric Barrat Cc: Mahesh J Salgaonkar Cc: Madhavan Srinivasan Cc: Nicholas Piggin Signed-off-by: Aditya Gupta --- docs/system/ppc/powernv.rst | 9 +- hw/ppc/pnv.c | 177 +++++++++++++++++++++++++++++++++++- hw/ppc/pnv_core.c | 11 +++ include/hw/ppc/pnv.h | 5 + include/hw/ppc/pnv_chip.h | 7 ++ include/hw/ppc/pnv_core.h | 1 + 6 files changed, 201 insertions(+), 9 deletions(-) diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst index de7a807ac762..366da9bc371c 100644 --- a/docs/system/ppc/powernv.rst +++ b/docs/system/ppc/powernv.rst @@ -1,5 +1,5 @@ -PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powern= v11``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 PowerNV (as Non-Virtualized) is the "bare metal" platform using the OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can @@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today. Supported devices ----------------- =20 - * Multi processor support for POWER8, POWER8NVL and POWER9. + * Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Powe= r11. * XSCOM, serial communication sideband bus to configure chiplets. * Simple LPC Controller. * Processor Service Interface (PSI) Controller. - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power1= 0). + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power1= 0 & + Power11). * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge. * Simple OCC is an on-chip micro-controller used for power management tas= ks. * iBT device to handle BMC communication, with the internal BMC simulator diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 87607508c768..1c4dc4ed1764 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -22,6 +22,7 @@ #include "qemu/units.h" #include "qemu/cutils.h" #include "qapi/error.h" +#include "qom/object.h" #include "system/qtest.h" #include "system/system.h" #include "system/numa.h" @@ -486,6 +487,33 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip= , void *fdt) pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); } =20 +static void pnv_chip_power11_dt_populate(PnvChip *chip, void *fdt) +{ + static const char compat[] =3D "ibm,power11-xscom\0ibm,xscom"; + int i; + + pnv_dt_xscom(chip, fdt, 0, + cpu_to_be64(PNV10_XSCOM_BASE(chip)), + cpu_to_be64(PNV10_XSCOM_SIZE), + compat, sizeof(compat)); + + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pnv_core =3D chip->cores[i]; + int offset; + + offset =3D pnv_dt_core(chip, pnv_core, fdt); + + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", + pa_features_31, sizeof(pa_features_31)))); + } + + if (chip->ram_size) { + pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); + } + + pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); +} + static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) { uint32_t io_base =3D d->ioport_id; @@ -1435,6 +1463,8 @@ static void pnv_chip_power10_intc_print_info(PnvChip = *chip, PowerPCCPU *cpu, =20 #define POWER10_CORE_MASK (0xffffffffffffffull) =20 +#define POWER11_CORE_MASK (0xffffffffffffffull) + static void pnv_chip_power8_instance_init(Object *obj) { Pnv8Chip *chip8 =3D PNV8_CHIP(obj); @@ -1966,6 +1996,20 @@ static void pnv_chip_power10_instance_init(Object *o= bj) PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(obj); int i; =20 + /* + * Power11 declares Power10 as it's parent class, to be able to reuse + * most of the Power10 code. + * But this causes Power10 and Power11's both instance init to be + * called for PowerNV11 chip + * + * Skip initialising Power10 specific child objects, if the chip is + * Power11 chip, in which case power11's instance init will initialise + * the child objects + */ + if (!strcmp(object_get_typename(obj), TYPE_PNV_CHIP_POWER11)) { + return; + } + object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), @@ -1997,7 +2041,8 @@ static void pnv_chip_power10_instance_init(Object *ob= j) } } =20 -static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) +static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp, + const char *cpu_model) { PnvChip *chip =3D PNV_CHIP(chip10); int i; @@ -2007,9 +2052,10 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip = *chip10, Error **errp) =20 for (i =3D 0; i < chip10->nr_quads; i++) { PnvQuad *eq =3D &chip10->quads[i]; + g_autofree char *type_name =3D PNV_QUAD_TYPE_NAME_DYN(cpu_model); =20 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], - PNV_QUAD_TYPE_NAME("power10")); + type_name); =20 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), &eq->xscom_regs); @@ -2047,7 +2093,8 @@ static void pnv_chip_power10_phb_realize(PnvChip *chi= p, Error **errp) } } =20 -static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) +static void pnv_chip_power10_common_realize(DeviceState *dev, Error **errp, + const char *cpu_model) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(dev); PnvChip *chip =3D PNV_CHIP(dev); @@ -2073,7 +2120,7 @@ static void pnv_chip_power10_realize(DeviceState *dev= , Error **errp) pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, &chip10->adu.xscom_regs); =20 - pnv_chip_power10_quad_realize(chip10, &local_err); + pnv_chip_power10_quad_realize(chip10, &local_err, cpu_model); if (local_err) { error_propagate(errp, local_err); return; @@ -2235,6 +2282,54 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) } } =20 +static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) +{ + pnv_chip_power10_common_realize(dev, errp, "power10"); +} + +static void pnv_chip_power11_instance_init(Object *obj) +{ + PnvChip *chip =3D PNV_CHIP(obj); + Pnv11Chip *chip11 =3D PNV11_CHIP(obj); + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(obj); + int i; + + object_initialize_child(obj, "adu", &chip11->adu, TYPE_PNV_ADU); + object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2); + object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive), + "xive-fabric"); + object_initialize_child(obj, "psi", &chip11->psi, TYPE_PNV11_PSI); + object_initialize_child(obj, "lpc", &chip11->lpc, TYPE_PNV11_LPC); + object_initialize_child(obj, "chiptod", &chip11->chiptod, + TYPE_PNV11_CHIPTOD); + object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV11_OCC); + object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV11_SBE); + object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV11_HOMER= ); + object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet, + TYPE_PNV_N1_CHIPLET); + + chip->num_pecs =3D pcc->num_pecs; + + for (i =3D 0; i < chip->num_pecs; i++) { + object_initialize_child(obj, "pec[*]", &chip11->pecs[i], + TYPE_PNV_PHB5_PEC); + } + + for (i =3D 0; i < pcc->i2c_num_engines; i++) { + object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I= 2C); + } + + for (i =3D 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { + object_initialize_child(obj, "pib_spic[*]", &chip11->pib_spic[i], + TYPE_PNV_SPI); + } +} + +static void pnv_chip_power11_realize(DeviceState *dev, Error **errp) +{ + pnv_chip_power10_common_realize(dev, errp, "power11"); +} + static void pnv_rainier_i2c_init(PnvMachineState *pnv) { int i; @@ -2300,6 +2395,34 @@ static void pnv_chip_power10_class_init(ObjectClass = *klass, void *data) &k->parent_realize); } =20 +static void pnv_chip_power11_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvChipClass *k =3D PNV_CHIP_CLASS(klass); + + static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] =3D {14, 14,= 2, 16}; + + k->chip_cfam_id =3D 0x220da04980000000ull; /* P11 DD2.0 (with NX) */ + k->cores_mask =3D POWER11_CORE_MASK; + k->get_pir_tir =3D pnv_get_pir_tir_p10; + k->intc_create =3D pnv_chip_power10_intc_create; + k->intc_reset =3D pnv_chip_power10_intc_reset; + k->intc_destroy =3D pnv_chip_power10_intc_destroy; + k->intc_print_info =3D pnv_chip_power10_intc_print_info; + k->isa_create =3D pnv_chip_power10_isa_create; + k->dt_populate =3D pnv_chip_power11_dt_populate; + k->pic_print_info =3D pnv_chip_power10_pic_print_info; + k->xscom_core_base =3D pnv_chip_power10_xscom_core_base; + k->xscom_pcba =3D pnv_chip_power10_xscom_pcba; + dc->desc =3D "PowerNV Chip POWER11"; + k->num_pecs =3D PNV10_CHIP_MAX_PEC; + k->i2c_num_engines =3D PNV10_CHIP_MAX_I2C; + k->i2c_ports_per_engine =3D i2c_ports_per_engine; + + device_class_set_parent_realize(dc, pnv_chip_power11_realize, + &k->parent_realize); +} + static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, Error **errp) { @@ -2757,7 +2880,6 @@ static void pnv_machine_p10_common_class_init(ObjectC= lass *oc, void *data) { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, }; =20 - mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power10_v2.0"); compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat= )); =20 mc->alias =3D "powernv"; @@ -2780,6 +2902,7 @@ static void pnv_machine_power10_class_init(ObjectClas= s *oc, void *data) =20 pnv_machine_p10_common_class_init(oc, data); mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER10"; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power10_v2.0"); =20 /* * This is the parent of POWER10 Rainier class, so properies go here @@ -2806,9 +2929,26 @@ static void pnv_machine_p10_rainier_class_init(Objec= tClass *oc, void *data) =20 pnv_machine_p10_common_class_init(oc, data); mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power10_v2.0"); pmc->i2c_init =3D pnv_rainier_i2c_init; } =20 +static void pnv_machine_power11_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); + static const char compat[] =3D "qemu,powernv11\0ibm,powernv"; + + /* do power10_class_init as p11 core is same as p10 */ + pnv_machine_p10_common_class_init(oc, data); + + mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER11"; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power11_v2.0"); + + pmc->compat =3D compat; + pmc->compat_size =3D sizeof(compat); +} + static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) { CPUPPCState *env =3D cpu_env(cs); @@ -2914,7 +3054,23 @@ static void pnv_machine_class_init(ObjectClass *oc, = void *data) .parent =3D TYPE_PNV10_CHIP, \ } =20 +#define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \ + { \ + .name =3D type, \ + .class_init =3D class_initfn, \ + .parent =3D TYPE_PNV11_CHIP, \ + } + static const TypeInfo types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("powernv11"), + .parent =3D TYPE_PNV_MACHINE, + .class_init =3D pnv_machine_power11_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_XIVE_FABRIC }, + { }, + }, + }, { .name =3D MACHINE_TYPE_NAME("powernv10-rainier"), .parent =3D MACHINE_TYPE_NAME("powernv10"), @@ -2969,6 +3125,17 @@ static const TypeInfo types[] =3D { .abstract =3D true, }, =20 + /* + * P11 chip and variants + */ + { + .name =3D TYPE_PNV11_CHIP, + .parent =3D TYPE_PNV10_CHIP, + .instance_init =3D pnv_chip_power11_instance_init, + .instance_size =3D sizeof(Pnv11Chip), + }, + DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_i= nit), + /* * P10 chip and variants */ diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 99d9644ee38e..12916b15aa3b 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -469,6 +469,11 @@ static void pnv_core_power10_class_init(ObjectClass *o= c, void *data) pcc->xscom_size =3D PNV10_XSCOM_EC_SIZE; } =20 +static void pnv_core_power11_class_init(ObjectClass *oc, void *data) +{ + pnv_core_power10_class_init(oc, data); +} + static void pnv_core_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -500,6 +505,7 @@ static const TypeInfo pnv_core_infos[] =3D { DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), + DEFINE_PNV_CORE_TYPE(power11, "power11_v2.0"), }; =20 DEFINE_TYPES(pnv_core_infos) @@ -748,6 +754,11 @@ static const TypeInfo pnv_quad_infos[] =3D { .name =3D PNV_QUAD_TYPE_NAME("power10"), .class_init =3D pnv_quad_power10_class_init, }, + { + .parent =3D PNV_QUAD_TYPE_NAME("power10"), + .name =3D PNV_QUAD_TYPE_NAME("power11"), + .class_init =3D pnv_quad_power10_class_init, + }, }; =20 DEFINE_TYPES(pnv_quad_infos); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index fcb6699150c8..ac960aa0fda9 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -33,6 +33,7 @@ typedef struct PnvChip PnvChip; typedef struct Pnv8Chip Pnv8Chip; typedef struct Pnv9Chip Pnv9Chip; typedef struct Pnv10Chip Pnv10Chip; +typedef struct Pnv10Chip Pnv11Chip; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX @@ -57,6 +58,10 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, TYPE_PNV_CHIP_POWER10) =20 +#define TYPE_PNV_CHIP_POWER11 PNV_CHIP_TYPE_NAME("power11_v2.0") +DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER11, + TYPE_PNV_CHIP_POWER11) + PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id); PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); =20 diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 24ce37a9c8e4..6bd930f8b439 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -141,6 +141,13 @@ struct Pnv10Chip { #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) #define PNV10_PIR2THREAD(pir) (((pir) & 0x7f)) =20 +#define TYPE_PNV11_CHIP "pnv11-chip" +DECLARE_INSTANCE_CHECKER(Pnv11Chip, PNV11_CHIP, + TYPE_PNV11_CHIP) + +/* Power11 core is same as Power10 */ +typedef struct Pnv10Chip Pnv11Chip; + struct PnvChipClass { /*< private >*/ SysBusDeviceClass parent_class; diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index d8afb4f95f92..febe940a9af5 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -104,6 +104,7 @@ struct PnvQuadClass { =20 #define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD #define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX +#define PNV_QUAD_TYPE_NAME_DYN(cpu) g_strconcat(cpu, PNV_QUAD_TYPE_SUFFIX,= NULL) =20 OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD) =20 --=20 2.48.1