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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373809; x=1741978609; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jZWYvDukaHCKn8Evm+7YplK9ZxqRKLhmL0oVaH6y4jI=; b=Fya8TKmlPnOFMdrlY5Bhma/yZnzm6/Hshr/iKiiwsjXQUOD2ogmJtHD0Es3I1nvjp6 kzHoZUXDLDe28ywR4SyDTRiBPXDJlI7ULgEyQemBJv73j4D3LM70wokD24XVDfpgNelY ghLcAexY4WxTyFAVSODsON7FBZVgiY93BX8SaqxvDLh0iuEa54zsJ4e7xJOcZAI2OPZx Q4lfmIJw/A6kkAchBYPHkoBWl+kJmEwWDk1ZrWU5A0EO3JDYaKFpoixbYJ74KYZv0fSW IiMPcxiPN4m2PW+lustG5SaKpYY7qdg84Rvzs9vPRco9XQGO0jCCZNZVq3bU0knAR5kj IIHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373809; x=1741978609; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jZWYvDukaHCKn8Evm+7YplK9ZxqRKLhmL0oVaH6y4jI=; b=ci+VbYz1Pz8KupIy72B2z1SsQeBcelDP6qIoCDH/OpYyB5/s/GACpO5ztDZP6dQgeL JRz3d5J3BN6SD6tUORc1dooz79o//9jsrVsff4lG+g+lRT6TN/VWZDXcY2HlSZTIPfFg IFU0iZqlFCrN34W+7a0IlgAajmKWUPexo0ksrmLftwy5m7b6WHW1lnReJOc9z9lztzZr CB5wzqto4MgZoLogVsGppWeRQ51yrH24LKupGZiTjF7yswWGgdiJzE/LM7KHNUg5UdGr VMJncybgI6PNCIJ/JcJrtOjmfzslyqqxw4lFuh/DfcFP9Ev1JgTe88Bxw6OYGTwBHFp+ L+Gw== X-Gm-Message-State: AOJu0YwOBu1SzEZq1yKj+BVoki+K2FJbEN1RTnW/d+0JmbYWu3VZL7ai xTbAJBSfqp4vVD4+KyER1XXWWskYc4j7GaPMVBhE0uolmUnwtmqdmAsERZC2lgUWkuxiboNt2f0 U X-Gm-Gg: ASbGncsZWaTmGRyL54QUr/8eNX5hAgVm9KwOYMcu1YJOLvrWaoFCvEwD6XEx2r2G2U/ 8SpIzBLkjOlphQLIAQx4vdtpvz+DEb8Iw2Ra7JodZLgKRIszvm48FV0hk2WZ9IwyJ9GT2Brg0d7 9BOJ1O+UHyrvWqYOIM16g/1wi5RwTaGB7Hur3I1kUrrTcyMFTJv2ykd49cXILb6GxC1BBYi60Pz j/gkaUGK0xaBo/c1nMINakew0FlbkbVSOSbjnPV9TC+0C1BtKmRNjED9DCn8uEloqxmEtPK8f/F EHmHcBUUT3FXkwkeKhUMXZl9ZxUuup2MiR+vPfkwUQcCkXnBQB4ef1ZIaezRbAk+4flSFei3YQ2 4 X-Google-Smtp-Source: AGHT+IE70cx2fqD7V7rU/8JSAY/C0kQV5m7e0A7i4hqb43Jwd+uMX0sHLExq9eVPeIE2MqTMGU+pcA== X-Received: by 2002:a17:90b:4c:b0:2ff:6a5f:9b39 with SMTP id 98e67ed59e1d1-2ff7ce844b6mr8226390a91.18.1741373808901; Fri, 07 Mar 2025 10:56:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 01/16] include/exec: Split out exec/cpu-interrupt.h Date: Fri, 7 Mar 2025 10:56:30 -0800 Message-ID: <20250307185645.970034-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373982029019000 Content-Type: text/plain; charset="utf-8" Some of these bits are actually common to all cpus; while the reset have common reservations for target-specific usage. While generic code cannot know what the target-specific usage is, common code can know what to do with the bits, e.g. single-step. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 53 +-------------------------- include/exec/cpu-interrupt.h | 70 ++++++++++++++++++++++++++++++++++++ include/exec/poison.h | 13 ------- 3 files changed, 71 insertions(+), 65 deletions(-) create mode 100644 include/exec/cpu-interrupt.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8f7aebb088..9e6724097c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -21,6 +21,7 @@ =20 #include "exec/page-protection.h" #include "exec/cpu-common.h" +#include "exec/cpu-interrupt.h" #include "exec/memory.h" #include "exec/tswap.h" #include "hw/core/cpu.h" @@ -109,58 +110,6 @@ static inline void stl_phys_notdirty(AddressSpace *as,= hwaddr addr, uint32_t val =20 CPUArchState *cpu_copy(CPUArchState *env); =20 -/* Flags for use in ENV->INTERRUPT_PENDING. - - The numbers assigned here are non-sequential in order to preserve - binary compatibility with the vmstate dump. Bit 0 (0x0001) was - previously used for CPU_INTERRUPT_EXIT, and is cleared when loading - the vmstate dump. */ - -/* External hardware interrupt pending. This is typically used for - interrupts from devices. */ -#define CPU_INTERRUPT_HARD 0x0002 - -/* Exit the current TB. This is typically used when some system-level dev= ice - makes some change to the memory mapping. E.g. the a20 line change. */ -#define CPU_INTERRUPT_EXITTB 0x0004 - -/* Halt the CPU. */ -#define CPU_INTERRUPT_HALT 0x0020 - -/* Debug event pending. */ -#define CPU_INTERRUPT_DEBUG 0x0080 - -/* Reset signal. */ -#define CPU_INTERRUPT_RESET 0x0400 - -/* Several target-specific external hardware interrupts. Each target/cpu.h - should define proper names based on these defines. */ -#define CPU_INTERRUPT_TGT_EXT_0 0x0008 -#define CPU_INTERRUPT_TGT_EXT_1 0x0010 -#define CPU_INTERRUPT_TGT_EXT_2 0x0040 -#define CPU_INTERRUPT_TGT_EXT_3 0x0200 -#define CPU_INTERRUPT_TGT_EXT_4 0x1000 - -/* Several target-specific internal interrupts. These differ from the - preceding target-specific interrupts in that they are intended to - originate from within the cpu itself, typically in response to some - instruction being executed. These, therefore, are not masked while - single-stepping within the debugger. */ -#define CPU_INTERRUPT_TGT_INT_0 0x0100 -#define CPU_INTERRUPT_TGT_INT_1 0x0800 -#define CPU_INTERRUPT_TGT_INT_2 0x2000 - -/* First unused bit: 0x4000. */ - -/* The set of all bits that should be masked when single-stepping. */ -#define CPU_INTERRUPT_SSTEP_MASK \ - (CPU_INTERRUPT_HARD \ - | CPU_INTERRUPT_TGT_EXT_0 \ - | CPU_INTERRUPT_TGT_EXT_1 \ - | CPU_INTERRUPT_TGT_EXT_2 \ - | CPU_INTERRUPT_TGT_EXT_3 \ - | CPU_INTERRUPT_TGT_EXT_4) - #include "cpu.h" =20 #ifdef CONFIG_USER_ONLY diff --git a/include/exec/cpu-interrupt.h b/include/exec/cpu-interrupt.h new file mode 100644 index 0000000000..40715193ca --- /dev/null +++ b/include/exec/cpu-interrupt.h @@ -0,0 +1,70 @@ +/* + * Flags for use with cpu_interrupt() + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef CPU_INTERRUPT_H +#define CPU_INTERRUPT_H + +/* + * The numbers assigned here are non-sequential in order to preserve binary + * compatibility with the vmstate dump. Bit 0 (0x0001) was previously used + * for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump. + */ + +/* + * External hardware interrupt pending. + * This is typically used for interrupts from devices. + */ +#define CPU_INTERRUPT_HARD 0x0002 + +/* + * Exit the current TB. This is typically used when some system-level dev= ice + * makes some change to the memory mapping. E.g. the a20 line change. + */ +#define CPU_INTERRUPT_EXITTB 0x0004 + +/* Halt the CPU. */ +#define CPU_INTERRUPT_HALT 0x0020 + +/* Debug event pending. */ +#define CPU_INTERRUPT_DEBUG 0x0080 + +/* Reset signal. */ +#define CPU_INTERRUPT_RESET 0x0400 + +/* + * Several target-specific external hardware interrupts. Each target/cpu.h + * should define proper names based on these defines. + */ +#define CPU_INTERRUPT_TGT_EXT_0 0x0008 +#define CPU_INTERRUPT_TGT_EXT_1 0x0010 +#define CPU_INTERRUPT_TGT_EXT_2 0x0040 +#define CPU_INTERRUPT_TGT_EXT_3 0x0200 +#define CPU_INTERRUPT_TGT_EXT_4 0x1000 + +/* + * Several target-specific internal interrupts. These differ from the + * preceding target-specific interrupts in that they are intended to + * originate from within the cpu itself, typically in response to some + * instruction being executed. These, therefore, are not masked while + * single-stepping within the debugger. + */ +#define CPU_INTERRUPT_TGT_INT_0 0x0100 +#define CPU_INTERRUPT_TGT_INT_1 0x0800 +#define CPU_INTERRUPT_TGT_INT_2 0x2000 + +/* First unused bit: 0x4000. */ + +/* The set of all bits that should be masked when single-stepping. */ +#define CPU_INTERRUPT_SSTEP_MASK \ + (CPU_INTERRUPT_HARD \ + | CPU_INTERRUPT_TGT_EXT_0 \ + | CPU_INTERRUPT_TGT_EXT_1 \ + | CPU_INTERRUPT_TGT_EXT_2 \ + | CPU_INTERRUPT_TGT_EXT_3 \ + | CPU_INTERRUPT_TGT_EXT_4) + +#endif /* CPU_INTERRUPT_H */ diff --git a/include/exec/poison.h b/include/exec/poison.h index 35721366d7..8ed04b3108 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -46,19 +46,6 @@ =20 #pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS =20 -#pragma GCC poison CPU_INTERRUPT_HARD -#pragma GCC poison CPU_INTERRUPT_EXITTB -#pragma GCC poison CPU_INTERRUPT_HALT -#pragma GCC poison CPU_INTERRUPT_DEBUG -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_2 - #pragma GCC poison CONFIG_ALPHA_DIS #pragma GCC poison CONFIG_HPPA_DIS #pragma GCC poison CONFIG_I386_DIS --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373992; cv=none; d=zohomail.com; s=zohoarc; b=fIYOCGOfCOLTbSB6XqbYIP/ZNHSM8CK6JNN0/azu9Gs41uSIRpwbnxhCkokuv+yF+M3/fCOLfNr7GAXLOOAxhKlZ4Q1NIAhbFZ0uqbdqfPCQIG6UYuyka2DkuFu/X7ih3jEjApPaLfe8zUekx5m+XCEvIhlMc3MDqT5ts0OW6k4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373992; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Vo9EUeboH3pwKtes0Z0Mb9EvndFByljrwhTfKec7eDo=; b=hX8aQNXzGbjIVLEifpi47bkjAIe2LUJNM2zF/WvcooHB6VIY4sMaTmMkZsWyI2iGgGvQaR/ZzjHtpAE5g751hK0BAXW3mTvwoma+R6Uho4K4EbNSDyCYGjyb3km3svh6ILQYTaJz/vMFAvIVXuB5ZpIkyLfKSCBtFXwLeIZ0wrc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373992252786.0974480071358; Fri, 7 Mar 2025 10:59:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsd-0007XF-Eh; Fri, 07 Mar 2025 13:57:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsP-0007Rh-Vz for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:54 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsN-0007lO-0r for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:53 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-22401f4d35aso43049595ad.2 for ; Fri, 07 Mar 2025 10:56:50 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373809; x=1741978609; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vo9EUeboH3pwKtes0Z0Mb9EvndFByljrwhTfKec7eDo=; b=nhFj/IK3z40Y/5Zd3T6HBeldI4dHNxZ5zTLO8+JBHgoI5X3qWBSkL99mEu45kC5HzC jrfw8gB5peqz4IN5eiOm4hx781MsqSm93ejM1Y0vWwT9G4dYcBtVRLhzq4XqPlun6olR mRn2mGi947rd8DVsLcP0XvD6kwXFJ1VCSq7T0Ux/0ZE8AjfkqQehTw8fMr4Q/mEMYwhP VXA3+NhjbmE9q5OfG2CB3I1sCN5AORcqbqZJk+QCr9B5vuZ4TAIp3XmfMZVsxF0JsM7k ald6ePaF5ceL3c3YUU25T7Hl4zRZDiwk0C5134HV7mooGZffu8uynlNvx/KeGpRNz9pi cSqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373809; x=1741978609; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vo9EUeboH3pwKtes0Z0Mb9EvndFByljrwhTfKec7eDo=; b=H0onRnCNrq/Uq8AqtjxGgyzCLpx1V6u7fE1DavMCmJ8Rze4/D6TXCDPqMpQHI70Fex bEZBDFbFqjY4CVycPiWhtwH5S3UL1CxdWxAWO2skxIEIpGLFEmx7LKfVJdwgV6WkHkwL BY++WPxRzMuASGUxA3YhM7hXZWYr8GRIX0zzFJ1jMpWdGroiCU8lD9Hszj4RTPnNSVGU HfSKvxD9g574GJbRw1M1YAYJPufGYXzhiVEtQZXfpfx6MDmIuz419UV/cEEvmaKjVgaz Z4DMDpENuqJzKY0JWj4K752cwPWaMpwb2rLaDG7J/KMNzti5dnaqNbxkSmwTWZ4x/Egc zWRg== X-Gm-Message-State: AOJu0YwD/mKGvAsHvaikPJz4WHfNSi1Euc4YXw82vai0KgZXo9SiHMRt yQ/tAqpFmKzvRDX4ttr9a6vunjt9pBpDLx/GJH/OVsKDRU/lVWDWjJ2hBlCwc0ZbIsss4l1Prdc f X-Gm-Gg: ASbGncszCLlS6va862daGWg3EZA+1CEhJcvq8Cl1WaOadRHFshzkR3MFCL3PLORUU0V jxI7Kxi/ACUKB96vFhkhLpRRxAtRhlNWcSGetEklU6pmOVT5Nhya7j20P4xVD5Z5lWbIaLRsuyZ ktD2G7cFsWzFePpRJ6ViDKbrwhZIYCRTDhGazD21x489/LAymNKXsx3vH9CtL2WOio/R5D6Q5hX dpusXBI3nqP26TGj6Rk+zIHF0OT/eQ06eNXnGStikR13T72BOHme5n6cbBYfgk+HFpkYA9br3mh eTxNqV/t9EFXw5NRSDlJeE91SgSMbM9fSUxBXV/8MV823OfV8zHepibXgwBVoWKz6oLTHUKNEdo I X-Google-Smtp-Source: AGHT+IGz+IGl0p1/KoWRnfRhFVwHK1ZC5+p8HozPLiHkUyNvRY8VHdGXy1/jcUIrhBYmUUHULLtYLA== X-Received: by 2002:a17:903:8c6:b0:223:47d9:1964 with SMTP id d9443c01a7336-22428ac953fmr78709045ad.34.1741373809531; Fri, 07 Mar 2025 10:56:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 02/16] accel/tcg: Compile watchpoint.c once Date: Fri, 7 Mar 2025 10:56:31 -0800 Message-ID: <20250307185645.970034-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373994034019000 Content-Type: text/plain; charset="utf-8" Move tb_check_watchpoint declaration from tb-internal.h, which is still target-specific, to internal-common.h, which isn't. Otherwise, all that is required to build watchpoint.c once is to include the new exec/cpu-interrupt.h instead of exec/exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Tested-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/internal-common.h | 2 ++ accel/tcg/tb-internal.h | 2 -- accel/tcg/watchpoint.c | 5 ++--- accel/tcg/meson.build | 2 +- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 7ef620d963..9b6ab3a8cc 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -72,4 +72,6 @@ void tcg_exec_unrealizefn(CPUState *cpu); /* current cflags for hashing/comparison */ uint32_t curr_cflags(CPUState *cpu); =20 +void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); + #endif diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index abd423fcf5..62a59a5307 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -75,6 +75,4 @@ void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, =20 bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); =20 -void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); - #endif diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index 40112b2b2e..ba8c9859cf 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -19,11 +19,10 @@ =20 #include "qemu/osdep.h" #include "qemu/main-loop.h" -#include "qemu/error-report.h" -#include "exec/exec-all.h" +#include "exec/breakpoint.h" +#include "exec/cpu-interrupt.h" #include "exec/page-protection.h" #include "exec/translation-block.h" -#include "tb-internal.h" #include "system/tcg.h" #include "system/replay.h" #include "accel/tcg/cpu-ops.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 69f4808ac4..979ce90eb0 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_spec= ific_ss) =20 specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'watchpoint.c', 'tcg-accel-ops.c', 'tcg-accel-ops-mttcg.c', 'tcg-accel-ops-icount.c', @@ -30,4 +29,5 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'= ], if_true: files( system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', + 'watchpoint.c', )) --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373914; cv=none; d=zohomail.com; s=zohoarc; b=jhM/P6nVZjqJyatK0YXZz95Z22DlF8RfICJatOmdMBImNtEfOQnZUEx+tlBW5ZqAYKIff0DP0dTCyO0V0pbURPiSKY28hPDqSi0bfm0re8ECT2k7lnpr72/18kY4cyzSRtcfMMDRlaIQiPiHy5Ero0jueUz6bggIdwFLg+vfoNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373914; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=k6rq6CIIqovi+rqTbWr+nZgRpCqEfphmlSslf2GR3LU=; b=IPhm7MjVVJNf73AS0ybKpUga0TndfJc0j9eA/bHu0ISXg9MH3Eo8m0xtY8zHrJmFn0Qo2BotmcloGvppFw7aq9dbkWkZw2rWAQJ05tMq43fCnqnkj5Vqu7Ol6RH5F5DaT49m5ot2JoGSESCVZ+L34zZDyNzFWeBva4aJd3IGnAM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373914859224.05342806569058; Fri, 7 Mar 2025 10:58:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsX-0007UF-Mm; Fri, 07 Mar 2025 13:57:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsP-0007Rg-Vu for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:54 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsN-0007lh-Np for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:53 -0500 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-2feb91a2492so4019101a91.2 for ; Fri, 07 Mar 2025 10:56:51 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373810; x=1741978610; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k6rq6CIIqovi+rqTbWr+nZgRpCqEfphmlSslf2GR3LU=; b=ApNry4HTsE4L5IdCITjCRkk4QHvKn5RWgFtJV+7RXL79FlqWTkPTk88rEVNsGNu2Zw LXcyolFnOJiGJqKBFzpcqsoAR9je1LjjsoRYc9JAHvzCSQBSgP25b2ynf0uafbOaZeJB I9Eh4lSTMmhDovl2mIcdyF4QbnweHAbPPjByXIL/Grv4qbbq9rzlhny2hGxfaPG+Gpz6 zfPuWzpo3kccyP5rrxGCneOQwoCXRZ+TpY3g3Q9Ad1Lm+5qG6vgPA5FQknGYrjgPz/Y2 v20X7qm2ySO4gAcij5IjxzzUS24KZUyrVW2Frz2kW1ctrK2Xksxw1SJTBuKyAhiPxX3O f+ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373810; x=1741978610; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k6rq6CIIqovi+rqTbWr+nZgRpCqEfphmlSslf2GR3LU=; b=UMBgtaAMes1YNtZ2h1Ge6uiXLjbD7KcWSb/ElH751nbl98durYsCpOBnQfYTcSx31F 5d4NEXcUKBR2U8cDp07d6pP9E7JQ7ATgJsMEwEsLO3zzcu9VeWg30iFbV6yyYAOLjFiT Z3t8SdT4UP4jeD6JT4R8BXN15bF1RvCjFUsySxcVGR88+xOderTwWChRMyLc/v7acl4y Im3VYaJwNNHuNYKbhcQGyis7mr5LMSld+UAJ7UrXqdyfjuYotF2w65R1IQfcrkfwI7jZ vg7RLHckckVswbN3QHJ7zBmGmNT0mjj/G3nP8UOiRoJtZe/GkaF/B1z0NFeAeRl4bn3c 0Ong== X-Gm-Message-State: AOJu0Yx40Mi4E3twn8rdIQE64sJQ4Wyqb18c8CQdRsdYPPjEO1aD3dHY +y5D+7egTny25B6aCZIYsbnUYwAYoV0X3ytmuXE/KNnxbCO0N9VxibtNDA8WKaYuJoqRLxOQKax e X-Gm-Gg: ASbGncs6tbIt8WQJim40AkZ43r/xZrhwUeeNcVYnE4KP0k1F0WaBO88QWCiPSaNsfed xD/+LHgMGu5QeTcxL5apW7P76hUDFcHjE0uLeS+/CuTtqX7pBgKhi22wwkS88Hsudylf6h5UhZI Icn1n0O/x11oJ4WPmdpL5cHkKVv28QSjeDoLwBUX1sWiBw18MluLadK4S5pTizSrIPgZAFtbSJF bLKEbnGc/L1e3DuMxmjvFXOU9mSYJEcPx9dxnuG0GdV7YuzNha6Xbk0sHi0uqw7uA4cjWr4w3Ba uLumFKe92LCxwR+goZUdeirx3+IeVCgHXZDc6sdGKKg1yJ9cEkmGC8/7VHi5vvdesdWYMsq2/+k 3 X-Google-Smtp-Source: AGHT+IHm3ACmK48dcxvecCMc0q8ObbimEvoFT+PEBg5oQDTvsotjyz6ve+I+ZO6Vqa6s1AQ0+tMkVA== X-Received: by 2002:a17:90a:e7c2:b0:2ee:c91a:ad05 with SMTP id 98e67ed59e1d1-2ff7ce52479mr6405940a91.3.1741373810325; Fri, 07 Mar 2025 10:56:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 03/16] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:32 -0800 Message-ID: <20250307185645.970034-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373915203019000 From: Philippe Mathieu-Daud=C3=A9 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Message-ID: <20241114011310.3615-14-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cputlb.h | 7 +++++++ include/exec/exec-all.h | 3 --- include/exec/ram_addr.h | 1 + system/physmem.c | 1 + 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index ef18642a32..6cac7d530f 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -32,4 +32,11 @@ void tlb_unprotect_code(ram_addr_t ram_addr); =20 #endif /* CONFIG_TCG */ =20 +#ifndef CONFIG_USER_ONLY + +void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); +void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); + +#endif + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 8eb0df48f9..f24256fb5e 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -486,9 +486,6 @@ static inline tb_page_addr_t get_page_addr_code(CPUArch= State *env, =20 #if !defined(CONFIG_USER_ONLY) =20 -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); -void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); - MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, hwaddr *xlat, hwaddr *plen, diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 94bb3ccbe4..3d8df4edf1 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -23,6 +23,7 @@ #include "cpu.h" #include "system/xen.h" #include "system/tcg.h" +#include "exec/cputlb.h" #include "exec/ramlist.h" #include "exec/ramblock.h" #include "exec/exec-all.h" diff --git a/system/physmem.c b/system/physmem.c index 8c1736f84e..a6af555f4b 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -32,6 +32,7 @@ #endif /* CONFIG_TCG */ =20 #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/translation-block.h" --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373870; cv=none; d=zohomail.com; s=zohoarc; b=H/KYf4c8fEC7/HYYKsWFVVmtRtQBuGcAlXxP1KWC7WfpKkIT9FsoY3YArr02sWo185sxvFJ22muXnJbicsaB9Uo+U1Vi+uq54QDg4AGiEiVrdyo8lGRAySeRYAby6Hgu/eHhr0rTeuzKIQt0vkCkzfP2OrVklAvpXkdSY2PRiWA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373870; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SzyDViup58ROLXi9a5eLqmvAZgtt4FP4fwTvGjoaRo8=; b=GelAyffMnL+tuTqrMbEuAIhXKq00kTgsIaDp1qvQyJoZO8S/yS2FxwAYDlcSxpA6t1HxjR749ZH3EFvM9K0WUENSgr2kF5QtQvadZdHnwRgU3/NrV97lt7Z7czNJSUss6l1YomSxZbkXf7PHsqZklf2ke7xp1xNuyUEtNBY12Ik= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373870781225.91121682510288; Fri, 7 Mar 2025 10:57:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsW-0007U8-Ib; Fri, 07 Mar 2025 13:57:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsQ-0007Rj-ED for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:54 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsO-0007m1-GG for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:54 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2235908a30aso15234785ad.3 for ; Fri, 07 Mar 2025 10:56:52 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373811; x=1741978611; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SzyDViup58ROLXi9a5eLqmvAZgtt4FP4fwTvGjoaRo8=; b=DywH/P87pkGFFqMRxJ7xn6GRLtOnOdrrX0ym/RwcEANRUHBq7APug8TCsdVZx5OtE2 ho45EyhEZfKedbyo+D9mKm3uOslz9zi5h36ErRrVztTdjYgs/d3ygVqIF2D9hui7jRMo L+g34Ogado4luUc0bH7SzDsHungxD6OvYYVHZtPzlfwGhj0xDhWhOzW/6mKUydJDTbxI WTFJfzfMJeTOZR4tDp4J9c3aDm397Uuyax16+ya+avu8hVoO64vLaV95bVdzDMrWN0kL Njnm7DnMoR4yopWHlwhy+eGI+LEBPYKwDxAPPmncHmSmlFQBuXXQZu6zJA+yiqUGyAfx mR+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373811; x=1741978611; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SzyDViup58ROLXi9a5eLqmvAZgtt4FP4fwTvGjoaRo8=; b=BgMs+5RJ8QykdonwP5ODZbmodKptPcd5VJkNesbapQBTwq38nyoR6wg3UhpNP3SfzZ +hkDuaK35LKdAyXO73MTprOjz1mzlWZ72lDstWWY3FWT2NTbx32tTi2k4dw0Pt4qGhha l49LYa4UNEqvqxiEf/K3BqmGznLG+lfLiSM4Wbe/6WPuehpFKAn2iMjrkI3CNs2jHKcl 7PaBlVdRG5uM9qnETZ8SfUyjcZj+EnIbCoL1pCr4YpZbtBpp4ISx3ZpqynrC1cbYyXje Z3a04yn/BqwZU9hJkVWTbwBL7tXWByQM0aUwvUJAjF+Bq2mTv+DpmqFfEObWtC7GhRpd kqGg== X-Gm-Message-State: AOJu0Yz+CzvNXRU9yLaJYRe0JM8jCGNKAgn8IMMnVgwIMnjC6hmWs5mn T1V1FMnlRNjbKPTtmN8Z65tkphgo5EhqlGda+mA7YeTZUzh3OQpz9duLtTSoQMKn99KJefPBGze h X-Gm-Gg: ASbGncvLFfK+oqV52fnFxKQZq24ryrAWzBffERaUeKGj1/7RSEhavypSDkCdgmA4Tfm +9SO+rxZgd3QwQxaZ4SJGBRK2W+8LzFlCEnO8HZ1IqjAN8z/zPdKOTRBgR/PhPsRgkMDISpcSDe vb1yP7UcXMKRKjOlEgxm6R+YrK2NWu9ODCyeJZzCA5nmYj2GxamlWBWPE3ai/OkRWemlteO76IU 1Zy/M5ZNiGSCCsu+BVESFJtOD1t/uVMU1WrzOvyqnr6/cRf9H2LNLlvit22cXM7mA6G/v3hdfXW rlb9QdFyPtD8fCMBdrQY0tIXZdn4Xx9wHWcBCZHq3eS//TYSzDmqMTxZhTIIKIzhtwy7G92L/LQ S X-Google-Smtp-Source: AGHT+IHHWMIx9HNmHaffyTP2HpiJ/yDQRPiibxBLg45i8lTaa1UT1sXFbutkrSYnD8yZrerMKPYwUA== X-Received: by 2002:a17:902:e5ce:b0:224:26f5:9c1e with SMTP id d9443c01a7336-22428880333mr69820735ad.2.1741373811125; Fri, 07 Mar 2025 10:56:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 04/16] exec: Declare tlb_set_page_full() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:33 -0800 Message-ID: <20250307185645.970034-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373873523019100 From: Philippe Mathieu-Daud=C3=A9 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-16-philmd@linaro.org> --- include/exec/cputlb.h | 23 +++++++++++++++++++++++ include/exec/exec-all.h | 22 ---------------------- target/sparc/mmu_helper.c | 2 +- 3 files changed, 24 insertions(+), 23 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 6cac7d530f..733ef012d1 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,7 @@ #define CPUTLB_H =20 #include "exec/cpu-common.h" +#include "exec/vaddr.h" =20 #ifdef CONFIG_TCG =20 @@ -39,4 +40,26 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_add= r_t length); =20 #endif =20 +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @addr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, + CPUTLBEntryFull *full); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f24256fb5e..f43c67366b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -156,28 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 -/** - * tlb_set_page_full: - * @cpu: CPU context - * @mmu_idx: mmu index of the tlb to modify - * @addr: virtual address of the entry to add - * @full: the details of the tlb entry - * - * Add an entry to @cpu tlb index @mmu_idx. All of the fields of - * @full must be filled, except for xlat_section, and constitute - * the complete description of the translated page. - * - * This is generally called by the target tlb_fill function after - * having performed a successful page table walk to find the physical - * address and attributes for the translation. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only - * used by tlb_flush_page. - */ -void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, - CPUTLBEntryFull *full); - /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 9ff06026b8..7548d01777 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/qemu-print.h" #include "trace.h" --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373963; cv=none; d=zohomail.com; s=zohoarc; b=k3/3XDHa6OFblcR/POa3kMEHDXzwoZNWBXf6uBgsGGHY1ujmZuGBq76HcJPQdqYPBNh81KGe5KC9dgmiZboqkw65CbNG+Jh+fCu6jKiDMvkwj066pOtTSb1kEES6ixUXNfrIV17yniu+5CeNeS57dOE6h0xb00C3zYddVUU1eA0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373963; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OZUhu3BnFzDT2DJGeBZFOFqKQQp7EogeXchL7RAMkqI=; b=F6WqycBSIY2f89NIQVGub/UUMl5Bo/9iU3Zlh4rakvUB7Z6yUVggvmEOfrVIzCiQvzeAqWRBSKgtyevkbQcLsVVvWAtbetsQyyYKM0UgdT77cevlAusP5f2JFTAM0HvooiPxpovdwyhppR3yfawtbjiHrw4ZrWdgbnOg0p77x7Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373963122223.96723446630403; Fri, 7 Mar 2025 10:59:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcse-0007XL-Pw; Fri, 07 Mar 2025 13:57:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsR-0007S6-25 for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:56 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsP-0007mC-2V for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:54 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2fee05829edso4743171a91.3 for ; Fri, 07 Mar 2025 10:56:52 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373812; x=1741978612; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OZUhu3BnFzDT2DJGeBZFOFqKQQp7EogeXchL7RAMkqI=; b=TjFxp62lW6qfz2KMRvOfTFrngP/swyyxTDqLTVU9VmcS2EzN/2r6STr/RjbgutX5wu ay9jP/RSBa24CzrCpzaln6YtEvqU+pLKKzt6jrvB3Vd+Qp94DFWUTcjtT0EbW5JuANZA sL/gJYkQbNti4S9yTkjEcTmOPYId01lWeHbOGOtRfUzXQMU7/E79PJyOPqIaAkA9Y2I9 TYEePamAwscer3rpgB8wq7I677QKsOTlBlfuPaThe7hrmgrhTUFQs9K+FBnocuhmLEWG 2HNZpCnmAoOSC7PB3vDCBGhUlrMKei1reDJBRLYou7F6XpwHZLppWNXZMESLHufOmajU vciw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373812; x=1741978612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OZUhu3BnFzDT2DJGeBZFOFqKQQp7EogeXchL7RAMkqI=; b=BpMCSHsiY/8zdt2FS0T916/2SurcljnTXuakUmhLupR35CbU9WuRk4NbHk3sjm/15u m7kT6tijffyT4YGEUNUqcB/MjH5mCCXOqBCqldDTUfu2xqSjEttjRFeXniGKsA961oTC PC4fL/lgICljTAt4mFzNpnr6ry8sNPtCoAIcWOQ3BgmTZgate+MXBUFSDmZkRkBnqxD3 arVsx2cNSvkiZp3z2wKjBDdNUDcdXWEAcBkVtwWTgE2c000ffn4RfRzA/qvzZBct50Aq tMFm1e1H8PYTNQgF1BG6MfV9LPLrPqPYe1Dhe6BJRToD4wMcZGMralFASj2hO6AuOXOU ZGTg== X-Gm-Message-State: AOJu0YxGf6m+ygIFTPjgReVemckjk1wUqJ1fa5VIQbZ2PgSVWV1f2OvA obs2gxMw3vadYpOPfCWUjidSMqHOpshaVJTM9AdD9CbcWkxlRzIAfLfm4YZ5nl5HphArg/em5NP N X-Gm-Gg: ASbGnctSq08v1xIBZjrg90DlvFph77ltrX4RHOfklGK1hNw1q7SzW7JLXmlfVL1uAWj W5fSNx0V8tVoyABTWCPmk4wVO4SCQBBptYEVWpOR0DBSXy+oPbDmbRdwpE0jwkJ4pzqt7pcDMZn Tq/uDlD9NwbOQ2TUaDP3rZs5JhTyENmLuAEXd3YqpuZSGMhWoIz339bL+cIvn8sphf2wy0Unwk1 3Yi+pYlEcy0H0+BdhB7hPfgkQtGb8Xx38GMgv8PJ+gY/N43oyEouWlVt44kmSoELgMDYbbcSeQs QRwVwuP4C+N0lDBYBxirJLqddIuq4McjxO5LR8NH11u9lOnaZrYKAFb3XFtytfHHqowlAcZd948 u X-Google-Smtp-Source: AGHT+IFN1/MYxbnPD7Vm9r+4vYkKdXRttulS8CDzGXr81qKZMEL6KXrgWiLqGjvM6FgPkqFZbS9AnA== X-Received: by 2002:a17:90b:3804:b0:2ee:edae:75e with SMTP id 98e67ed59e1d1-2ff7ce77a3fmr7203085a91.13.1741373811734; Fri, 07 Mar 2025 10:56:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 05/16] exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:34 -0800 Message-ID: <20250307185645.970034-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373965715019100 From: Philippe Mathieu-Daud=C3=A9 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-17-philmd@linaro.org> --- include/exec/cputlb.h | 28 ++++++++++++++++++++++++++++ include/exec/exec-all.h | 25 ------------------------- target/i386/tcg/system/excp_helper.c | 2 +- target/microblaze/helper.c | 2 +- 4 files changed, 30 insertions(+), 27 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 733ef012d1..56dd05a148 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,8 @@ #define CPUTLB_H =20 #include "exec/cpu-common.h" +#include "exec/hwaddr.h" +#include "exec/memattrs.h" #include "exec/vaddr.h" =20 #ifdef CONFIG_TCG @@ -62,4 +64,30 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_add= r_t length); void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, CPUTLBEntryFull *full); =20 +/** + * tlb_set_page_with_attrs: + * @cpu: CPU to add this TLB entry for + * @addr: virtual address of page to add entry for + * @paddr: physical address of the page + * @attrs: memory transaction attributes + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @mmu_idx: MMU index to insert TLB entry for + * @size: size of the page in bytes + * + * Add an entry to this CPU's TLB (a mapping from virtual address + * @addr to physical address @paddr) with the specified memory + * transaction attributes. This is generally called by the target CPU + * specific code after it has been called through the tlb_fill() + * entry point and performed a successful page table walk to find + * the physical address and attributes for the virtual address + * which provoked the TLB miss. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only + * used by tlb_flush_page. + */ +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f43c67366b..62d6300752 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -156,31 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 -/** - * tlb_set_page_with_attrs: - * @cpu: CPU to add this TLB entry for - * @addr: virtual address of page to add entry for - * @paddr: physical address of the page - * @attrs: memory transaction attributes - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) - * @mmu_idx: MMU index to insert TLB entry for - * @size: size of the page in bytes - * - * Add an entry to this CPU's TLB (a mapping from virtual address - * @addr to physical address @paddr) with the specified memory - * transaction attributes. This is generally called by the target CPU - * specific code after it has been called through the tlb_fill() - * entry point and performed a successful page table walk to find - * the physical address and attributes for the virtual address - * which provoked the TLB miss. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only - * used by tlb_flush_page. - */ -void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, vaddr size); /* tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index 864e3140e3..6876329de2 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "tcg/helper-tcg.h" =20 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5d3259ce31..27fc929bee 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -20,7 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/host-utils.h" #include "exec/log.h" --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373949; cv=none; d=zohomail.com; s=zohoarc; b=Wa4y+pieV3ME03DVCoaNvOck1nqByhfjGR5w3iHBp2Taimd6o6aD7K3Hu5FoIPY/UVNUhLbYEwzzKY4YlO4+LpTRS91+BqtAbg5OhTWUyp9UrzgJAKyhdyH7P2DysfQ0ZLxNGS5y/RW8DBkC72nLiikySUnsMEC91m7vZMe94ao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373949; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4u5PBwHEPecUaxrqA3yTEFMGllvxnHxvoZEJcDTq3Zs=; b=mb+C38eGsm9UUu4EwPW0FOM1wMnKI4ptN3Bmb9l7z5A8rTL0p3Tl5WTmpMFkDyTmVZTAMaXDtPYz4/DKm0WzVOZgb02AthiyTgCoud7PiPLH90r7LHQLWYXthOjzGUfUlnpJ9+LMsXM+q2LETqqAuBPMs2IkgK3qk7995d3WSFs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174137394945552.27789215700284; Fri, 7 Mar 2025 10:59:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcse-0007XG-6b; Fri, 07 Mar 2025 13:57:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsS-0007SP-K5 for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:57 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsQ-0007me-7f for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:56 -0500 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-2fec13a4067so3599481a91.2 for ; Fri, 07 Mar 2025 10:56:53 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373812; x=1741978612; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4u5PBwHEPecUaxrqA3yTEFMGllvxnHxvoZEJcDTq3Zs=; b=a4iDSzYSuNBtLPs7rpIbeNUmuvOPz5m5Kb52cduEsfGKb4jkc2+uGkMOWYC/P45ywM 1BAFXsVHUPzBIS4k0hvvy/5AJRsUvqtn43QTVFkt3GNgPE9wv0VIv0jX5aaAlI98rb21 3/ZuDjCkihwvu1dQkGnkHR1bqzkJvSiljOwiy8pLlQc7TSGwrFuoJM4smmIt1D3mheum ObLZv3w3TpuAPt5Eru9oAq0bhRtEmdcocioBXOYUpnAYC/o77w59yXVwCprXgq7ANYSS Db4IVgY3W6jriL3bQKPhuxMbH9JJ0I55NnrUCnc7Ke45KFQARLMpGtnA9nUMAtIJAOsn U2Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373812; x=1741978612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4u5PBwHEPecUaxrqA3yTEFMGllvxnHxvoZEJcDTq3Zs=; b=Svsou+rXqxInIyTPPus9aytMrNk0AFo3YVagqZEqDFnaZ6VLzuvtFvMaYOLFl+cC7n mZreIBVnsE2VP9VwIZMotI9rkaLL2Nz984xdGD7aMZa2Qv/4dG1qRRE7FugjR9CvCR0Y 0p5jETNoFiji4Z0ZOGazIfO1jRsJfv9zhswn4lYSP9U2363OTnpXFngb/MDnTdoihlbk Uw7X6+yBwQ9cULBJKIHQmj7DAr70+hTdaJldNCCi5+KYNOD8Ot5TlDZvAmtNyHLaRqpd cjVCU97KqHoALpOoKvClrXBaQ2MRMYyf4R63HymcgGfYCUcrhttYJVV4PsrnW9PLNp4o jUFw== X-Gm-Message-State: AOJu0YzsADAz8aEEpY5yAT7wHt8kVr/fb/JU4ftGlV9GZdqhDKUrbgnC z/MW8J0JEc/04rGDDSx/TQI3zXln+loRmCbgE2LQYPZ/LUYC1paHijUoXefkgakgEP9kxDrwzKb 5 X-Gm-Gg: ASbGncsl78Z9n01uKkcJ59Kl6b3otF7/51xYQxar4kp2K4upBciBh0ezmsIasaKF/Q/ qXQB/hZTnjcxb+MnyIONmIa3i29tMQseflkxnGn75tPZgrhogO2CVDIKr1X8I1cvfup8IOyTzXo r/qsxSbHESpgxO3wQEWNCuBvAK7VGbiaQRKMebrLJIVijdN6VftIkEZzL/6m3CRWhEGIobMMiqw xzsQjjmdU06gsdQfDKEJ9hk1g1O5nBnd2RtEAoDJFudZxpzpgkxJcqYn8XuCKhM/bAALTQbg95s T+0uLMN+R35qVJVP7WPx2W8e+pT4vTUEAXO4sMaCQcCtFvHoE8bXQMym/c3JDrg+17hhp8yWg8r k X-Google-Smtp-Source: AGHT+IHWAcIkzpAWk8/jzv5PiqZoXlGOX+LUKRAMNAGQkv0X4GwFy2Se9h2SOhfVzp11F3Hgfnh5yg== X-Received: by 2002:a17:90b:4a:b0:2fe:a8b1:7d8 with SMTP id 98e67ed59e1d1-2ff7cefbc78mr7391097a91.25.1741373812397; Fri, 07 Mar 2025 10:56:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 06/16] exec: Declare tlb_set_page() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:35 -0800 Message-ID: <20250307185645.970034-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373951768019100 From: Philippe Mathieu-Daud=C3=A9 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-18-philmd@linaro.org> --- include/exec/cputlb.h | 11 +++++++++++ include/exec/exec-all.h | 9 --------- target/alpha/helper.c | 2 +- target/avr/helper.c | 2 +- target/loongarch/tcg/tlb_helper.c | 1 + target/m68k/helper.c | 1 + target/mips/tcg/system/tlb_helper.c | 1 + target/openrisc/mmu.c | 2 +- target/ppc/mmu_helper.c | 1 + target/riscv/cpu_helper.c | 1 + target/rx/cpu.c | 2 +- target/s390x/tcg/excp_helper.c | 1 + target/sh4/helper.c | 1 + target/tricore/helper.c | 2 +- target/xtensa/helper.c | 2 +- 15 files changed, 24 insertions(+), 15 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 56dd05a148..cdfaf17403 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -90,4 +90,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, vaddr size); =20 +/** + * tlb_set_page: + * + * This function is equivalent to calling tlb_set_page_with_attrs() + * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided + * as a convenience for CPUs which don't use memory transaction attributes. + */ +void tlb_set_page(CPUState *cpu, vaddr addr, + hwaddr paddr, int prot, + int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 62d6300752..a3aa8448d0 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -156,15 +156,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 -/* tlb_set_page: - * - * This function is equivalent to calling tlb_set_page_with_attrs() - * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided - * as a convenience for CPUs which don't use memory transaction attributes. - */ -void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, - int mmu_idx, vaddr size); #else static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2f1000c99f..57cefcba14 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index 9ea6870e44..3412312ad5 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,7 +23,7 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index a323606e5a..f6b63c7224 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -12,6 +12,7 @@ #include "cpu.h" #include "internals.h" #include "exec/helper-proto.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index beefeb7069..0bf574830f 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/gdbstub.h" diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index e98bb95951..ca4d6b27bc 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -21,6 +21,7 @@ =20 #include "cpu.h" #include "internal.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index c632d5230b..47ac783c52 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index a802bc9c62..ad9ba8294c 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -24,6 +24,7 @@ #include "kvm_ppc.h" #include "mmu-hash64.h" #include "mmu-hash32.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/log.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 34092f372d..6c4391d96b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "internals.h" #include "pmu.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "instmap.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 1c40c8977e..f01e069a90 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -21,7 +21,7 @@ #include "qapi/error.h" #include "cpu.h" #include "migration/vmstate.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/translation-block.h" #include "hw/loader.h" diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 4c0b692c9e..f969850f87 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "s390x-internal.h" #include "tcg_s390x.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index b8774e046e..7567e6c8b6 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" =20 #include "cpu.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/log.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 9898752eb0..a64412e6bd 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -19,7 +19,7 @@ #include "qemu/log.h" #include "hw/registerfields.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f64699b116..4824b97e37 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -28,7 +28,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373985; cv=none; d=zohomail.com; s=zohoarc; b=BymXIdC0hsTfW9911/Qz+aZifW3jzZpPOd8pZQ8Efal+q8VpIo04YxtfpEWPH2kTP91irQ/UmP3P9a9VpeEHNwDf8lyi6d7FNRBDPfOKPPFuAaxbLtYBs2k79aFQSotQlip4FXkPQ6NdjdhTYWyJMwFxG3WkG0D+CF+deYoGXxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373985; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20241114011310.3615-20-philmd@linaro.org> --- include/exec/cpu-all.h | 23 ----------------------- accel/tcg/cputlb.c | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 9e6724097c..8cd6c00cf8 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -179,29 +179,6 @@ static inline int cpu_mmu_index(CPUState *cs, bool ife= tch) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); =20 -/** - * tlb_hit_page: return true if page aligned @addr is a hit against the - * TLB entry @tlb_addr - * - * @addr: virtual address to test (must be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) -{ - return addr =3D=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); -} - -/** - * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr - * - * @addr: virtual address to test (need not be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) -{ - return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); -} - #endif /* !CONFIG_USER_ONLY */ =20 /* Validate correct placement of CPUArchState. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c8761683a0..fb22048876 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1201,6 +1201,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr, prot, mmu_idx, size); } =20 +/** + * tlb_hit_page: return true if page aligned @addr is a hit against the + * TLB entry @tlb_addr + * + * @addr: virtual address to test (must be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) +{ + return addr =3D=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); +} + +/** + * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr + * + * @addr: virtual address to test (need not be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) +{ + return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); +} + /* * Note: tlb_fill_align() can trigger a resize of the TLB. * This means that all of the caller's prior references to the TLB table --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373979; cv=none; d=zohomail.com; s=zohoarc; b=Gxrzb0lV/G/PmqFMuiYGLGz3Jzr2wobPV7qangOoWgdTWHkyfxcxB4ux88wCnvLSuAIG7fmw3yNIj9FOBVH+2qjw+IIJG95Y5VW+cgEuWCamN70u3S3Owp8gsw3y2tgn8BjFil6+ficeKb+MUyBkZ4a6/WxiwsCGTzr0Za8x5Rw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373979; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+PiHnQ+1q+MwLFjoc0q+vLnYcSz+0aCBgyfQrhPwFSE=; b=U4ezdXFPM4um6+UHxjyVNnKWos1bdbftkiswUckAthwDt+mzq5OTd733QSesuP/jvsq0KkPpMOoQK/DYaINCM65dSw4PsIT3BPWFAeghcnQJq4vXQuZgqN+Ju1mVG8OX1x11cdZtuyVVl+WAw6TnTKddbw1ZE4JRPulCwKaAZmM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373979552169.92910857917946; Fri, 7 Mar 2025 10:59:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsb-0007Vu-6b; Fri, 07 Mar 2025 13:57:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsW-0007UB-P1 for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:57:00 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsS-0007nR-Bu for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:57:00 -0500 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-2ff6a98c638so4296330a91.0 for ; Fri, 07 Mar 2025 10:56:54 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373814; x=1741978614; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+PiHnQ+1q+MwLFjoc0q+vLnYcSz+0aCBgyfQrhPwFSE=; b=q0Awfi/0u5fSpnYNDiH4RHSZzixNGbEnhgp675F8MLW3W+gfc3kaA1bThDhshu4WU5 EpgOrkiyAIjSspCIGljWHMosZ/fLDLTsHH0Ya39O6frnEKQphu/EwOLkGqqrA98YqV20 zkOH74HUcp2C+RDJkRDe+gjVXMusGkPeeIPKHQiCISvyIcB7OIDjtsN9uUNHON03mjBj SdmcLY42WGHNSfDQkgWtLU55Lel14YviXYgwHWsqLvcCS3i7+oUt4kVKDX4mASoi7F0c C8ZmUgbu8JznBUxKQV65FAvhGUn5A4haVoz6Azr9VqVcyd82nHQLNkCTPCT0ZgaeY4+W rOiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373814; x=1741978614; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+PiHnQ+1q+MwLFjoc0q+vLnYcSz+0aCBgyfQrhPwFSE=; b=Bag3izS06YQ+WmKM0vYfyXjUeOTKk0eUhuuvGsDqJ7YnhfsQHsd5eB2psMTVoOgENc 9LA7GxHSkUQZ+ktUJUMf8n9MpYQ9ZgAGOlT3Cm/ReB1a7f4lDm+uuduf35JPtc0qTThO oJt8ZXHgi99UnDxEK/A9WilB4yZ+PTYNQJYHuJgrl/sbNn9QMOWfOx+oyUR6WUGxW1cA /qWKNt7tDqBFfJq6uWdiQg528aSxYu5aQVCf2AiMqA36HGvS68EZ9aF+BM7sZiHj/JyU 5XzxTzeJ+VYHVc7A/Us67oc8CAD3vNbdcPqIS/XbqBeuarrm29K2AFqugWivWwJmUqja loGg== X-Gm-Message-State: AOJu0YxQVm8VkWNXP9gmV3UPWJWSx+aVCRF3UX5WXXgh8mTet0Xn8X0H aZX7S51joFLy8ZH0Bm0VUHERf3XDmAh5EL+/SmUw3R+ozeCh6B0PEuUmw9qHXfLIm4Gdi+D+jqn P X-Gm-Gg: ASbGncs2dHhzqIbstJsoGW/DG5WcuKd5/ThMVaAm7J0yHKl38cPE6mRv6NKEahl+zIo o/RXbsjCzhwiIrhtsW6rfjK44b5Z8j2uOUXBKa/SoJvANSBLT76qomtS2SSw0I6ecfV+72qQmYY 7NnubgKA1O8e5sRfM6w78YK4a1SA4NHWbKS7hhxQNOE9zZ0IhfC+LQ1zyzhY3IxkPYm3uZXYgoD 6sgtWZiYSNMkqXPHdeHwpZQH9JVtaqcBmxi/SSXuHUoUHfqlRTuh3lo6BrQ+0RTEj9ZMZzHmDfP wedN+KWHX1hFUFlk4udgsIsH4lGStvh3IA6oQN3fbE7ethk+oUA5+wNFxSU/iUSMlpvs4Yb68Su v X-Google-Smtp-Source: AGHT+IHAP61/hSZgoSsHvsBMCrodEwe2ZuEUCuxxP1bAQJZZT6W8VH/ILw0aZpkq0B/r3pO46SXKEA== X-Received: by 2002:a17:90b:1d52:b0:2ff:6f88:b04a with SMTP id 98e67ed59e1d1-2ff7ce8222emr7341880a91.15.1741373813760; Fri, 07 Mar 2025 10:56:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, Pierrick Bouvier Subject: [PATCH 08/16] exec: Declare tlb_flush*() in 'exec/cputlb.h' Date: Fri, 7 Mar 2025 10:56:37 -0800 Message-ID: <20250307185645.970034-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373980134019000 From: Philippe Mathieu-Daud=C3=A9 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Message-ID: <20241114011310.3615-19-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cputlb.h | 200 +++++++++++++++++++++++++-- include/exec/exec-all.h | 184 ------------------------ accel/tcg/tcg-accel-ops.c | 2 +- cpu-target.c | 1 + hw/intc/armv7m_nvic.c | 2 +- hw/ppc/spapr_nested.c | 1 + hw/sh4/sh7750.c | 1 + system/watchpoint.c | 3 +- target/alpha/sys_helper.c | 2 +- target/arm/helper.c | 1 + target/arm/tcg/tlb-insns.c | 2 +- target/hppa/mem_helper.c | 1 + target/i386/helper.c | 2 +- target/i386/machine.c | 2 +- target/i386/tcg/fpu_helper.c | 2 +- target/i386/tcg/misc_helper.c | 2 +- target/i386/tcg/system/misc_helper.c | 2 +- target/i386/tcg/system/svm_helper.c | 2 +- target/loongarch/tcg/csr_helper.c | 2 +- target/microblaze/mmu.c | 2 +- target/mips/system/cp0.c | 2 +- target/mips/tcg/system/cp0_helper.c | 2 +- target/openrisc/sys_helper.c | 1 + target/ppc/helper_regs.c | 2 +- target/ppc/misc_helper.c | 1 + target/riscv/csr.c | 1 + target/riscv/op_helper.c | 1 + target/riscv/pmp.c | 2 +- target/s390x/gdbstub.c | 2 +- target/s390x/sigp.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/s390x/tcg/misc_helper.c | 1 + target/sparc/ldst_helper.c | 1 + target/xtensa/mmu_helper.c | 1 + 34 files changed, 224 insertions(+), 211 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index cdfaf17403..8125f6809c 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -25,21 +25,14 @@ #include "exec/memattrs.h" #include "exec/vaddr.h" =20 -#ifdef CONFIG_TCG - -#if !defined(CONFIG_USER_ONLY) -/* cputlb.c */ +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); #endif =20 -#endif /* CONFIG_TCG */ - #ifndef CONFIG_USER_ONLY - void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); - #endif =20 /** @@ -101,4 +94,193 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); =20 -#endif +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) +/** + * tlb_flush_page: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of the specified CPU, for all + * MMU indexes. + */ +void tlb_flush_page(CPUState *cpu, vaddr addr); + +/** + * tlb_flush_page_all_cpus_synced: + * @cpu: src CPU of the flush + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of all CPUs, for all + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); + +/** + * tlb_flush: + * @cpu: CPU whose TLB should be flushed + * + * Flush the entire TLB for the specified CPU. Most CPU architectures + * allow the implementation to drop entries from the TLB at any time + * so this is generally safe. If more selective flushing is required + * use one of the other functions for efficiency. + */ +void tlb_flush(CPUState *cpu); + +/** + * tlb_flush_all_cpus_synced: + * @cpu: src CPU of the flush + * + * Flush the entire TLB for all CPUs, for all MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_all_cpus_synced(CPUState *src_cpu); + +/** + * tlb_flush_page_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_page_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @wait: If true ensure synchronisation by exiting the cpu_loop + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_page_bits_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * Similar to tlb_flush_page_mask, but with a bitmap of indexes. + */ +void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr ad= dr, + uint16_t idxmap, + unsigned bits); + +/** + * tlb_flush_range_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of the start of the range to be flushed + * @len: length of range to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), + * comparing only the low @bits worth of each virtual page. + */ +void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits); +#else +static inline void tlb_flush_page(CPUState *cpu, vaddr addr) +{ +} +static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr add= r) +{ +} +static inline void tlb_flush(CPUState *cpu) +{ +} +static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) +{ +} +static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, + vaddr addr, uint16_t idxmap) +{ +} + +static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) +{ +} +static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + uint16_t idxma= p) +{ +} +static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, + uint16_t idxmap) +{ +} +static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, + vaddr addr, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void +tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bi= ts) +{ +} +static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxm= ap, + unsigned bits) +{ +} +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ +#endif /* CPUTLB_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a3aa8448d0..a758b7a843 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -27,190 +27,6 @@ #include "exec/mmu-access-type.h" #include "exec/translation-block.h" =20 -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/* cputlb.c */ -/** - * tlb_flush_page: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of the specified CPU, for all - * MMU indexes. - */ -void tlb_flush_page(CPUState *cpu, vaddr addr); -/** - * tlb_flush_page_all_cpus_synced: - * @cpu: src CPU of the flush - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of all CPUs, for all - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); -/** - * tlb_flush: - * @cpu: CPU whose TLB should be flushed - * - * Flush the entire TLB for the specified CPU. Most CPU architectures - * allow the implementation to drop entries from the TLB at any time - * so this is generally safe. If more selective flushing is required - * use one of the other functions for efficiency. - */ -void tlb_flush(CPUState *cpu); -/** - * tlb_flush_all_cpus_synced: - * @cpu: src CPU of the flush - * - * Flush the entire TLB for all CPUs, for all MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_all_cpus_synced(CPUState *src_cpu); -/** - * tlb_flush_page_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_page_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @wait: If true ensure synchronisation by exiting the cpu_loop - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); -/** - * tlb_flush_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); - -/** - * tlb_flush_page_bits_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * Similar to tlb_flush_page_mask, but with a bitmap of indexes. - */ -void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_page_bits_by_mmuidx_all_cpus_synced - (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); - -/** - * tlb_flush_range_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of the start of the range to be flushed - * @len: length of range to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), - * comparing only the low @bits worth of each virtual page. - */ -void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits); - -#else -static inline void tlb_flush_page(CPUState *cpu, vaddr addr) -{ -} -static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr add= r) -{ -} -static inline void tlb_flush(CPUState *cpu) -{ -} -static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) -{ -} -static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, - vaddr addr, uint16_t idxmap) -{ -} - -static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) -{ -} -static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - uint16_t idxma= p) -{ -} -static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, - uint16_t idxmap) -{ -} -static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, - vaddr addr, - uint16_t idxmap, - unsigned bits) -{ -} -static inline void -tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bi= ts) -{ -} -static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxm= ap, - unsigned bits) -{ -} -#endif - #if defined(CONFIG_TCG) =20 /** diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 132c5d1461..53e580d128 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -33,7 +33,7 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "qemu/timer.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" #include "exec/translation-block.h" diff --git a/cpu-target.c b/cpu-target.c index 5aa6c4b0c6..b6e66d5ac0 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -31,6 +31,7 @@ #include "exec/tswap.h" #include "exec/replay-core.h" #include "exec/cpu-common.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" #include "exec/log.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5fd0760982..7212c87c68 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -22,7 +22,7 @@ #include "system/runstate.h" #include "target/arm/cpu.h" #include "target/arm/cpu-features.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/memop.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 7def8eb73b..23958c6383 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" #include "hw/ppc/spapr.h" diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 8892eaddcb..6faf0e3ca8 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -36,6 +36,7 @@ #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "trace.h" =20 typedef struct SH7750State { diff --git a/system/watchpoint.c b/system/watchpoint.c index 2aa2a9ea63..08dbd8483d 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -19,7 +19,8 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" +#include "exec/target_page.h" #include "hw/core/cpu.h" =20 /* Add a watchpoint. */ diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 54ee93f34c..51e3254428 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/helper-proto.h" #include "system/runstate.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 71dead7241..e786c8df5f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -18,6 +18,7 @@ #include "qemu/timer.h" #include "qemu/bitops.h" #include "qemu/qemu-print.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/translation-block.h" #include "hw/irq.h" diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index fadc61a76e..630a481f0f 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -7,7 +7,7 @@ */ #include "qemu/osdep.h" #include "qemu/log.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "cpu.h" #include "internals.h" #include "cpu-features.h" diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 304f0b61e2..fb1d93ef1f 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 3bc15fba6e..c07b1b16ea 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qapi/qapi-events-run-state.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/translation-block.h" #include "system/runstate.h" #ifndef CONFIG_USER_ONLY diff --git a/target/i386/machine.c b/target/i386/machine.c index d9d4f25d1a..70f632a36f 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1,6 +1,6 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "hw/isa/isa.h" #include "migration/cpu.h" #include "kvm/hyperv.h" diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4858ae9a5f..c1184ca219 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,7 +21,7 @@ #include #include "cpu.h" #include "tcg-cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index ed4cda8001..2b5f092a23 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper-tcg.h" =20 /* diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/= misc_helper.c index c9c4d42f84..ce18c75b9f 100644 --- a/target/i386/tcg/system/misc_helper.c +++ b/target/i386/tcg/system/misc_helper.c @@ -23,7 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "tcg/helper-tcg.h" #include "hw/i386/apic.h" =20 diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/s= vm_helper.c index 5f95b5227b..f9982b72d1 100644 --- a/target/i386/tcg/system/svm_helper.c +++ b/target/i386/tcg/system/svm_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "tcg/helper-tcg.h" =20 diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 6c95be9910..84f7ff25f6 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -12,7 +12,7 @@ #include "internals.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "hw/irq.h" #include "cpu-csr.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 2423ac6172..f8587d5ac4 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" =20 static unsigned int tlb_decode_size(unsigned int f) diff --git a/target/mips/system/cp0.c b/target/mips/system/cp0.c index bae37f515b..ff7d3db00c 100644 --- a/target/mips/system/cp0.c +++ b/target/mips/system/cp0.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" =20 /* Called for updates to CP0_Status. */ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/c= p0_helper.c index 79a5c833ce..01a07a169f 100644 --- a/target/mips/tcg/system/cp0_helper.c +++ b/target/mips/tcg/system/cp0_helper.c @@ -27,7 +27,7 @@ #include "internal.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" =20 =20 /* SMP helpers. */ diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 77567afba4..21bc137ccc 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "exception.h" #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 3ad4273c16..f211bc9830 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/main-loop.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "system/kvm.h" #include "system/tcg.h" #include "helper_regs.h" diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index f0ca80153b..e379da6010 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0ebcca4597..49566d3c08 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -25,6 +25,7 @@ #include "pmu.h" #include "time_helper.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "system/cpu-timers.h" #include "qemu/guest-random.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f156bfab12..0d4220ba93 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "trace.h" diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 85ab270dad..b0841d44f4 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -24,7 +24,7 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" =20 static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6879430adc..6bca376f2b 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "s390x-internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/gdbstub.h" #include "gdbstub/helpers.h" #include "qemu/bitops.h" diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index cf53b23291..6a4d9c5081 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -15,6 +15,7 @@ #include "system/hw_accel.h" #include "system/runstate.h" #include "exec/address-spaces.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "system/tcg.h" #include "trace.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index ea9fa64d6b..8187b917ba 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -26,6 +26,7 @@ #include "exec/helper-proto.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 0245451472..31266aeda4 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/timer.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "qapi/error.h" #include "tcg_s390x.h" diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 4c54e45655..b559afc9a9 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -24,6 +24,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #ifdef CONFIG_USER_ONLY diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 29b84d5dbf..63be741a42 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -32,6 +32,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" =20 --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373916; cv=none; d=zohomail.com; s=zohoarc; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373814; x=1741978614; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=13ZFhLiBHBjpoAqV9uKZaMKlyYRJeq7eTuuvmkqTawA=; b=MJHLb+4qdZheBqrNvc+rfUB/yzNXmhOxppiTeY5oedFF2ty/4gKjGLGM9qxGron3nC b2UQEMe76KkzWjiePnblvuH2ANwyFQAzk3AEMjdyrjdwLPIVoQOUrwRDjNmwnQH6BEwD 68Kd3uaC8GnqcjUPvabBlTUEveFhvzGd/jcKs/HK0WiMEGz/Yc7dxIH0FS4TnE7QLslJ hllIHqPZcvtz2zmnn4c3NrHct9o2CufA+nQXwbsUiVAaegD5Kn7e3hyFcsBq1CjSbhqu v/XIJHoF49O5++GP4M5PPrcIv3EBQ6zXjiEsD2YB5XQr6pUS4zNha5j4HT2jru4s2HH5 a3pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373814; x=1741978614; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=13ZFhLiBHBjpoAqV9uKZaMKlyYRJeq7eTuuvmkqTawA=; b=k+QojHKfwt3yNjGYaMtLH7NtZlo3wO3u0Ays2r3w0/TpqLZOk5matEA+gplLv/SlXx mOg8G2dQSprwPdP4CvmNVQb3A0vTN2QqOa3ck7GzH8HfK5s9vAZhBcEBgPpiQknQiUMD 310vMu6K5mZrQACf88OfhE69HptervsHDS5xvBXAfgyQ+M0+27QPeIP5qsFolef8miy0 mCcMDo7ttc+Kpwc+sd/oLWSvApWjXpEqAw0lCY634MeQBLGNBNbjJWIdtJMo9cq+ZjH0 kXeEMq6BDKun/jTZy3Y0jnrbJXpunbFjwzro6oXzcsXFzwyU8Gd3YQ2nZJFd2ZUp2pOI 3Ltg== X-Gm-Message-State: AOJu0YzDmRtX7BPUeZylNVpb8V3BIiibaebRM3cm1lHyzcgNrM//bXVc 1c6x/xnR19BwP8lFzc2r99fgoRFhJE6Exh1hBuAFnzSNBvkEzGbpAP6idmnW7q7jgKdYwu0go8p V X-Gm-Gg: ASbGncsFjQMSH6UIa0S0e9Gt00aZNvtmgJQ9AjEj9ZnH8o5ZAOPKhVYLpMDNc1arA+F eHkvUlOTHnFLfLW0RkrZfQmpMZ56eY+SeQczQ0MM4CcbtMB82f/q3YQTd4TwypChOwngIcPadyI lfhevPd7oUKTLron4nuXq6cp1TU5LeuqpePaKbzULrpLOT8wZ6KIA3Q39gJ1MoSZjwoc9wFDUmI 9qgIiTpcZOsRh/KiT+5uvVD4O+5/ADAYONe/yw9G2Aak8Q3TlIdEs3VQBFaLumKG9X1/pH57rd/ b3q2DiWVjiGWPJeoVyJux4D/Yvez2oMGL4M8NQW2cIR5xHkNMlG/TSUSUYYmNiT3VWXqVJFwL2Y v X-Google-Smtp-Source: AGHT+IEAY/SPgd3nEC+70Ay82umoGARB5I1yeVNjbtP87Prcx09es8xIt2jI2qthEYcfy4pdsVb0Sg== X-Received: by 2002:a17:90b:4cca:b0:2ff:7b28:a51c with SMTP id 98e67ed59e1d1-2ff7cf32cb7mr5728103a91.34.1741373814493; Fri, 07 Mar 2025 10:56:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 09/16] system: Build watchpoint.c once Date: Fri, 7 Mar 2025 10:56:38 -0800 Message-ID: <20250307185645.970034-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373917161019000 Content-Type: text/plain; charset="utf-8" Now that watchpoint.c uses cputlb.h instead of exec-all.h, it can be built once. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Tested-by: Philippe Mathieu-Daud=C3=A9 --- system/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/meson.build b/system/meson.build index 4952f4b2c7..c83d80fa24 100644 --- a/system/meson.build +++ b/system/meson.build @@ -3,7 +3,6 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files( 'ioport.c', 'memory.c', 'physmem.c', - 'watchpoint.c', )]) =20 system_ss.add(files( @@ -24,6 +23,7 @@ system_ss.add(files( 'runstate.c', 'tpm-hmp-cmds.c', 'vl.c', + 'watchpoint.c', ), sdl, libpmem, libdaxctl) =20 if have_tpm --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373888; cv=none; d=zohomail.com; s=zohoarc; b=g2mRy4Gzv0pMTP5pJK4VrmBPldxNDaKDo90q8TQCqSCTyH3yWVPhhDh40Rat+kjvC5Pp1o37ZZcuiv4CNPc10g5TmMtOV5OzR0Xeb0IHrOmigh/qADt26voaDmXhculhU8DGI3Cg59rmpg1ma1wNuohXSnlUmpPlm9tGXFwgGbw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373888; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YJaPAtjiKCI7xNvYK1z8ajXotpby2ndW32q1olZ40bI=; b=BZGAxyLrDWXYSA7JY5B3VcuBOZkKcajzARLK+VWkydNWnbpoC3HKGZZ/QV07TPsq3qz3gQbj03sgvt92wKI3WAJS6CVbfgIna/bxWPvccLoGpvRHtpDpsPqX1NAiAWAAIOMfYMtDED3rnMuzxCZo3qITjqAYcr3klCw0tgCIOTw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373888663521.8544760856473; Fri, 7 Mar 2025 10:58:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsh-0007YE-Hb; Fri, 07 Mar 2025 13:57:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsV-0007TE-5S for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:59 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsS-0007nh-LT for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:58 -0500 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2ff69365e1dso3416133a91.3 for ; Fri, 07 Mar 2025 10:56:56 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373815; x=1741978615; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YJaPAtjiKCI7xNvYK1z8ajXotpby2ndW32q1olZ40bI=; b=LKy+LO5A3dcrlEDDg490qYWC9j6l36pYZnsEeb3NvVRWJGQhZYoFvKjGQoUkf1Pv4B Vye28e3iMyN8wYTXIfF7jV8vMBevEX0fmEpeb4ALQJV24t8cf60WiEzuD1Zcb5cTJcvj /+m6v5WPuQfLJqFzs72ZU6BrbjK4vX30oy55S4URrMqVMNR+NbajRHRSkX18U96/+yl+ pJy7gLY2n82v1udFKpxfxD0ft11iTJakw16MbsM55yVzP9gVXts/cJjFfaNEEeCz7/fk P2GtsAZT6xSr4vq8g36i0FdN1IItr/WZPqhB2KaLEcYGXXXMbAckDb5V+4fRCK/mxkNc Ogxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373815; x=1741978615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YJaPAtjiKCI7xNvYK1z8ajXotpby2ndW32q1olZ40bI=; b=sV3AoEIj+kZcwevgXWy33XNg5OVzTom2X4M8IpPwTtkr4a9vBgvM6/R7iRGk2Y2Z1B gs4Jsazk+X08irUs2Ae7bghCKi3gDvqa/eP8iYxDnEKcq2IyQxHFpxwNDj0PLqQPXhIJ LjXGV4aTo2YEawqYYyIeciQOtBVmnQoReUE5q9C0wrtqd2zAzvbvqUNhcBCSt57FjLUM mTnUV5bcjX301bpXtnE4OZ7DyhA1ro0VbkOwa9NqJDYHYOlbH/7saxH9v2iiIcLUarlF x5xN/E/UpDoc24RzAtyihbkmWTEw0zOobPiwzLWdvZ7wEadWh1DBlIpXfA85NfghdLRV hToQ== X-Gm-Message-State: AOJu0YxAxnZH1D7VnPNQXOH2hQ3t9NQmCvGHYtMu9J0V7a2Nu/i+0N7e w6i1def56oQS3xNc/xBuKL+h0LfRk6FSDmmg4aaaEULhRt76CaKYThMWo13W4b2rLwpeAhEcW39 a X-Gm-Gg: ASbGncuGgkNAiaMrhoC+xiX/itXXCGL1ex25qRwrnHZdjIwpyxPgPMQL3XqQ4b7aVLk aKCQn171cKMQtt41LQFRJina0si5nxlzMUdEtS3WerT7CdAh77CFKuTt1ei7++c8mcOTY58W4oh aqGfpNMEV/0yCaXbEel2aTNSHKb/JH6P4HYXzt13+D99khBPkOjfYOMPJ+jP7RC8nbL1oV7KjBN MbJDbBzjOCIN22pU+uOc3wmnJ4cmMW5jNOuJm+DoI+FoEhQQCy0a9djylT03dc45MhsV75qiU3+ LVfRun3KIh4hIbhUfxErJRNuUPeOLiKDQ/JiokNWXkub+831UXuJNa6A76azcvFAKZP7P/pSpM5 Q X-Google-Smtp-Source: AGHT+IFc5IBAh3DDbrzfFjHNPAm2YzILwpM4eAQf1qnNkHqFWHnSMAD0qMOwagFPsEQYU8LIpduYgQ== X-Received: by 2002:a17:90b:4c8a:b0:2ee:af31:a7bd with SMTP id 98e67ed59e1d1-2ff7ce4f28amr6637684a91.5.1741373815192; Fri, 07 Mar 2025 10:56:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 10/16] accel/tcg: Build tcg-accel-ops.c once Date: Fri, 7 Mar 2025 10:56:39 -0800 Message-ID: <20250307185645.970034-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373889575019100 Content-Type: text/plain; charset="utf-8" Now that tcg-accel-ops.c uses cputlb.h instead of exec-all.h, it can be built once. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 979ce90eb0..70ada21f42 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_spec= ific_ss) =20 specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'tcg-accel-ops.c', 'tcg-accel-ops-mttcg.c', 'tcg-accel-ops-icount.c', 'tcg-accel-ops-rr.c', @@ -29,5 +28,6 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'= ], if_true: files( system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', + 'tcg-accel-ops.c', 'watchpoint.c', )) --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373908; cv=none; d=zohomail.com; s=zohoarc; b=RDVR/Btr5zqhh1+5dwg7bSmeuqWqxaHt9RL9N/U6/Ks3f64VxuZhNibcE0ulbVDwely7i8FdDqYX0vU1lys3mvfMCw0+p+aR4cVD8PnkMcef4PHL8FZwM6k7Lkg0hik7k4L0032g7yCUb55Xtc3nbryG91qkLbTdVrKZ1Edn1Go= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373908; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yvub9wKD2OmaGYjgLz+dO6qQURDfWdRF4qq4HxWTWTw=; b=OG2lPmj130zgi1sxvCOwlpLicnb7qhrmjjV3XvAjPMvEypbEsy079BE2xdaWGlayy6YGYJyN9CJBWsQJOYBekwUEGsy9GhDEVsTAjcS56ZwgPd61tObyO8s8ST9d3Gq5V399PTzrmj+EhpkUG0bdS+l6ENye/0tXoM/of4vUYMo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174137390871630.337795833209384; Fri, 7 Mar 2025 10:58:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsf-0007XP-4m; Fri, 07 Mar 2025 13:57:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsV-0007TF-5c for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:59 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsT-0007nj-26 for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:58 -0500 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2feb91a25bdso3609191a91.1 for ; Fri, 07 Mar 2025 10:56:56 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373816; x=1741978616; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yvub9wKD2OmaGYjgLz+dO6qQURDfWdRF4qq4HxWTWTw=; b=jv/2R72yKIX63Gwhq8rykNOaecp983dYK9zRFCtavI6zQbj6D9zCHhPkFPA//z1o7E REYrUbAXGWi2nfaDXwRc+RtETiUbjdbtPPK6wPnpkbOC4gPj7ASaRz0Yf7/j9ZhOVPXq qzpUBy8ab/kbHyY3DvuoEjqv9xHxVz2XTMAP8nOIkfQ4by72Q76nPcEhKPu+ehwPlY0K kGgzKOTD/spy1zVl58YPZ3mi3CJBKBDyCFAji6XX2aKCqFJyZvXNSlavwrGkxUMny7aj /AzItJ05H66fTQTmCj3Wl41fZheI2ybiYiqFElSqC3A502IbQMXST5yMHSgB3ElRIKjg U3Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373816; x=1741978616; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yvub9wKD2OmaGYjgLz+dO6qQURDfWdRF4qq4HxWTWTw=; b=as2J1t9wJk1HpAkDE95JobTTrtNfYhLqydmnCrh61pjNE9HEEQij4TZYM7+19lINWz gd4OVaP6jQUU8IFYa6Z72qB3AMLZeWj4e8biXY+PHKqiLJ/NSWVIyfFk1NwvxAZEV08F zgSa0JQ/QRFLSfrU2TQrYyeWvIMxjZsTXcxyqgOVBDWEI1yqY8RTphkiLo8vuSBn6SXl vjq26bgRY7SFk5w+X0Tw0wV7z+fVnqQN9TGsnqsuZwaqjxAd0zr0Bi5N2krW1w6MhANc pGsk41Y3zDQb2wb7VeanvhXV+nussF3GzVAKiuRd5fosd+KIqcbvDiGU/DQeoKPdvLfR ozwQ== X-Gm-Message-State: AOJu0Yw6+Jm/MOyq7WXQ1bkf/q3bqKFbjlQK1OqIKx1mGTrNFgmgz8Fw B10IAvCDmRz/hQc6krkr0CY+uusOi/MNJO6G2etq1QD10TZFW3RHmrWOYG0y8jw1C3EZma3oaYc Q X-Gm-Gg: ASbGncusRWO8QmNmyNfJxu86YCEHcE4CIQk5e+0sTtWLK8Vg5iEY3nO8gsx2scoH5/+ KpgP0LkSZBeqNtvrW5gAh5rz04LFQDfAuixvjhf5mcnLnxdPL3GdzjqN0gS3nITybeh1sV4KZdc qqsk0YmWzqKIreQXv67/wRr12iFMClY9aqJhM2zqA2LLBzgwiQwYAZNkKu9OYUEZZXAHATUu8ub u2mTJ3L/rszLXSbWnSe1IAcH0jdQa21Q8jpCDJnN2RyChB8PCgMKzG4PDDgzQqTwc2ajNEEOlm6 vATVWs1sEFbxu9gsrjL96BkVvvkVGxzhpXkeTyFFOkraw3ZZyAfEmN8wvFBm7gAuOKfD0pUWqqF 8 X-Google-Smtp-Source: AGHT+IGFlBjWP0Mcyc6XGqxDjRWlB3KZf3/AFkQikj0M7vjpnHvybAKT/bX2H9KmYnLRKQ4zGp0NTg== X-Received: by 2002:a17:90b:3c41:b0:2fa:157e:c78e with SMTP id 98e67ed59e1d1-2ff7ce65536mr7470098a91.7.1741373815798; Fri, 07 Mar 2025 10:56:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 11/16] accel/tcg: Build tcg-accel-ops-icount.c once Date: Fri, 7 Mar 2025 10:56:40 -0800 Message-ID: <20250307185645.970034-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373909545019100 Content-Type: text/plain; charset="utf-8" All that is required is to avoid including exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-accel-ops-icount.c | 2 +- accel/tcg/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-ico= unt.c index d6b472a0b0..27cf1044c7 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -28,7 +28,7 @@ #include "system/cpu-timers.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "hw/core/cpu.h" =20 #include "tcg-accel-ops.h" #include "tcg-accel-ops-icount.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 70ada21f42..891b724eb6 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_spec= ific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', 'tcg-accel-ops-mttcg.c', - 'tcg-accel-ops-icount.c', 'tcg-accel-ops-rr.c', )) =20 @@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', 'tcg-accel-ops.c', + 'tcg-accel-ops-icount.c', 'watchpoint.c', )) --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373949; cv=none; d=zohomail.com; s=zohoarc; b=i5weg+CXJsPoEUoWsBxJcpzse5PpSjdIdS4G+Gfl8Ze540YFUka/hKWAjU7etruaSyDaRbs8eJU2FVAjVEOYB3e7CkV/KoxvCE8OJlS6kx2v9USQUs7uNtNPGgKIqPzTbtUC4DrfHK1yrPiDvt4oKUQ+sQCaWchojYaOkA7uYaU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373949; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8xGAU/49OeEOOEzt+6b6VcCQ4H44QO9LUOBmF2tDbf4=; b=O/K6cFgIh1f0r+ELzJY1fE4yEg9FmtDWb54kXc+shuxoA3LTnkkUIYOllhqNjErqRudGfVBGTLmWJEJQYUbMmxAKQi3MfNz6/H0bhJsT2J5qcVXm0+4UliQSb2uZ/fUZbVAXU9LWNG/9X+AZ7dVNS7jA9CvXh4KZOMZH5Ba7u9g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373949102917.1025738594305; Fri, 7 Mar 2025 10:59:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsh-0007YL-LC; Fri, 07 Mar 2025 13:57:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsV-0007TO-Dg for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:59 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsT-0007oE-Pl for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:56:59 -0500 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2f9d3d0f55dso3599772a91.1 for ; Fri, 07 Mar 2025 10:56:57 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373816; x=1741978616; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8xGAU/49OeEOOEzt+6b6VcCQ4H44QO9LUOBmF2tDbf4=; b=Pvry11wzpfe4flGPMP52A+z9+b1TJ+kQy/K41L8FYqfNDRFnqv6dGXAu4+K2hCPT3K Mxj3AAVITxG44u3Eho1szYb8mqPOom91zRsgQhQ/U8Hy64gkUpqaGHw4nA2n6aSbEjaG T/llqL20LcvnZlUEoQb6DOt6ju3eX2g7hceLSZ5HuwqARy2CtrFpVWWgQpjco42QobD9 QKSke+89QH6ukYWStqorCYIg3pGwJKm1QiMfqiWuF5QH8WU2FOD8AnoWb+bqSDE++it2 FW03+5isQ1cY8AFE8WzY65ynvoPnycpJvKBk09Y5Wvgb1M2ghppz+fW9qVNaTINnilBP APUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373816; x=1741978616; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8xGAU/49OeEOOEzt+6b6VcCQ4H44QO9LUOBmF2tDbf4=; b=rvdb4EOfhz8P03rTd7pSuMPHaefiPdhVd2hcp5RiZbe6FO4ekjVxC5KLKFYXV8raSs c4n9XV3/6FsG+72+sAKMy+K6scELWMH05s/2mUAOzO44PCQF3gp8sT/nb3YvpwgUhHUf sSx0Fg/ogfUhskFYLHCOf3IoGxzQZdNyG9KPpBn66QFrrormxBiZAr2I2n6nCaWaxPlu CdP0zFJgVvpRsYhiCw9su5weLwiJAvTnuc79qj+vxosnmW6bbEr0zzmGcJDj1PV9hkj9 f2nhkflwDk6g7c3n2uYdMC+5i7y2jIdcKlEzHmRbbgfAPPSjsLX0UVEi8g7dDOuWFLIP e9/A== X-Gm-Message-State: AOJu0YzTvOg2G43kHQa3HP9uP85lt3bHjMJ46y0ZTZHsmvsox3FTgyW1 wMYCuurfFd8qmnpg/KZ35cimOX141ONZg+DLjlwXX9YNm7o9mOH+JjBXsSuyYTpNN3sZbUedJlD r X-Gm-Gg: ASbGnct/0qfQJl0KF3ioAo+JFinB66wWoHek4YLEG1qSOAPBA0ex5J48k0rTTPKR+8h lRGM9IYHQDnCNJ6RzzAgF3JKWpgzDi2xpGcconMgoenR4Npj9FcWILbafizYJj6HcrWs9y5Wo6l MNqnhV+y36XHrmKMicq/SrQUmx0t6VSd42vXAN1pTTCOdYomIsVfqtXZhtGEmLnXx2L5PTNgRCh bawo9iW8pfcPsSbz3cal/GWvv2SRFfwiaIq9l1UpkJtMH17HPnJmogAyjpomUIlwoK0iTKr4lPE X1bjG5r/6iUaDnsLfZ8tjrYfbHPt7Vf2Y5tdPTXpE1idxOtACOgsJsr902BElTYlapgTdxIOgML a X-Google-Smtp-Source: AGHT+IHdaukiL68NDZCeyfizn0sTf6RGxC+glZ0vHaixzU+W97bEjj+IR1JJaneQtU1NH7YMnAKKoQ== X-Received: by 2002:a17:90b:2d82:b0:2ee:c2b5:97a0 with SMTP id 98e67ed59e1d1-2ff7cf0a651mr7252721a91.25.1741373816466; Fri, 07 Mar 2025 10:56:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 12/16] accel/tcg: Build tcg-accel-ops-rr.c once Date: Fri, 7 Mar 2025 10:56:41 -0800 Message-ID: <20250307185645.970034-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373949840019000 Content-Type: text/plain; charset="utf-8" All that is required is to use cpu-common.h instead of exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 028b385af9..f62cf24e1d 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -31,7 +31,7 @@ #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" +#include "exec/cpu-common.h" #include "tcg/startup.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 891b724eb6..87c1394b62 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -21,7 +21,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_spec= ific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', 'tcg-accel-ops-mttcg.c', - 'tcg-accel-ops-rr.c', )) =20 system_ss.add(when: ['CONFIG_TCG'], if_true: files( @@ -29,5 +28,6 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'monitor.c', 'tcg-accel-ops.c', 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-rr.c', 'watchpoint.c', )) --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373913; cv=none; d=zohomail.com; s=zohoarc; b=DiyyVjUBH4S/VBns1C2kx2/GiH0ieM/jLVRV/P0PecMDbXTQYV/a1OZHzSXubqqHb7HkzJic23GhHjeH/IMffMHD0GrusJitQIAlhWDCvxLEXnHbYjH8hxqO/RQC2jaPGi4mlx4vqtF0kd/BFzONp/upRX7U9yrAMsQoAafnX3w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373913; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+0vlhP+/ciA3q59qQifyZ8D/3OKhNe8zch9jvXIoi5A=; b=fJAusz/O2/9tkhImmeLBfp/P0pMugshelfAy0R4jMl7csN5gq7DyOW91BFhv8Hl5MUpd3eqUU9yy51kWNroBtudSWgXhkhhixTNT9sEFm2eAq3PTDYJ4FwIK82HBnkVboBNXmcE/q15Vqa85piCnObArNh180/l3A7CFVxUMwxE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373913639680.0646580805023; Fri, 7 Mar 2025 10:58:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsa-0007VT-7A; Fri, 07 Mar 2025 13:57:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsW-0007UA-Ga for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:57:00 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsU-0007oT-NJ for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:57:00 -0500 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2fef5c978ccso3558533a91.1 for ; Fri, 07 Mar 2025 10:56:58 -0800 (PST) Received: from stoup.. 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373817; x=1741978617; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+0vlhP+/ciA3q59qQifyZ8D/3OKhNe8zch9jvXIoi5A=; b=w7D/qhWZQZMho6FCx+LirGK9aIkw7zzz1u6E7FiW9MEjUxgkgno9powxby5pqECXL0 zOmNR64RMBjhYADVSut8cS3b5ipmSI3LLkl609BiaKh83LSVUavtt0JH58oNZjkaOh53 8cj/bNeOqWquRrhmrr1JJWY7r88+p9XP+v5T9oFolx3HO0U55I0tcSWLtaz5Ubr/aFAg I3Q+8XGRsvCmZpf8sWhgev1WRE5u0gTL9nAc+WbQjip+Xs9I/SygGF4DcaG+XSZo/G6h Vfvo+piS8tPLimnQa/d9OfaQDIvpLWqHlOcxCOrVNBLaO/UPFHmko1f7DMwj1YlTFprN bvRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373817; x=1741978617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+0vlhP+/ciA3q59qQifyZ8D/3OKhNe8zch9jvXIoi5A=; b=nQnKkx76VxspH7ThEDfMEJt0G/arQBSPwJkaNiXmIeXLWt/s/jquHVeHnywSJwmUyS fs8VAnJ5UbrHTE+ciAQ5/4nruzSQXIDpa6mdvaZucLxr8UStBqg59mZ9JmVk/oRQfiX3 7E/5Hea8e0cnvx+JWvO0q4Dm2i6z90/aeLk9Cd07+bo/vbWtoUwebSRBhWjAg1JdfJ9j 9gPO3cpK2UWcqL46b+B4EMISMmyGALRqGEiXzk0kZA4NOKK8DVuLZng+V6HyQpAtTcj7 KyAB/7MCi8T/4zMhEizvUgzRoYDP3QhyVGpisAtzYW626FuFQtRJTjNNS80R86gK0Bxd 8hKQ== X-Gm-Message-State: AOJu0Yx/XwcTuxk6v5bSu3/QYe4AsbwHehb0ERT9Ajdcv9G/+8A4URxE myQUHpC6XR9Dzrj8s/YS6n8mM6KBxpeK2rs7DGzi2ROT8m773H/e5plC4f9YrO41R0wqe07QO58 F X-Gm-Gg: ASbGncup7PvEb4Lc2sj/QnCJjuuMentmKfWdoaWviCaZYO4Do8zaiT60JJLWfRzJSm5 weRhld+dpBNttfjT8bVDtcLCbhT62vfPKWsHfx5cGD+XmUXuSciCbVLOvSFt6KDxYI4FrZ3aBFL RA51vrdnTrYmQ2jnjabtf6GG46xk3sSNw0viI3tMe6AMRN5lgTerqBHdMa6iaHFPirsUV0LSv9g iFtIZyKy2mTbs+XvgfAX4OIfuuwlmC7yQUfostnPsJacrd2POtDZC8hGp/6HwcRPkf7Nuq6DSKV gdbdtznjBxDzl4+7aUm7OmEpXvSmrC/QfROIfQyqdoFnt6+xTNIgDtK7prCT897bRWVil/Ybu12 z X-Google-Smtp-Source: AGHT+IH/8CGOizvE8NyWoZgHayF8ydxCdXF1WReFxrABEX308VrgXK1eoMG/wFgl40kty6/GIKI7wg== X-Received: by 2002:a17:90b:3911:b0:2ff:5714:6a with SMTP id 98e67ed59e1d1-2ff7ce895fbmr6273140a91.19.1741373817265; Fri, 07 Mar 2025 10:56:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 13/16] accel/tcg: Build tcg-accel-ops-mttcg.c once Date: Fri, 7 Mar 2025 10:56:42 -0800 Message-ID: <20250307185645.970034-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373915532019100 Content-Type: text/plain; charset="utf-8" All that is required is to avoid including exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-accel-ops-mttcg.c | 1 - accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index ba7cf6819d..bdcc385ae9 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -30,7 +30,6 @@ #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" -#include "exec/exec-all.h" #include "hw/boards.h" #include "tcg/startup.h" #include "tcg-accel-ops.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 87c1394b62..81fb25da5c 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,7 +20,6 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_spec= ific_ss) =20 specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'tcg-accel-ops-mttcg.c', )) =20 system_ss.add(when: ['CONFIG_TCG'], if_true: files( @@ -28,6 +27,7 @@ system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'monitor.c', 'tcg-accel-ops.c', 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-mttcg.c', 'tcg-accel-ops-rr.c', 'watchpoint.c', )) --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373862; cv=none; d=zohomail.com; s=zohoarc; b=dmMfgYKIMLYgfyJ/BCPKdahs78VhfdLUPfGqD4aX0PbMqSf7tmX2LSajNi7RnNcPmiNnKfDpqZv3oJICIz4FWzefF+aTCAksJCT2A11XByprA3TY80WLPBWnxKyykmxxLB/yLOZzFPHYBQ7hG63OBDY7R6DdyzO7ZISuoRIChHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373862; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RytMCD0LlZ8TULuAO+TyiQ/M0TGfjDPA2CE/B7x8fYg=; b=RJZYLfSr19yrSX3eSiHJKeOPHDcJ/jYJSX4aW5A4vWSm0qVBQqGuRrMVbSJPgfOPmYsRhf8SE5W4rbPClVT9+JkpveAYZsjaF7QvdLR0OJ1Dw04sr8ziK3sYQRFMetTlTllZBLJiwdA8v8Yx5cTsFC1X5Vb7S9hxG6X9zxrKMPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373862558276.93290821477797; Fri, 7 Mar 2025 10:57:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsc-0007Ww-Hv; Fri, 07 Mar 2025 13:57:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsX-0007US-FR for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:57:01 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsV-0007oZ-HW for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:57:01 -0500 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-2ff087762bbso3426749a91.3 for ; Fri, 07 Mar 2025 10:56:59 -0800 (PST) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/exec-all.h | 19 +------------------ include/exec/helper-getpc.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 18 deletions(-) create mode 100644 include/exec/helper-getpc.h diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a758b7a843..22a99ca502 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -26,6 +26,7 @@ #endif #include "exec/mmu-access-type.h" #include "exec/translation-block.h" +#include "exec/helper-getpc.h" =20 #if defined(CONFIG_TCG) =20 @@ -177,24 +178,6 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_= addr_t page_addr); void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); =20 -/* GETPC is the true target of the return instruction that we'll execute. = */ -#if defined(CONFIG_TCG_INTERPRETER) -extern __thread uintptr_t tci_tb_ptr; -# define GETPC() tci_tb_ptr -#else -# define GETPC() \ - ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) -#endif - -/* The true return address will often point to a host insn that is part of - the next translated guest insn. Adjust the address backward to point to - the middle of the call insn. Subtracting one would do the job except f= or - several compressed mode architectures (arm, mips) which set the low bit - to indicate the compressed mode; subtracting two works around that. It - is also the case that there are no host isas that contain a call insn - smaller than 4 bytes, so we don't worry about special-casing this. */ -#define GETPC_ADJ 2 - #if !defined(CONFIG_USER_ONLY) =20 /** diff --git a/include/exec/helper-getpc.h b/include/exec/helper-getpc.h new file mode 100644 index 0000000000..1c8bd72c11 --- /dev/null +++ b/include/exec/helper-getpc.h @@ -0,0 +1,31 @@ +/* + * Get host pc for helper unwinding. + * + * Copyright (c) 2003 Fabrice Bellard + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef HELPER_GETPC_H +#define HELPER_GETPC_H + +/* GETPC is the true target of the return instruction that we'll execute. = */ +#if defined(CONFIG_TCG_INTERPRETER) +extern __thread uintptr_t tci_tb_ptr; +# define GETPC() tci_tb_ptr +#else +# define GETPC() \ + ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) +#endif + +/* + * The true return address will often point to a host insn that is part of + * the next translated guest insn. Adjust the address backward to point to + * the middle of the call insn. Subtracting one would do the job except f= or + * several compressed mode architectures (arm, mips) which set the low bit + * to indicate the compressed mode; subtracting two works around that. It + * is also the case that there are no host isas that contain a call insn + * smaller than 4 bytes, so we don't worry about special-casing this. + */ +#define GETPC_ADJ 2 + +#endif /* HELPER_GETPC_H */ --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1741373920; cv=none; d=zohomail.com; s=zohoarc; b=Jn8LcNczAVdNzw6F8db0deOMGOBLWdgOh/rk3bRZbCpqYBavrqjtgmWkpsy8W5TuqxPfk3uqX1Fa3sr1JkQLsnTvZq1cASC3Wp/mICrlfex/vuRtAhop2AGgo7f1yR5nEpbGCzGW6tuKRunWe+QrsQhCu373GMaU91O7uM//D1c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741373920; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=b/kc5PC1uGwC95AZ8XXvOvpXwja1rKXIUn6SjN0F6p4=; b=Nx2BZVshyH32ZkpMMvVRp3bnGN5VZ5k4UHkQmHW3XhG+tLE9gcWHPZWTzyEreaTG5sU5/4GrRUvp52a9Bxd8Bnm668MOfbCIpYcrQH6v1lJEbKkaTLLxDmSJwj0ewDQhvFcaqz0eewGl+J/lybSYlImIBaaE5gY/kw4RSLa0wbU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741373920391331.20735680913117; Fri, 7 Mar 2025 10:58:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqcsk-0007Z5-Cl; Fri, 07 Mar 2025 13:57:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqcsX-0007UU-LE for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:57:01 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tqcsW-0007pA-1o for qemu-devel@nongnu.org; Fri, 07 Mar 2025 13:57:01 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-22359001f1aso56337425ad.3 for ; Fri, 07 Mar 2025 10:56:59 -0800 (PST) Received: from stoup.. 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Fri, 07 Mar 2025 10:56:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 15/16] accel/tcg: Build tcg-runtime.c once Date: Fri, 7 Mar 2025 10:56:44 -0800 Message-ID: <20250307185645.970034-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373923542019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-runtime.c | 8 ++------ accel/tcg/meson.build | 2 +- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 9fa539ad3d..72c4c6bd31 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -23,13 +23,9 @@ */ #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "cpu.h" +#include "exec/cpu-common.h" #include "exec/helper-proto-common.h" -#include "exec/cpu_ldst.h" -#include "exec/exec-all.h" -#include "disas/disas.h" -#include "exec/log.h" -#include "tcg/tcg.h" +#include "exec/helper-getpc.h" =20 #define HELPER_H "accel/tcg/tcg-runtime.h" #include "exec/helper-info.c.inc" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 81fb25da5c..411fe28dea 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,5 +1,6 @@ common_ss.add(when: 'CONFIG_TCG', if_true: files( 'cpu-exec-common.c', + 'tcg-runtime.c', )) tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(files( @@ -7,7 +8,6 @@ tcg_specific_ss.add(files( 'cpu-exec.c', 'tb-maint.c', 'tcg-runtime-gvec.c', - 'tcg-runtime.c', 'translate-all.c', 'translator.c', )) --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 07 Mar 2025 10:56:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 16/16] accel/tcg: Build tcg-runtime-gvec.c once Date: Fri, 7 Mar 2025 10:56:45 -0800 Message-ID: <20250307185645.970034-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1741373921520019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Tested-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tcg-runtime-gvec.c | 1 - accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index afca89baa1..ff927c5dd8 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "cpu.h" #include "exec/helper-proto-common.h" #include "tcg/tcg-gvec-desc.h" =20 diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 411fe28dea..38ff227eb0 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,13 +1,13 @@ common_ss.add(when: 'CONFIG_TCG', if_true: files( 'cpu-exec-common.c', 'tcg-runtime.c', + 'tcg-runtime-gvec.c', )) tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', 'cpu-exec.c', 'tb-maint.c', - 'tcg-runtime-gvec.c', 'translate-all.c', 'translator.c', )) --=20 2.43.0 From nobody Sun Nov 16 09:20:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ff693534f8sm3391917a91.17.2025.03.07.10.56.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 10:56:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741373808; x=1741978608; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L5b/Oejd0mTwwlW1J+0jZU46/YaPksZa78jQ92shGik=; b=NZjFxMbiJnCe7OFWxTCfer08Y75CrfFyE9ye2h4e5z2BffX4HYSLBbscVBujFVlRBZ fVSn1aUaZqrmuBE+E06/D8YlkxppI955j7JaqUBhG0WLk6X84GYAbesxVH4yJoD07K/6 Pg+sgZbsLmbhLKUHicSXr7NvtfSIsHc8pc7glpNcg6Eeg6HEnIrLFCkAZaUpmwNr6LDW 1GjGJ4FqQl2kODPjmKOAFQij65k2fPEeKikZH2z31dDgNTz/UGzuEun/65Jy6nxAmmWc 7iIIU7FtSV6uSMjq5DGgD7gtEj5WyAcVqWHdq0u2liAMwCjrkXT3FKxAY5rI9ABDzCyh xgGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741373808; x=1741978608; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L5b/Oejd0mTwwlW1J+0jZU46/YaPksZa78jQ92shGik=; b=Oweh59GnSUvzZEE/jOTUVOpTD5PwheM2YFtEa06TQrGUkcy8pbagsq3YQVc30gvtle PFhrEZ5pEMeXzxUBlTsEWF28dPYn5TJptzC1Kah+WY783af+VNHuaZrVP0EB26ymg38C S6+sQbEPOu6MkjPiYOUfV8N17i1+m3mJePkfVVmufKb8iWwtad23ZGMPoneHGGFaZkNj BrkvV9Eo5W+YJkhFba8DAP+T5mmLVhIKjLy/VGpl5vQntbldyppggT+2qNhY/jH9I3b9 5zJ81fM1T1xRjRhsPkSP7xeuxaTIE9yjx7a3jPIcQ8LFzwjyFxRLJ5gk1c/0YAl+tGRD O9gw== X-Gm-Message-State: AOJu0YwZ5fbr6lwEHKVetOGnXGn5vdMKv5gd0Fnl8t9sBJxs4LO3N7us XVohQmX4fL3kALYguPLoa2CFo1cIIKceFRGzAeZbwQ5SGdgPkzWf+X29BUFAsP2X9avYGywIIOZ D X-Gm-Gg: ASbGncvb+vOmmnhE8B0sqHbUtlO6cosZYOXpFEZ2aJbhLxFrrxfKk+jOn/In7ajpdzi VheUETCQ0vyh4rOLmP121UftcGiMm3Z8gmYst63+5Ld9k5bYpw3gh7y84hgzkfxS7FXpgAD6Vdy hRwzZSqenY/UXjmhfZYPmZnt+xCisavz+ttBZMLafmgwUJoQxnJ5AFB7fch8RfuWEVK5piNBMEV y69v6qrwGr7WkwRyEfzTflj+1krit4jKktbc9Y2Unpb2CTf02AU0bLwRmp1uCFUcuefSZxw7pif KsboNhFpXvCy2pztuIRP41/YUfWkiHnIRdOSSY/WltOaFRYCjnXYkw3AL661PMwpYUGLNoR8rdB D X-Google-Smtp-Source: AGHT+IGxqRVkTw0z2OwhtYHb0KfpaLwYFeIosgZ1FGZ4vBWP2WG5+ntedd7BY53I3HlVgEW27Mkhtw== X-Received: by 2002:a17:90b:3b4a:b0:2fa:603e:905c with SMTP id 98e67ed59e1d1-2ffbc147913mr987991a91.2.1741373808069; Fri, 07 Mar 2025 10:56:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH] include/exec: Move TARGET_PAGE_{SIZE, MASK, BITS} to target_page.h Date: Fri, 7 Mar 2025 10:56:29 -0800 Message-ID: <20250307185645.970034-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307185645.970034-1-richard.henderson@linaro.org> References: <20250307185645.970034-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1741373851218019000 Content-Type: text/plain; charset="utf-8" Re-use the TARGET_PAGE_BITS_VARY mechanism to define TARGET_PAGE_SIZE and friends when not compiling per-target. Inline qemu_target_page_{size,mask,bits} as they are now trivial. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- After this, we could in fact remove qemu_target_page_foo(), etc. We certainly don't need to convert any more uses of TARGET_PAGE_FOO. r~ --- include/exec/cpu-all.h | 21 +------------- include/exec/poison.h | 5 ---- include/exec/target_page.h | 58 ++++++++++++++++++++++++++++++++++---- page-target.c | 18 ------------ page-vary-target.c | 2 ++ 5 files changed, 55 insertions(+), 49 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 09f537d06f..8f7aebb088 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -105,26 +105,7 @@ static inline void stl_phys_notdirty(AddressSpace *as,= hwaddr addr, uint32_t val =20 /* page related stuff */ #include "exec/cpu-defs.h" -#ifdef TARGET_PAGE_BITS_VARY -# include "exec/page-vary.h" -extern const TargetPageBits target_page; -# ifdef CONFIG_DEBUG_TCG -# define TARGET_PAGE_BITS ({ assert(target_page.decided); \ - target_page.bits; }) -# define TARGET_PAGE_MASK ({ assert(target_page.decided); \ - (target_long)target_page.mask; }) -# else -# define TARGET_PAGE_BITS target_page.bits -# define TARGET_PAGE_MASK ((target_long)target_page.mask) -# endif -# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) -#else -# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS -# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) -# define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) -#endif - -#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) +#include "exec/target_page.h" =20 CPUArchState *cpu_copy(CPUArchState *env); =20 diff --git a/include/exec/poison.h b/include/exec/poison.h index f4283f693a..ce43a12965 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -44,11 +44,6 @@ #pragma GCC poison TARGET_FMT_ld #pragma GCC poison TARGET_FMT_lu =20 -#pragma GCC poison TARGET_PAGE_SIZE -#pragma GCC poison TARGET_PAGE_MASK -#pragma GCC poison TARGET_PAGE_BITS -#pragma GCC poison TARGET_PAGE_ALIGN - #pragma GCC poison CPU_INTERRUPT_HARD #pragma GCC poison CPU_INTERRUPT_EXITTB #pragma GCC poison CPU_INTERRUPT_HALT diff --git a/include/exec/target_page.h b/include/exec/target_page.h index 98ffbb5c23..8e89e5cbe6 100644 --- a/include/exec/target_page.h +++ b/include/exec/target_page.h @@ -14,10 +14,56 @@ #ifndef EXEC_TARGET_PAGE_H #define EXEC_TARGET_PAGE_H =20 -size_t qemu_target_page_size(void); -int qemu_target_page_mask(void); -int qemu_target_page_bits(void); -int qemu_target_page_bits_min(void); - -size_t qemu_target_pages_to_MiB(size_t pages); +/* + * If compiling per-target, get the real values. + * For generic code, reuse the mechanism for variable page size. + */ +#ifdef COMPILING_PER_TARGET +#include "cpu-param.h" +#include "exec/target_long.h" +#define TARGET_PAGE_TYPE target_long +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_TYPE int +#endif + +#ifdef TARGET_PAGE_BITS_VARY +# include "exec/page-vary.h" +extern const TargetPageBits target_page; +# ifdef CONFIG_DEBUG_TCG +# define TARGET_PAGE_BITS ({ assert(target_page.decided); \ + target_page.bits; }) +# define TARGET_PAGE_MASK ({ assert(target_page.decided); \ + (TARGET_PAGE_TYPE)target_page.mask; }) +# else +# define TARGET_PAGE_BITS target_page.bits +# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)target_page.mask) +# endif +# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) +#else +# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS +# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) +# define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)-1 << TARGET_PAGE_BITS) +#endif + +#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) + +static inline size_t qemu_target_page_size(void) +{ + return TARGET_PAGE_SIZE; +} + +static inline int qemu_target_page_mask(void) +{ + return TARGET_PAGE_MASK; +} + +static inline int qemu_target_page_bits(void) +{ + return TARGET_PAGE_BITS; +} + +int qemu_target_page_bits_min(void); +size_t qemu_target_pages_to_MiB(size_t pages); + #endif diff --git a/page-target.c b/page-target.c index 82211c8593..321e43d06f 100644 --- a/page-target.c +++ b/page-target.c @@ -8,24 +8,6 @@ =20 #include "qemu/osdep.h" #include "exec/target_page.h" -#include "exec/cpu-defs.h" -#include "cpu.h" -#include "exec/cpu-all.h" - -size_t qemu_target_page_size(void) -{ - return TARGET_PAGE_SIZE; -} - -int qemu_target_page_mask(void) -{ - return TARGET_PAGE_MASK; -} - -int qemu_target_page_bits(void) -{ - return TARGET_PAGE_BITS; -} =20 int qemu_target_page_bits_min(void) { diff --git a/page-vary-target.c b/page-vary-target.c index 343b4adb95..1b4a9a10be 100644 --- a/page-vary-target.c +++ b/page-vary-target.c @@ -37,5 +37,7 @@ void finalize_target_page_bits(void) { #ifdef TARGET_PAGE_BITS_VARY finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN); +#else + finalize_target_page_bits_common(TARGET_PAGE_BITS); #endif } --=20 2.43.0