From nobody Sat Feb 7 06:20:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1741320424; cv=none; d=zohomail.com; s=zohoarc; b=bBLYQhbULxHgH/KRj5xWG05QitB+nRW2tIEBZNQwyajv7vLJi/kiAy2XZYG/qnKA2hbd5dQYm6qGo3gDsYaazRNpjMufAbkDtd0jXKctIORjF+9uXYlP96kYdBHIDCimTJTCkspSxCduBq+YYcjjGpOtEGMNJe3bVNHRIRSrYo8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1741320424; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=JKpcbyk6MmOVpOvhet6/HkpzDfSSqhizykUwF+3f350=; b=OrAL7H+ENf4/B82TWMQFkvrp+Oj7kDRH3p4cyNoGMYvacBM3EwAg2y5nkHCW9+Z/7uXv91wcfUruXcON/sCOptAUSVF2RTFBGTkAff/ciJ95aCvthfMF51V3IQ6Q8shEMN2lZcjQaCFydAD9D4UkcQqgQGqcBzbQcjdvM/LN0yw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1741320424552659.5381656959972; Thu, 6 Mar 2025 20:07:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tqOsf-0007mU-Qj; Thu, 06 Mar 2025 23:00:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqOsY-0007eu-1M; Thu, 06 Mar 2025 23:00:06 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tqOsV-0004jN-QJ; Thu, 06 Mar 2025 23:00:05 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 7 Mar 2025 11:59:47 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 7 Mar 2025 11:59:47 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v6 06/29] hw/intc/aspeed: Introduce helper functions for enable and status registers Date: Fri, 7 Mar 2025 11:59:15 +0800 Message-ID: <20250307035945.3698802-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307035945.3698802-1-jamin_lin@aspeedtech.com> References: <20250307035945.3698802-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1741320425980019100 The behavior of the enable and status registers is almost identical between INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds "aspeed_intc_enable_handler" functions to handle enable register write behavior and "aspeed_intc_status_handler" functions to handle status register write behavior. No functional change. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/aspeed_intc.c | 191 ++++++++++++++++++++++++------------------ 1 file changed, 108 insertions(+), 83 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index d684b4bb4f..b58a7ee712 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -120,6 +120,112 @@ static void aspeed_intc_set_irq(void *opaque, int irq= , int level) } } =20 +static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset, + uint64_t data) +{ + AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + uint32_t reg =3D offset >> 2; + uint32_t old_enable; + uint32_t change; + uint32_t irq; + + irq =3D (offset & 0x0f00) >> 8; + + if (irq >=3D aic->num_ints) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", + __func__, irq); + return; + } + + /* + * The enable registers are used to enable source interrupts. + * They also handle masking and unmasking of source interrupts + * during the execution of the source ISR. + */ + + /* disable all source interrupt */ + if (!data && !s->enable[irq]) { + s->regs[reg] =3D data; + return; + } + + old_enable =3D s->enable[irq]; + s->enable[irq] |=3D data; + + /* enable new source interrupt */ + if (old_enable !=3D s->enable[irq]) { + trace_aspeed_intc_enable(s->enable[irq]); + s->regs[reg] =3D data; + return; + } + + /* mask and unmask source interrupt */ + change =3D s->regs[reg] ^ data; + if (change & data) { + s->mask[irq] &=3D ~change; + trace_aspeed_intc_unmask(change, s->mask[irq]); + } else { + s->mask[irq] |=3D change; + trace_aspeed_intc_mask(change, s->mask[irq]); + } + + s->regs[reg] =3D data; +} + +static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset, + uint64_t data) +{ + AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); + uint32_t reg =3D offset >> 2; + uint32_t irq; + + if (!data) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__); + return; + } + + irq =3D (offset & 0x0f00) >> 8; + + if (irq >=3D aic->num_ints) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n= ", + __func__, irq); + return; + } + + /* clear status */ + s->regs[reg] &=3D ~data; + + /* + * These status registers are used for notify sources ISR are executed. + * If one source ISR is executed, it will clear one bit. + * If it clear all bits, it means to initialize this register status + * rather than sources ISR are executed. + */ + if (data =3D=3D 0xffffffff) { + return; + } + + /* All source ISR execution are done */ + if (!s->regs[reg]) { + trace_aspeed_intc_all_isr_done(irq); + if (s->pending[irq]) { + /* + * handle pending source interrupt + * notify firmware which source interrupt are pending + * by setting status register + */ + s->regs[reg] =3D s->pending[irq]; + s->pending[irq] =3D 0; + trace_aspeed_intc_trigger_irq(irq, s->regs[reg]); + aspeed_intc_update(s, irq, 1); + } else { + /* clear irq */ + trace_aspeed_intc_clear_irq(irq, 0); + aspeed_intc_update(s, irq, 0); + } + } +} + static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int= size) { AspeedINTCState *s =3D ASPEED_INTC(opaque); @@ -136,11 +242,7 @@ static void aspeed_intc_write(void *opaque, hwaddr off= set, uint64_t data, unsigned size) { AspeedINTCState *s =3D ASPEED_INTC(opaque); - AspeedINTCClass *aic =3D ASPEED_INTC_GET_CLASS(s); uint32_t reg =3D offset >> 2; - uint32_t old_enable; - uint32_t change; - uint32_t irq; =20 trace_aspeed_intc_write(offset, size, data); =20 @@ -154,45 +256,7 @@ static void aspeed_intc_write(void *opaque, hwaddr off= set, uint64_t data, case R_GICINT134_EN: case R_GICINT135_EN: case R_GICINT136_EN: - irq =3D (offset & 0x0f00) >> 8; - - if (irq >=3D aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: = %d\n", - __func__, irq); - return; - } - - /* - * These registers are used for enable sources interrupt and - * mask and unmask source interrupt while executing source ISR. - */ - - /* disable all source interrupt */ - if (!data && !s->enable[irq]) { - s->regs[reg] =3D data; - return; - } - - old_enable =3D s->enable[irq]; - s->enable[irq] |=3D data; - - /* enable new source interrupt */ - if (old_enable !=3D s->enable[irq]) { - trace_aspeed_intc_enable(s->enable[irq]); - s->regs[reg] =3D data; - return; - } - - /* mask and unmask source interrupt */ - change =3D s->regs[reg] ^ data; - if (change & data) { - s->mask[irq] &=3D ~change; - trace_aspeed_intc_unmask(change, s->mask[irq]); - } else { - s->mask[irq] |=3D change; - trace_aspeed_intc_mask(change, s->mask[irq]); - } - s->regs[reg] =3D data; + aspeed_intc_enable_handler(s, offset, data); break; case R_GICINT128_STATUS: case R_GICINT129_STATUS: @@ -203,46 +267,7 @@ static void aspeed_intc_write(void *opaque, hwaddr off= set, uint64_t data, case R_GICINT134_STATUS: case R_GICINT135_STATUS: case R_GICINT136_STATUS: - irq =3D (offset & 0x0f00) >> 8; - - if (irq >=3D aic->num_ints) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: = %d\n", - __func__, irq); - return; - } - - /* clear status */ - s->regs[reg] &=3D ~data; - - /* - * These status registers are used for notify sources ISR are exec= uted. - * If one source ISR is executed, it will clear one bit. - * If it clear all bits, it means to initialize this register stat= us - * rather than sources ISR are executed. - */ - if (data =3D=3D 0xffffffff) { - return; - } - - /* All source ISR execution are done */ - if (!s->regs[reg]) { - trace_aspeed_intc_all_isr_done(irq); - if (s->pending[irq]) { - /* - * handle pending source interrupt - * notify firmware which source interrupt are pending - * by setting status register - */ - s->regs[reg] =3D s->pending[irq]; - s->pending[irq] =3D 0; - trace_aspeed_intc_trigger_irq(irq, s->regs[reg]); - aspeed_intc_update(s, irq, 1); - } else { - /* clear irq */ - trace_aspeed_intc_clear_irq(irq, 0); - aspeed_intc_update(s, irq, 0); - } - } + aspeed_intc_status_handler(s, offset, data); break; default: s->regs[reg] =3D data; --=20 2.43.0